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Diffstat (limited to 'target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch')
-rw-r--r--target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch110
1 files changed, 110 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch
new file mode 100644
index 0000000000..1b3a0d92bf
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch
@@ -0,0 +1,110 @@
+From e49546bf3f255f028d0877ceeb7ed6466fe37d8a Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Mon, 21 Nov 2011 00:53:26 +0100
+Subject: [PATCH 56/84] MIPS: BCM63XX: enable pcie for BCM6362
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 +-
+ arch/mips/pci/pci-bcm63xx.c | 57 +++++++++++++++------
+ 2 files changed, 44 insertions(+), 16 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1223,7 +1223,8 @@
+ /*************************************************************************
+ * _REG relative to RSET_MISC
+ *************************************************************************/
+-#define MISC_SERDES_CTRL_REG 0x0
++#define MISC_SERDES_CTRL_6328_REG 0x0
++#define MISC_SERDES_CTRL_6362_REG 0x4
+ #define SERDES_PCIE_EN (1 << 0)
+ #define SERDES_PCIE_EXD_EN (1 << 15)
+
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -118,35 +118,61 @@ void __iomem *pci_iospace_start;
+ static void __init bcm63xx_reset_pcie(void)
+ {
+ u32 val;
++ u32 reg;
++ u32 mask;
+
+ /* enable clock */
++
++ if (BCMCPU_IS_6328())
++ mask = CKCTL_6328_PCIE_EN;
++ else
++ mask = CKCTL_6362_PCIE_EN;
++
+ val = bcm_perf_readl(PERF_CKCTL_REG);
+- val |= CKCTL_6328_PCIE_EN;
++ val |= mask;
+ bcm_perf_writel(val, PERF_CKCTL_REG);
+
+ /* enable SERDES */
+- val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
++
++ if (BCMCPU_IS_6328())
++ reg = MISC_SERDES_CTRL_6328_REG;
++ else
++ reg = MISC_SERDES_CTRL_6362_REG;
++
++ val = bcm_misc_readl(reg);
+ val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
+- bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
++ bcm_misc_writel(val, reg);
+
+ /* reset the PCIe core */
+- val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
++ if (BCMCPU_IS_6328()) {
++ reg = PERF_SOFTRESET_6328_REG;
++ mask = SOFTRESET_6328_PCIE_MASK | SOFTRESET_6328_PCIE_CORE_MASK
++ | SOFTRESET_6328_PCIE_HARD_MASK;
++ } else {
++ reg = PERF_SOFTRESET_6362_REG;
++ mask = SOFTRESET_6362_PCIE_MASK | SOFTRESET_6362_PCIE_CORE_MASK;
++ }
++ val = bcm_perf_readl(reg);
++ val &= ~mask;
++
++ if (BCMCPU_IS_6328())
++ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
++ else
++ val &= ~SOFTRESET_6362_PCIE_EXT_MASK;
+
+- val &= ~SOFTRESET_6328_PCIE_MASK;
+- val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
+- val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
+- val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
+- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++ bcm_perf_writel(val, reg);
+ mdelay(10);
+
+- val |= SOFTRESET_6328_PCIE_MASK;
+- val |= SOFTRESET_6328_PCIE_CORE_MASK;
+- val |= SOFTRESET_6328_PCIE_HARD_MASK;
+- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++ val |= mask;
++ bcm_perf_writel(val, reg);
+ mdelay(10);
+
+- val |= SOFTRESET_6328_PCIE_EXT_MASK;
+- bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++ if (BCMCPU_IS_6328())
++ val |= SOFTRESET_6328_PCIE_EXT_MASK;
++ else
++ val |= SOFTRESET_6362_PCIE_EXT_MASK;
++
++ bcm_perf_writel(val, reg);
+ mdelay(200);
+ }
+
+@@ -332,6 +358,7 @@ static int __init bcm63xx_pci_init(void)
+
+ switch (bcm63xx_get_cpu_id()) {
+ case BCM6328_CPU_ID:
++ case BCM6362_CPU_ID:
+ return bcm63xx_register_pcie();
+ case BCM6348_CPU_ID:
+ case BCM6358_CPU_ID: