diff options
Diffstat (limited to 'target/linux/brcm47xx/patches-2.6.28')
17 files changed, 2082 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/patches-2.6.28/100-board_support.patch b/target/linux/brcm47xx/patches-2.6.28/100-board_support.patch new file mode 100644 index 0000000000..eb8bf5f7c0 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/100-board_support.patch @@ -0,0 +1,27 @@ +diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h +--- a/arch/mips/include/asm/bootinfo.h ++++ b/arch/mips/include/asm/bootinfo.h +@@ -57,6 +57,12 @@ + #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ + #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ + ++/* ++ * Valid machtype for group Broadcom ++ */ ++#define MACH_GROUP_BRCM 23 /* Broadcom */ ++#define MACH_BCM47XX 1 /* Broadcom BCM47xx */ ++ + #define CL_SIZE COMMAND_LINE_SIZE + + extern char *system_type; +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2061,6 +2061,7 @@ + #define PCI_DEVICE_ID_TIGON3_5906M 0x1713 + #define PCI_DEVICE_ID_BCM4401 0x4401 + #define PCI_DEVICE_ID_BCM4401B0 0x4402 ++#define PCI_DEVICE_ID_BCM4713 0x4713 + + #define PCI_VENDOR_ID_TOPIC 0x151f + #define PCI_DEVICE_ID_TOPIC_TP560 0x0000 diff --git a/target/linux/brcm47xx/patches-2.6.28/110-flash_map.patch b/target/linux/brcm47xx/patches-2.6.28/110-flash_map.patch new file mode 100644 index 0000000000..7d19dfcd1a --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/110-flash_map.patch @@ -0,0 +1,27 @@ +diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig +--- a/drivers/mtd/maps/Kconfig ++++ b/drivers/mtd/maps/Kconfig +@@ -332,6 +332,12 @@ config MTD_CFI_FLAGADM + Mapping for the Flaga digital module. If you don't have one, ignore + this setting. + ++config MTD_BCM47XX ++ tristate "BCM47xx flash device" ++ depends on MIPS && MTD_CFI && BCM47XX ++ help ++ Support for the flash chips on the BCM947xx board. ++ + config MTD_REDWOOD + tristate "CFI Flash devices mapped on IBM Redwood" + depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 ) +diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile +--- a/drivers/mtd/maps/Makefile ++++ b/drivers/mtd/maps/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_PMC_MSP_RAMROOT)+= pmcmsp-ramroot.o + obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o + obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o + obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o ++obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o + obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o + obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o + obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o diff --git a/target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch b/target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch new file mode 100644 index 0000000000..e80f51f000 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch @@ -0,0 +1,93 @@ +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -198,7 +198,6 @@ config MIPS_MALTA + select I8259 + select MIPS_BOARDS_GEN + select MIPS_BONITO64 +- select MIPS_CPU_SCACHE + select PCI_GT64XXX_PCI0 + select MIPS_MSC + select SWAP_IO_SPACE +@@ -1383,13 +1382,6 @@ config IP22_CPU_SCACHE + bool + select BOARD_SCACHE + +-# +-# Support for a MIPS32 / MIPS64 style S-caches +-# +-config MIPS_CPU_SCACHE +- bool +- select BOARD_SCACHE +- + config R5000_CPU_SCACHE + bool + select BOARD_SCACHE +diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c +--- a/arch/mips/kernel/cpu-probe.c ++++ b/arch/mips/kernel/cpu-probe.c +@@ -755,6 +755,8 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) + case PRID_IMP_25KF: + c->cputype = CPU_25KF; + __cpu_name[cpu] = "MIPS 25Kc"; ++ /* Probe for L2 cache */ ++ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + break; + case PRID_IMP_34K: + c->cputype = CPU_34K; +diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile +--- a/arch/mips/mm/Makefile ++++ b/arch/mips/mm/Makefile +@@ -31,6 +31,5 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o + obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o + obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o + obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o +-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o + + EXTRA_CFLAGS += -Werror +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -1121,7 +1121,6 @@ static void __init loongson2_sc_init(void) + + extern int r5k_sc_init(void); + extern int rm7k_sc_init(void); +-extern int mips_sc_init(void); + + static void __cpuinit setup_scache(void) + { +@@ -1175,29 +1174,17 @@ static void __cpuinit setup_scache(void) + #endif + + default: +- if (c->isa_level == MIPS_CPU_ISA_M32R1 || +- c->isa_level == MIPS_CPU_ISA_M32R2 || +- c->isa_level == MIPS_CPU_ISA_M64R1 || +- c->isa_level == MIPS_CPU_ISA_M64R2) { +-#ifdef CONFIG_MIPS_CPU_SCACHE +- if (mips_sc_init ()) { +- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; +- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", +- scache_size >> 10, +- way_string[c->scache.ways], c->scache.linesz); +- } +-#else +- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) +- panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); +-#endif +- return; +- } + sc_present = 0; + } + + if (!sc_present) + return; + ++ if ((c->isa_level == MIPS_CPU_ISA_M32R1 || ++ c->isa_level == MIPS_CPU_ISA_M64R1) && ++ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) ++ panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); ++ + /* compute a couple of other cache variables */ + c->scache.waysize = scache_size / c->scache.ways; + diff --git a/target/linux/brcm47xx/patches-2.6.28/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.28/150-cpu_fixes.patch new file mode 100644 index 0000000000..e3d8899791 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/150-cpu_fixes.patch @@ -0,0 +1,370 @@ +diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h +--- a/arch/mips/include/asm/r4kcache.h ++++ b/arch/mips/include/asm/r4kcache.h +@@ -17,6 +17,20 @@ + #include <asm/cpu-features.h> + #include <asm/mipsmtregs.h> + ++#ifdef CONFIG_BCM47XX ++#include <asm/paccess.h> ++#include <linux/ssb/ssb.h> ++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE))) ++ ++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr)) ++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); }) ++#else ++#define BCM4710_DUMMY_RREG() ++ ++#define BCM4710_FILL_TLB(addr) ++#define BCM4710_PROTECTED_FILL_TLB(addr) ++#endif ++ + /* + * This macro return a properly sign-extended address suitable as base address + * for indexed cache operations. Two issues here: +@@ -150,6 +164,7 @@ static inline void flush_icache_line_indexed(unsigned long addr) + static inline void flush_dcache_line_indexed(unsigned long addr) + { + __dflush_prologue ++ BCM4710_DUMMY_RREG(); + cache_op(Index_Writeback_Inv_D, addr); + __dflush_epilogue + } +@@ -169,6 +184,7 @@ static inline void flush_icache_line(unsigned long addr) + static inline void flush_dcache_line(unsigned long addr) + { + __dflush_prologue ++ BCM4710_DUMMY_RREG(); + cache_op(Hit_Writeback_Inv_D, addr); + __dflush_epilogue + } +@@ -176,6 +192,7 @@ static inline void flush_dcache_line(unsigned long addr) + static inline void invalidate_dcache_line(unsigned long addr) + { + __dflush_prologue ++ BCM4710_DUMMY_RREG(); + cache_op(Hit_Invalidate_D, addr); + __dflush_epilogue + } +@@ -208,6 +225,7 @@ static inline void flush_scache_line(unsigned long addr) + */ + static inline void protected_flush_icache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + protected_cache_op(Hit_Invalidate_I, addr); + } + +@@ -219,6 +237,7 @@ static inline void protected_flush_icache_line(unsigned long addr) + */ + static inline void protected_writeback_dcache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + protected_cache_op(Hit_Writeback_Inv_D, addr); + } + +@@ -339,8 +358,52 @@ static inline void invalidate_tcache_page(unsigned long addr) + : "r" (base), \ + "i" (op)); + ++static inline void blast_dcache(void) ++{ ++ unsigned long start = KSEG0; ++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways; ++ unsigned long end = (start + dcache_size); ++ ++ do { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Index_Writeback_Inv_D, start); ++ start += current_cpu_data.dcache.linesz; ++ } while(start < end); ++} ++ ++static inline void blast_dcache_page(unsigned long page) ++{ ++ unsigned long start = page; ++ unsigned long end = start + PAGE_SIZE; ++ ++ BCM4710_FILL_TLB(start); ++ do { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Hit_Writeback_Inv_D, start); ++ start += current_cpu_data.dcache.linesz; ++ } while(start < end); ++} ++ ++static inline void blast_dcache_page_indexed(unsigned long page) ++{ ++ unsigned long start = page; ++ unsigned long end = start + PAGE_SIZE; ++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; ++ unsigned long ws_end = current_cpu_data.dcache.ways << ++ current_cpu_data.dcache.waybit; ++ unsigned long ws, addr; ++ for (ws = 0; ws < ws_end; ws += ws_inc) { ++ start = page + ws; ++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Index_Writeback_Inv_D, addr); ++ } ++ } ++} ++ ++ + /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ ++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \ + static inline void blast_##pfx##cache##lsize(void) \ + { \ + unsigned long start = INDEX_BASE; \ +@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##lsize(void) \ + \ + __##pfx##flush_prologue \ + \ ++ war \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws, indexop); \ +@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ + \ + __##pfx##flush_prologue \ + \ ++ war \ + do { \ + cache##lsize##_unroll32(start, hitop); \ + start += lsize * 32; \ +@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ ++ war \ ++ \ + __##pfx##flush_prologue \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ +@@ -393,35 +460,37 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) + __##pfx##flush_epilogue \ + } + +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) +- +-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) +-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) ++ ++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) ++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) + + /* build blast_xxx_range, protected_blast_xxx_range */ +-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ ++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \ + static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ + { \ + unsigned long lsize = cpu_##desc##_line_size(); \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ ++ war \ + \ + __##pfx##flush_prologue \ + \ + while (1) { \ ++ war2 \ + prot##cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ +@@ -431,13 +500,13 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ + __##pfx##flush_epilogue \ + } + +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) +-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, ) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, ) + /* blast_inv_dcache_range */ +-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) +-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) ++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, ) + + #endif /* _ASM_R4KCACHE_H */ +diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h +--- a/arch/mips/include/asm/stackframe.h ++++ b/arch/mips/include/asm/stackframe.h +@@ -409,6 +409,10 @@ + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + .set mips3 ++#ifdef CONFIG_BCM47XX ++ nop ++ nop ++#endif + eret + .set mips0 + .endm +diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S +--- a/arch/mips/kernel/genex.S ++++ b/arch/mips/kernel/genex.S +@@ -52,6 +52,10 @@ NESTED(except_vec1_generic, 0, sp) + NESTED(except_vec3_generic, 0, sp) + .set push + .set noat ++#ifdef CONFIG_BCM47XX ++ nop ++ nop ++#endif + #if R5432_CP0_INTERRUPT_WAR + mfc0 k0, CP0_INDEX + #endif +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -34,6 +34,9 @@ + #include <asm/cacheflush.h> /* for run_uncached() */ + + ++/* For enabling BCM4710 cache workarounds */ ++int bcm4710 = 0; ++ + /* + * Special Variant of smp_call_function for use by cache functions: + * +@@ -104,6 +107,9 @@ static void __cpuinit r4k_blast_dcache_page_setup(void) + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache_page = blast_dcache_page; ++ else + if (dc_lsize == 0) + r4k_blast_dcache_page = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -118,6 +124,9 @@ static void __cpuinit r4k_blast_dcache_page_indexed_setup(void) + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed; ++ else + if (dc_lsize == 0) + r4k_blast_dcache_page_indexed = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -132,6 +141,9 @@ static void __cpuinit r4k_blast_dcache_setup(void) + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache = blast_dcache; ++ else + if (dc_lsize == 0) + r4k_blast_dcache = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -647,6 +659,8 @@ static void local_r4k_flush_cache_sigtramp(void * arg) + unsigned long addr = (unsigned long) arg; + + R4600_HIT_CACHEOP_WAR_IMPL; ++ BCM4710_PROTECTED_FILL_TLB(addr); ++ BCM4710_PROTECTED_FILL_TLB(addr + 4); + if (dc_lsize) + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + if (!cpu_icache_snoops_remote_store && scache_size) +@@ -1271,6 +1285,17 @@ static void __cpuinit coherency_setup(void) + * silly idea of putting something else there ... + */ + switch (current_cpu_type()) { ++ case CPU_BCM3302: ++ { ++ u32 cm; ++ cm = read_c0_diag(); ++ /* Enable icache */ ++ cm |= (1 << 31); ++ /* Enable dcache */ ++ cm |= (1 << 30); ++ write_c0_diag(cm); ++ } ++ break; + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: +@@ -1328,6 +1353,15 @@ void __cpuinit r4k_cache_init(void) + break; + } + ++ /* Check if special workarounds are required */ ++#ifdef CONFIG_BCM47XX ++ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) { ++ printk("Enabling BCM4710A0 cache workarounds.\n"); ++ bcm4710 = 1; ++ } else ++#endif ++ bcm4710 = 0; ++ + probe_pcache(); + setup_scache(); + +@@ -1386,5 +1420,13 @@ void __cpuinit r4k_cache_init(void) + #if !defined(CONFIG_MIPS_CMP) + local_r4k___flush_cache_all(NULL); + #endif ++#ifdef CONFIG_BCM47XX ++ { ++ static void (*_coherency_setup)(void); ++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup); ++ _coherency_setup(); ++ } ++#else + coherency_setup(); ++#endif + } +diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c +--- a/arch/mips/mm/tlbex.c ++++ b/arch/mips/mm/tlbex.c +@@ -678,6 +678,9 @@ static void __cpuinit build_r4000_tlb_refill_handler(void) + /* No need for uasm_i_nop */ + } + ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(&p); ++#endif + #ifdef CONFIG_64BIT + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ + #else +@@ -1085,6 +1088,9 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, + struct uasm_reloc **r, unsigned int pte, + unsigned int ptr) + { ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++#endif + #ifdef CONFIG_64BIT + build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ + #else diff --git a/target/linux/brcm47xx/patches-2.6.28/160-kmap_coherent.patch b/target/linux/brcm47xx/patches-2.6.28/160-kmap_coherent.patch new file mode 100644 index 0000000000..383aabf17d --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/160-kmap_coherent.patch @@ -0,0 +1,81 @@ +diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h +--- a/arch/mips/include/asm/cpu-features.h ++++ b/arch/mips/include/asm/cpu-features.h +@@ -101,6 +101,9 @@ + #ifndef cpu_has_pindexed_dcache + #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) + #endif ++#ifndef cpu_use_kmap_coherent ++#define cpu_use_kmap_coherent 1 ++#endif + + /* + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors +diff --git a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h +@@ -0,0 +1,13 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) ++ */ ++#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H ++ ++#define cpu_use_kmap_coherent 0 ++ ++#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */ +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -494,7 +494,7 @@ static inline void local_r4k_flush_cache_page(void *args) + */ + map_coherent = (cpu_has_dc_aliases && + page_mapped(page) && !Page_dcache_dirty(page)); +- if (map_coherent) ++ if (map_coherent && cpu_use_kmap_coherent) + vaddr = kmap_coherent(page, addr); + else + vaddr = kmap_atomic(page, KM_USER0); +@@ -517,7 +517,7 @@ static inline void local_r4k_flush_cache_page(void *args) + } + + if (vaddr) { +- if (map_coherent) ++ if (map_coherent && cpu_use_kmap_coherent) + kunmap_coherent(); + else + kunmap_atomic(vaddr, KM_USER0); +diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c +--- a/arch/mips/mm/init.c ++++ b/arch/mips/mm/init.c +@@ -212,7 +212,7 @@ void copy_user_highpage(struct page *to, struct page *from, + void *vfrom, *vto; + + vto = kmap_atomic(to, KM_USER1); +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapped(from) && !Page_dcache_dirty(from)) { + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); +@@ -234,7 +234,7 @@ void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) + { +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapped(page) && !Page_dcache_dirty(page)) { + void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(vto, src, len); +@@ -252,7 +252,7 @@ void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) + { +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapped(page) && !Page_dcache_dirty(page)) { + void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(dst, vfrom, len); diff --git a/target/linux/brcm47xx/patches-2.6.28/210-b44_phy_fix.patch b/target/linux/brcm47xx/patches-2.6.28/210-b44_phy_fix.patch new file mode 100644 index 0000000000..e526584d1c --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/210-b44_phy_fix.patch @@ -0,0 +1,50 @@ +diff --git a/drivers/net/b44.c b/drivers/net/b44.c +--- a/drivers/net/b44.c ++++ b/drivers/net/b44.c +@@ -384,7 +384,7 @@ static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote) + __b44_set_flow_ctrl(bp, pause_enab); + } + +-#ifdef SSB_DRIVER_MIPS ++#ifdef CONFIG_SSB_DRIVER_MIPS + extern char *nvram_get(char *name); + static void b44_wap54g10_workaround(struct b44 *bp) + { +@@ -2068,6 +2068,28 @@ out: + return err; + } + ++#ifdef CONFIG_SSB_DRIVER_MIPS ++static void b44_wrtsl54gs_workaround(struct b44 *bp) ++{ ++ const char *str; ++ ++ /* ++ * workaround for physical wiring in Linksys WRSL54GS ++ * see https://dev.openwrt.org/ticket/2662 and 3903 ++ * eth1 PHY is probably on BCM5325 switch accessed via eth0 ++ */ ++ str = nvram_get("boardnum"); ++ if (!str) ++ return; ++ if (simple_strtoul(str, NULL, 0) == 42) { ++ bp->phy_addr = B44_PHY_ADDR_NO_PHY; ++ } ++ return; ++} ++#else ++static void b44_wrtsl54gs_workaround(struct b44 *bp) { } ++#endif ++ + static int __devinit b44_get_invariants(struct b44 *bp) + { + struct ssb_device *sdev = bp->sdev; +@@ -2089,6 +2111,8 @@ static int __devinit b44_get_invariants(struct b44 *bp) + * valid PHY address. */ + bp->phy_addr &= 0x1F; + ++ b44_wrtsl54gs_workaround(bp); ++ + memcpy(bp->dev->dev_addr, addr, 6); + + if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ diff --git a/target/linux/brcm47xx/patches-2.6.28/220-bcm5354.patch b/target/linux/brcm47xx/patches-2.6.28/220-bcm5354.patch new file mode 100644 index 0000000000..723e638aea --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/220-bcm5354.patch @@ -0,0 +1,45 @@ +diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c +--- a/drivers/ssb/driver_chipcommon.c ++++ b/drivers/ssb/driver_chipcommon.c +@@ -270,6 +270,8 @@ void ssb_chipco_resume(struct ssb_chipcommon *cc) + void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, + u32 *plltype, u32 *n, u32 *m) + { ++ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354) ++ return; + *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); + *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); + switch (*plltype) { +@@ -293,6 +295,8 @@ void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, + void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, + u32 *plltype, u32 *n, u32 *m) + { ++ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354) ++ return; + *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); + *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); + switch (*plltype) { +diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c +--- a/drivers/ssb/driver_mipscore.c ++++ b/drivers/ssb/driver_mipscore.c +@@ -161,6 +161,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore) + + if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) { + rate = 200000000; ++ } else if (bus->chip_id == 0x5354) { ++ rate = 240000000; + } else { + rate = ssb_calc_clock_rate(pll_type, n, m); + } +diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -1011,6 +1011,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus) + + if (bus->chip_id == 0x5365) { + rate = 100000000; ++ } else if (bus->chip_id == 0x5354) { ++ rate = 120000000; + } else { + rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); + if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ diff --git a/target/linux/brcm47xx/patches-2.6.28/250-ohci-ssb-usb2.patch b/target/linux/brcm47xx/patches-2.6.28/250-ohci-ssb-usb2.patch new file mode 100644 index 0000000000..a3d0481b46 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/250-ohci-ssb-usb2.patch @@ -0,0 +1,73 @@ +diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c +--- a/drivers/usb/host/ohci-ssb.c ++++ b/drivers/usb/host/ohci-ssb.c +@@ -106,10 +106,59 @@ static int ssb_ohci_attach(struct ssb_device *dev) + int err = -ENOMEM; + u32 tmp, flags = 0; + +- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) ++ /* ++ * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE ++ * ++ * The USB core requires a special bit to be set during core ++ * reset to enable host (OHCI) mode. Resetting the SB core in ++ * pcibios_enable_device() is a hack for compatibility with ++ * vanilla usb-ohci so that it does not have to know about ++ * SB. A driver that wants to use the USB core in device mode ++ * should know about SB and should reset the bit back to 0 ++ * after calling pcibios_enable_device(). ++ */ ++ ++ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) { + flags |= SSB_OHCI_TMSLOW_HOSTMODE; ++ ssb_device_enable(dev, flags); ++ } ++ ++ /* ++ * USB 2.0 special considerations: ++ * ++ * 1. Since the core supports both OHCI and EHCI functions, it must ++ * only be reset once. ++ * ++ * 2. In addition to the standard SB reset sequence, the Host Control ++ * Register must be programmed to bring the USB core and various ++ * phy components out of reset. ++ */ ++ ++ else if (dev->id.coreid == SSB_DEV_USB20_HOST) { ++#warning FIX ME need test for core being up & exit ++ ssb_device_enable(dev, 0); ++ ssb_write32(dev, 0x200, 0x7ff); ++ udelay(1); ++ if (dev->id.revision == 1) { // bug in rev 1 ++ ++ /* Change Flush control reg */ ++ tmp = ssb_read32(dev, 0x400); ++ tmp &= ~8; ++ ssb_write32(dev, 0x400, tmp); ++ tmp = ssb_read32(dev, 0x400); ++ printk("USB20H fcr: 0x%0x\n", tmp); ++ ++ /* Change Shim control reg */ ++ tmp = ssb_read32(dev, 0x304); ++ tmp &= ~0x100; ++ ssb_write32(dev, 0x304, tmp); ++ tmp = ssb_read32(dev, 0x304); ++ printk("USB20H shim: 0x%0x\n", tmp); ++ } ++ } ++ else ++ ssb_device_enable(dev, 0); + +- ssb_device_enable(dev, flags); + + hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev, + dev_name(dev->dev)); +@@ -200,6 +249,7 @@ static int ssb_ohci_resume(struct ssb_device *dev) + static const struct ssb_device_id ssb_ohci_table[] = { + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV), + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV), ++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), + SSB_DEVTABLE_END + }; + MODULE_DEVICE_TABLE(ssb, ssb_ohci_table); diff --git a/target/linux/brcm47xx/patches-2.6.28/260-ohci-set-dma-mask.patch b/target/linux/brcm47xx/patches-2.6.28/260-ohci-set-dma-mask.patch new file mode 100644 index 0000000000..7385993ce3 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/260-ohci-set-dma-mask.patch @@ -0,0 +1,15 @@ +diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c +--- a/drivers/usb/host/ohci-ssb.c ++++ b/drivers/usb/host/ohci-ssb.c +@@ -159,6 +159,11 @@ static int ssb_ohci_attach(struct ssb_device *dev) + else + ssb_device_enable(dev, 0); + ++ /* ++ * Set dma mask - 32 bit mask is just an assumption ++ */ ++ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK)) ++ return -EOPNOTSUPP; + + hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev, + dev_name(dev->dev)); diff --git a/target/linux/brcm47xx/patches-2.6.28/270-ehci-ssb.patch b/target/linux/brcm47xx/patches-2.6.28/270-ehci-ssb.patch new file mode 100644 index 0000000000..767ba23041 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/270-ehci-ssb.patch @@ -0,0 +1,311 @@ +diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -96,6 +96,19 @@ config USB_EHCI_HCD_PPC_OF + Enables support for the USB controller present on the PowerPC + OpenFirmware platform bus. + ++config USB_EHCI_HCD_SSB ++ bool "EHCI support for Broadcom SSB EHCI core" ++ depends on USB_EHCI_HCD && SSB && EXPERIMENTAL ++ default n ++ ---help--- ++ Support for the Sonics Silicon Backplane (SSB) attached ++ Broadcom USB EHCI core. ++ ++ This device is present in some embedded devices with ++ Broadcom based SSB bus. ++ ++ If unsure, say N. ++ + config USB_ISP116X_HCD + tristate "ISP116X HCD support" + depends on USB +diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1034,8 +1034,16 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ixp4xx_ehci_driver + #endif + +-#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ +- !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) ++#ifdef CONFIG_USB_EHCI_HCD_SSB ++#include "ehci-ssb.c" ++#define SSB_EHCI_DRIVER ssb_ehci_driver ++#endif ++ ++#if !defined(PCI_DRIVER) && \ ++ !defined(PLATFORM_DRIVER) && \ ++ !defined(PS3_SYSTEM_BUS_DRIVER) && \ ++ !defined(OF_PLATFORM_DRIVER) && \ ++ !defined(SSB_EHCI_DRIVER) + #error "missing bus glue for ehci-hcd" + #endif + +diff --git a/drivers/usb/host/ehci-ssb.c b/drivers/usb/host/ehci-ssb.c +--- /dev/null ++++ b/drivers/usb/host/ehci-ssb.c +@@ -0,0 +1,201 @@ ++/* ++ * Sonics Silicon Backplane ++ * Broadcom USB-core EHCI driver (SSB bus glue) ++ * ++ * Copyright 2007 Steven Brown <sbrown@cortland.com> ++ * ++ * Derived from the OHCI-SSB driver ++ * Copyright 2007 Michael Buesch <mb@bu3sch.de> ++ * ++ * Derived from the EHCI-PCI driver ++ * Copyright (c) 2000-2004 by David Brownell ++ * ++ * Derived from the OHCI-PCI driver ++ * Copyright 1999 Roman Weissgaerber ++ * Copyright 2000-2002 David Brownell ++ * Copyright 1999 Linus Torvalds ++ * Copyright 1999 Gregory P. Smith ++ * ++ * Derived from the USBcore related parts of Broadcom-SB ++ * Copyright 2005 Broadcom Corporation ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++#include <linux/ssb/ssb.h> ++ ++#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29) ++ ++struct ssb_ehci_device { ++ struct ehci_hcd ehci; /* _must_ be at the beginning. */ ++ ++ u32 enable_flags; ++}; ++ ++static inline ++struct ssb_ehci_device *hcd_to_ssb_ehci(struct usb_hcd *hcd) ++{ ++ return (struct ssb_ehci_device *)(hcd->hcd_priv); ++} ++ ++ ++static int ssb_ehci_reset(struct usb_hcd *hcd) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int err; ++ ++ ehci->caps = hcd->regs; ++ ehci->regs = hcd->regs + ++ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); ++ ++ dbg_hcs_params(ehci, "reset"); ++ dbg_hcc_params(ehci, "reset"); ++ ++ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ ++ err = ehci_halt(ehci); ++ ++ if (err) ++ return err; ++ ++ err = ehci_init(hcd); ++ ++ if (err) ++ return err; ++ ++ ehci_port_power(ehci, 0); ++ ++ return err; ++} ++ ++static int ssb_ehci_start(struct usb_hcd *hcd) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int err; ++ ++ err = ehci_run(hcd); ++ if (err < 0) { ++ ehci_err(ehci, "can't start\n"); ++ ehci_stop(hcd); ++ } ++ ++ return err; ++} ++ ++#ifdef CONFIG_PM ++static int ssb_ehci_hcd_suspend(struct usb_hcd *hcd, pm_message_t message) ++{ ++ struct ssb_ehci_device *ehcidev = hcd_to_ssb_ehci(hcd); ++ struct ehci_hcd *ehci = &ehcidev->ehci; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ehci->lock, flags); ++ ++ ehci_writel(ehci, EHCI_INTR_MIE, &ehci->regs->intrdisable); ++ ehci_readl(ehci, &ehci->regs->intrdisable); /* commit write */ ++ ++ /* make sure snapshot being resumed re-enumerates everything */ ++ if (message.event == PM_EVENT_PRETHAW) ++ ehci_usb_reset(ehci); ++ ++ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ++ ++ spin_unlock_irqrestore(&ehci->lock, flags); ++ return 0; ++} ++ ++static int ssb_ehci_hcd_resume(struct usb_hcd *hcd) ++{ ++ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ++ usb_hcd_resume_root_hub(hcd); ++ return 0; ++} ++#endif /* CONFIG_PM */ ++ ++static const struct hc_driver ssb_ehci_hc_driver = { ++ .description = "ssb-usb-ehci", ++ .product_desc = "SSB EHCI Controller", ++ .hcd_priv_size = sizeof(struct ssb_ehci_device), ++ ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ .reset = ssb_ehci_reset, ++ .start = ssb_ehci_start, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, ++ ++#ifdef CONFIG_PM ++ .suspend = ssb_ehci_hcd_suspend, ++ .resume = ssb_ehci_hcd_resume, ++#endif ++ ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ ++ .get_frame_number = ehci_get_frame, ++ ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#ifdef CONFIG_PM ++ .bus_suspend = ehci_bus_suspend, ++ .bus_resume = ehci_bus_resume, ++#endif ++ ++}; ++ ++static void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd) ++{ ++ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ usb_put_hcd(hcd); ++} ++EXPORT_SYMBOL_GPL(ssb_ehci_detach); ++ ++static int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **ehci_hcd) ++{ ++ struct ssb_ehci_device *ehcidev; ++ struct usb_hcd *hcd; ++ int err = -ENOMEM; ++ u32 tmp, flags = 0; ++ ++ hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev, ++ dev->dev->bus_id); ++ if (!hcd) ++ goto err_dev_disable; ++ ++ ehcidev = hcd_to_ssb_ehci(hcd); ++ ehcidev->enable_flags = flags; ++ tmp = ssb_read32(dev, SSB_ADMATCH0); ++ hcd->rsrc_start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */ ++ hcd->rsrc_len = 0x100; /* ehci reg block size */ ++ /* ++ * start & size modified per sbutils.c ++ */ ++ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) ++ goto err_put_hcd; ++ err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED | IRQF_DISABLED); ++ if (err) ++ goto err_iounmap; ++ ++ *ehci_hcd = hcd; ++ ++ return err; ++ ++err_iounmap: ++ iounmap(hcd->regs); ++err_put_hcd: ++ usb_put_hcd(hcd); ++err_dev_disable: ++ ssb_device_disable(dev, flags); ++ return err; ++} ++EXPORT_SYMBOL_GPL(ssb_ehci_attach); ++ ++static const struct ssb_device_id ssb_ehci_table[] = { ++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV), ++ SSB_DEVTABLE_END ++}; ++MODULE_DEVICE_TABLE(ssb, ssb_ehci_table); +diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c +--- a/drivers/usb/host/ohci-ssb.c ++++ b/drivers/usb/host/ohci-ssb.c +@@ -17,6 +17,8 @@ + */ + #include <linux/ssb/ssb.h> + ++extern int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **hcd); ++extern void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd); + + #define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29) + +@@ -24,6 +26,7 @@ struct ssb_ohci_device { + struct ohci_hcd ohci; /* _must_ be at the beginning. */ + + u32 enable_flags; ++ struct usb_hcd *ehci_hcd; + }; + + static inline +@@ -92,13 +95,25 @@ static const struct hc_driver ssb_ohci_hc_driver = { + static void ssb_ohci_detach(struct ssb_device *dev) + { + struct usb_hcd *hcd = ssb_get_drvdata(dev); ++#ifdef CONFIG_USB_EHCI_HCD_SSB ++ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd); ++#endif + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + usb_put_hcd(hcd); ++ ++#ifdef CONFIG_USB_EHCI_HCD_SSB ++ /* ++ * Also detach ehci function ++ */ ++ if (dev->id.coreid == SSB_DEV_USB20_HOST) ++ ssb_ehci_detach(dev, ohcidev->ehci_hcd); ++#endif + ssb_device_disable(dev, 0); + } + ++ + static int ssb_ohci_attach(struct ssb_device *dev) + { + struct ssb_ohci_device *ohcidev; +@@ -184,6 +199,14 @@ static int ssb_ohci_attach(struct ssb_device *dev) + + ssb_set_drvdata(dev, hcd); + ++#ifdef CONFIG_USB_EHCI_HCD_SSB ++ /* ++ * attach ehci function in this core ++ */ ++ if (dev->id.coreid == SSB_DEV_USB20_HOST) ++ err = ssb_ehci_attach(dev, &(ohcidev->ehci_hcd)); ++#endif ++ + return err; + + err_iounmap: diff --git a/target/linux/brcm47xx/patches-2.6.28/300-fork_cacheflush.patch b/target/linux/brcm47xx/patches-2.6.28/300-fork_cacheflush.patch new file mode 100644 index 0000000000..87469d4390 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/300-fork_cacheflush.patch @@ -0,0 +1,12 @@ +diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h +--- a/arch/mips/include/asm/cacheflush.h ++++ b/arch/mips/include/asm/cacheflush.h +@@ -32,7 +32,7 @@ + extern void (*flush_cache_all)(void); + extern void (*__flush_cache_all)(void); + extern void (*flush_cache_mm)(struct mm_struct *mm); +-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0) ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) + extern void (*flush_cache_range)(struct vm_area_struct *vma, + unsigned long start, unsigned long end); + extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); diff --git a/target/linux/brcm47xx/patches-2.6.28/310-no_highpage.patch b/target/linux/brcm47xx/patches-2.6.28/310-no_highpage.patch new file mode 100644 index 0000000000..2420e81a31 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/310-no_highpage.patch @@ -0,0 +1,68 @@ +diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h +--- a/arch/mips/include/asm/page.h ++++ b/arch/mips/include/asm/page.h +@@ -32,6 +32,7 @@ + #ifndef __ASSEMBLY__ + + #include <linux/pfn.h> ++#include <asm/cpu-features.h> + #include <asm/io.h> + + extern void build_clear_page(void); +@@ -67,13 +68,16 @@ static inline void clear_user_page(void *addr, unsigned long vaddr, + flush_data_cache_page((unsigned long)addr); + } + +-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, +- struct page *to); +-struct vm_area_struct; +-extern void copy_user_highpage(struct page *to, struct page *from, +- unsigned long vaddr, struct vm_area_struct *vma); ++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, ++ struct page *to) ++{ ++ extern void (*flush_data_cache_page)(unsigned long addr); + +-#define __HAVE_ARCH_COPY_USER_HIGHPAGE ++ copy_page(vto, vfrom); ++ if (!cpu_has_ic_fills_f_dc || ++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) ++ flush_data_cache_page((unsigned long)vto); ++} + + /* + * These are used to make use of C type-checking.. +diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c +--- a/arch/mips/mm/init.c ++++ b/arch/mips/mm/init.c +@@ -206,30 +206,6 @@ void kunmap_coherent(void) + preempt_check_resched(); + } + +-void copy_user_highpage(struct page *to, struct page *from, +- unsigned long vaddr, struct vm_area_struct *vma) +-{ +- void *vfrom, *vto; +- +- vto = kmap_atomic(to, KM_USER1); +- if (cpu_has_dc_aliases && cpu_use_kmap_coherent && +- page_mapped(from) && !Page_dcache_dirty(from)) { +- vfrom = kmap_coherent(from, vaddr); +- copy_page(vto, vfrom); +- kunmap_coherent(); +- } else { +- vfrom = kmap_atomic(from, KM_USER0); +- copy_page(vto, vfrom); +- kunmap_atomic(vfrom, KM_USER0); +- } +- if ((!cpu_has_ic_fills_f_dc) || +- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) +- flush_data_cache_page((unsigned long)vto); +- kunmap_atomic(vto, KM_USER1); +- /* Make sure this page is cleared on other CPU's too before using it */ +- smp_wmb(); +-} +- + void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) diff --git a/target/linux/brcm47xx/patches-2.6.28/400-arch-bcm47xx.patch b/target/linux/brcm47xx/patches-2.6.28/400-arch-bcm47xx.patch new file mode 100644 index 0000000000..ae7bd74dc6 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/400-arch-bcm47xx.patch @@ -0,0 +1,326 @@ +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -53,6 +53,7 @@ config BCM47XX + select SSB_DRIVER_MIPS + select SSB_DRIVER_EXTIF + select SSB_EMBEDDED ++ select SSB_B43_PCI_BRIDGE + select SSB_PCICORE_HOSTMODE if PCI + select GENERIC_GPIO + select SYS_HAS_EARLY_PRINTK +diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile +--- a/arch/mips/bcm47xx/Makefile ++++ b/arch/mips/bcm47xx/Makefile +@@ -3,4 +3,4 @@ + # under Linux. + # + +-obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o ++obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o +diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c +--- a/arch/mips/bcm47xx/irq.c ++++ b/arch/mips/bcm47xx/irq.c +@@ -1,5 +1,6 @@ + /* + * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org> ++ * Copyright (C) 2008 Michael Buesch <mb@bu3sch.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the +@@ -23,10 +24,19 @@ + */ + + #include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/init.h> + #include <linux/interrupt.h> + #include <linux/irq.h> ++#include <linux/pci.h> ++#include <linux/ssb/ssb.h> ++ + #include <asm/irq_cpu.h> + ++ ++extern struct ssb_bus ssb_bcm47xx; ++ ++ + void plat_irq_dispatch(void) + { + u32 cause; +diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -24,10 +24,10 @@ + #include <asm/io.h> + #include <asm/uaccess.h> + +-#include <nvram.h> ++#include "include/nvram.h" + + #define MB * 1048576 +-extern struct ssb_bus ssb; ++extern struct ssb_bus ssb_bcm47xx; + + static char nvram_buf[NVRAM_SPACE]; + static int cfe_env; +@@ -36,7 +36,7 @@ extern char *cfe_env_get(char *nv_buf, const char *name); + /* Probe for NVRAM header */ + static void __init early_nvram_init(void) + { +- struct ssb_mipscore *mcore = &ssb.mipscore; ++ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; + struct nvram_header *header; + int i; + u32 base, lim, off; +diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -2,7 +2,7 @@ + * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org> + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org> + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> +- * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de> ++ * Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the +@@ -25,18 +25,28 @@ + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + ++#include <linux/init.h> + #include <linux/types.h> + #include <linux/ssb/ssb.h> + #include <linux/ssb/ssb_embedded.h> ++#include <linux/tty.h> ++#include <linux/serial.h> ++#include <linux/serial_core.h> ++#include <linux/serial_reg.h> ++#include <linux/serial_8250.h> + #include <asm/bootinfo.h> + #include <asm/reboot.h> + #include <asm/time.h> +-#include <bcm47xx.h> + #include <asm/fw/cfe/cfe_api.h> ++#include <linux/pm.h> ++ ++#include "include/nvram.h" + + struct ssb_bus ssb_bcm47xx; + EXPORT_SYMBOL(ssb_bcm47xx); + ++extern void bcm47xx_pci_init(void); ++ + static void bcm47xx_machine_restart(char *command) + { + printk(KERN_ALERT "Please stand by while rebooting the system...\n"); +@@ -56,7 +66,7 @@ static void bcm47xx_machine_halt(void) + cpu_relax(); + } + +-static void str2eaddr(char *str, char *dest) ++static void e_aton(char *str, char *dest) + { + int i = 0; + +@@ -73,52 +83,141 @@ static void str2eaddr(char *str, char *dest) + } + } + +-static int bcm47xx_get_invariants(struct ssb_bus *bus, +- struct ssb_init_invariants *iv) ++static void bcm47xx_fill_sprom(struct ssb_sprom *sprom) ++{ ++ char *s; ++ ++ memset(sprom, 0xFF, sizeof(struct ssb_sprom)); ++ ++ sprom->revision = 1; ++ if ((s = nvram_get("il0macaddr"))) ++ e_aton(s, sprom->il0mac); ++ if ((s = nvram_get("et0macaddr"))) ++ e_aton(s, sprom->et0mac); ++ if ((s = nvram_get("et1macaddr"))) ++ e_aton(s, sprom->et1mac); ++ if ((s = nvram_get("et0phyaddr"))) ++ sprom->et0phyaddr = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("et1phyaddr"))) ++ sprom->et1phyaddr = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("et0mdcport"))) ++ sprom->et0mdcport = !!simple_strtoul(s, NULL, 10); ++ if ((s = nvram_get("et1mdcport"))) ++ sprom->et1mdcport = !!simple_strtoul(s, NULL, 10); ++ if ((s = nvram_get("pa0b0"))) ++ sprom->pa0b0 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa0b1"))) ++ sprom->pa0b1 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa0b2"))) ++ sprom->pa0b2 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa1b0"))) ++ sprom->pa1b0 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa1b1"))) ++ sprom->pa1b1 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa1b2"))) ++ sprom->pa1b2 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("wl0gpio0"))) ++ sprom->gpio0 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("wl0gpio1"))) ++ sprom->gpio1 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("wl0gpio2"))) ++ sprom->gpio2 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("wl0gpio3"))) ++ sprom->gpio3 = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa0maxpwr"))) ++ sprom->maxpwr_bg = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa1maxpwr"))) ++ sprom->maxpwr_a = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa0itssit"))) ++ sprom->itssi_bg = simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("pa1itssit"))) ++ sprom->itssi_a = simple_strtoul(s, NULL, 0); ++ sprom->boardflags_lo = 0; ++ if ((s = nvram_get("boardflags"))) ++ sprom->boardflags_lo = simple_strtoul(s, NULL, 0); ++ sprom->boardflags_hi = 0; ++ if ((s = nvram_get("boardflags2"))) ++ sprom->boardflags_hi = simple_strtoul(s, NULL, 0); ++} ++ ++static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv) + { +- char buf[100]; +- +- /* Fill boardinfo structure */ +- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo)); +- +- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0) +- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0); +- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0) +- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0); +- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0) +- iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0); +- +- /* Fill sprom structure */ +- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom)); +- iv->sprom.revision = 3; +- +- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0) +- str2eaddr(buf, iv->sprom.et0mac); +- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0) +- str2eaddr(buf, iv->sprom.et1mac); +- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0) +- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10); +- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0) +- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10); +- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0) +- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10); +- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0) +- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10); ++ char *s; ++ ++ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM; ++ if ((s = nvram_get("boardtype"))) ++ iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0); ++ if ((s = nvram_get("boardrev"))) ++ iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0); ++ ++ bcm47xx_fill_sprom(&iv->sprom); ++ ++ if ((s = nvram_get("cardbus"))) ++ iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10); + + return 0; + } + + void __init plat_mem_setup(void) + { +- int err; ++ int i, err; ++ char *s; ++ struct ssb_mipscore *mcore; ++ ++ err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants); ++ if (err) { ++ const char *msg = "Failed to initialize SSB bus (err %d)\n"; ++ printk(msg, err); /* Make sure the message gets out of the box. */ ++ panic(msg, err); ++ } ++ mcore = &ssb_bcm47xx.mipscore; ++ ++ s = nvram_get("kernel_args"); ++ if (s && !strncmp(s, "console=ttyS1", 13)) { ++ struct ssb_serial_port port; + +- err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, +- bcm47xx_get_invariants); +- if (err) +- panic("Failed to initialize SSB bus (err %d)\n", err); ++ printk("Swapping serial ports!\n"); ++ /* swap serial ports */ ++ memcpy(&port, &mcore->serial_ports[0], sizeof(port)); ++ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port)); ++ memcpy(&mcore->serial_ports[1], &port, sizeof(port)); ++ } ++ ++ for (i = 0; i < mcore->nr_serial_ports; i++) { ++ struct ssb_serial_port *port = &(mcore->serial_ports[i]); ++ struct uart_port s; ++ ++ memset(&s, 0, sizeof(s)); ++ s.line = i; ++ s.membase = port->regs; ++ s.irq = port->irq + 2; ++ s.uartclk = port->baud_base; ++ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; ++ s.iotype = SERIAL_IO_MEM; ++ s.regshift = port->reg_shift; ++ ++ early_serial_setup(&s); ++ } ++ printk("Serial init done.\n"); + + _machine_restart = bcm47xx_machine_restart; + _machine_halt = bcm47xx_machine_halt; + pm_power_off = bcm47xx_machine_halt; + } + ++static int __init bcm47xx_register_gpiodev(void) ++{ ++ static struct resource res = { ++ .start = 0xFFFFFFFF, ++ }; ++ struct platform_device *pdev; ++ ++ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1); ++ if (!pdev) { ++ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++device_initcall(bcm47xx_register_gpiodev); +diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c +--- a/arch/mips/bcm47xx/time.c ++++ b/arch/mips/bcm47xx/time.c +@@ -22,11 +22,17 @@ + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +- + #include <linux/init.h> ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/serial_reg.h> ++#include <linux/interrupt.h> + #include <linux/ssb/ssb.h> ++#include <asm/addrspace.h> ++#include <asm/io.h> + #include <asm/time.h> +-#include <bcm47xx.h> ++ ++extern struct ssb_bus ssb_bcm47xx; + + void __init plat_time_init(void) + { diff --git a/target/linux/brcm47xx/patches-2.6.28/500-lzma_initramfs.patch b/target/linux/brcm47xx/patches-2.6.28/500-lzma_initramfs.patch new file mode 100644 index 0000000000..d03d34b331 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/500-lzma_initramfs.patch @@ -0,0 +1,119 @@ +diff --git a/init/initramfs.c b/init/initramfs.c +--- a/init/initramfs.c ++++ b/init/initramfs.c +@@ -475,6 +475,69 @@ static void __init flush_window(void) + outcnt = 0; + } + ++#include <linux/LzmaDecode.h> ++static int __init lzma_unzip(void) ++{ ++ unsigned int i; /* temp value */ ++ unsigned int lc; /* literal context bits */ ++ unsigned int lp; /* literal pos state bits */ ++ unsigned int pb; /* pos state bits */ ++ unsigned int osize; /* uncompressed size */ ++ unsigned char *workspace; ++ unsigned char* outputbuffer; ++ unsigned int outsizeProcessed = 0; ++ int workspace_size; ++ int res; ++ ++ // lzma args ++ i = get_byte(); ++ lc = i % 9, i = i / 9; ++ lp = i % 5, pb = i / 5; ++ ++ // skip dictionary size ++ for (i = 0; i < 4; i++) ++ get_byte(); ++ ++ /* read the lower half of uncompressed size in the header */ ++ osize = ((unsigned int)get_byte()) + ++ ((unsigned int)get_byte() << 8) + ++ ((unsigned int)get_byte() << 16) + ++ ((unsigned int)get_byte() << 24); ++ ++ /* skip rest of the header (upper half of uncompressed size) */ ++ for (i = 0; i < 4; i++) ++ get_byte(); ++ ++ workspace_size = ((LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp))) * sizeof(CProb)) + 100; ++ printk( KERN_NOTICE "initramfs: LZMA lc=%d,lp=%d,pb=%d,origSize=%d\n", ++ lc,lp,pb,osize); ++ outputbuffer = kmalloc(osize, GFP_KERNEL); ++ if (outputbuffer == 0) { ++ printk(KERN_ERR "initramfs: Couldn't allocate lzma output buffer\n"); ++ return -1; ++ } ++ ++ workspace = kmalloc(workspace_size, GFP_KERNEL); ++ if (workspace == NULL) { ++ printk(KERN_ERR "initramfs: Couldn't allocate lzma workspace\n"); ++ return -1; ++ } ++ ++ res = LzmaDecode(workspace, workspace_size, lc, lp, pb, inbuf + inptr, insize - inptr, outputbuffer, osize, &outsizeProcessed); ++ if( res != 0 ) { ++ panic( KERN_ERR "initramfs: Lzma decode failure\n"); ++ return -1; ++ } ++ ++ flush_buffer(outputbuffer, outsizeProcessed); ++ inptr = insize; ++ ++ kfree(outputbuffer); ++ kfree(workspace); ++ state = Reset; ++ return 0; ++} ++ + static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only) + { + int written; +@@ -509,12 +572,28 @@ static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only) + inptr = 0; + outcnt = 0; /* bytes in output buffer */ + bytes_out = 0; +- crc = (ulg)0xffffffffL; /* shift register contents */ +- makecrc(); +- gunzip(); +- if (state != Reset) ++ if( inbuf[0] == 037 && ((inbuf[1] == 0213) || (inbuf[1] == 0236))) ++ { ++ printk( KERN_NOTICE "detected gzip initramfs\n"); ++ crc = (ulg)0xffffffffL; /* shift register contents */ ++ makecrc(); ++ gunzip(); ++ if (state != Reset) + error("junk in gzipped archive"); +- this_header = saved_offset + inptr; ++ } ++ else if(!memcmp(inbuf+1, "\x00\x00\x80\x00", 4)) /* FIXME: hardcoded dictionary size */ ++ { ++ printk( KERN_NOTICE "detected lzma initramfs\n"); ++ lzma_unzip(); ++ } ++ else ++ { ++ // skip forward ? ++ crc = (ulg)0xffffffffL; /* shift register contents */ ++ makecrc(); ++ gunzip(); ++ } ++ this_header = saved_offset + inptr; + buf += inptr; + len -= inptr; + } +diff --git a/scripts/gen_initramfs_list.sh b/scripts/gen_initramfs_list.sh +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -287,7 +287,7 @@ if [ ! -z ${output_file} ]; then + if [ "${is_cpio_compressed}" = "compressed" ]; then + cat ${cpio_tfile} > ${output_file} + else +- cat ${cpio_tfile} | gzip -f -9 - > ${output_file} ++ lzma e -lc1 -lp2 -pb2 ${cpio_tfile} ${output_file} + fi + [ -z ${cpio_file} ] && rm ${cpio_tfile} + fi diff --git a/target/linux/brcm47xx/patches-2.6.28/601-mips-remove-pci-collision-check.patch b/target/linux/brcm47xx/patches-2.6.28/601-mips-remove-pci-collision-check.patch new file mode 100644 index 0000000000..50b6fbdfe3 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/601-mips-remove-pci-collision-check.patch @@ -0,0 +1,19 @@ +diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -207,12 +207,10 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) + if ((idx == PCI_ROM_RESOURCE) && + (!(r->flags & IORESOURCE_ROM_ENABLE))) + continue; +- if (!r->start && r->end) { +- printk(KERN_ERR "PCI: Device %s not available " +- "because of resource collisions\n", ++ if (!r->start && r->end) ++ printk(KERN_WARNING "PCI: Device %s resource" ++ "collisions detected. Ignoring...\n", + pci_name(dev)); +- return -EINVAL; +- } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) diff --git a/target/linux/brcm47xx/patches-2.6.28/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.28/700-ssb-gigabit-ethernet-driver.patch new file mode 100644 index 0000000000..f02269e025 --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/700-ssb-gigabit-ethernet-driver.patch @@ -0,0 +1,338 @@ +diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c +--- a/drivers/net/tg3.c ++++ b/drivers/net/tg3.c +@@ -40,6 +40,7 @@ + #include <linux/workqueue.h> + #include <linux/prefetch.h> + #include <linux/dma-mapping.h> ++#include <linux/ssb/ssb_driver_gige.h> + + #include <net/checksum.h> + #include <net/ip.h> +@@ -428,8 +429,9 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) + static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) + { + tp->write32_mbox(tp, off, val); +- if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && +- !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) ++ if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) || ++ (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && ++ !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))) + tp->read32_mbox(tp, off); + } + +@@ -439,7 +441,7 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) + writel(val, mbox); + if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) + writel(val, mbox); +- if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ++ if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES)) + readl(mbox); + } + +@@ -711,7 +713,7 @@ static void tg3_switch_clocks(struct tg3 *tp) + + #define PHY_BUSY_LOOPS 5000 + +-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ++static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val) + { + u32 frame_val; + unsigned int loops; +@@ -725,7 +727,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) + + *val = 0x0; + +- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & ++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) & + MI_COM_PHY_ADDR_MASK); + frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & + MI_COM_REG_ADDR_MASK); +@@ -760,7 +762,12 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) + return ret; + } + +-static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ++static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ++{ ++ return __tg3_readphy(tp, PHY_ADDR, reg, val); ++} ++ ++static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val) + { + u32 frame_val; + unsigned int loops; +@@ -776,7 +783,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) + udelay(80); + } + +- frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & ++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) & + MI_COM_PHY_ADDR_MASK); + frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & + MI_COM_REG_ADDR_MASK); +@@ -809,6 +816,11 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) + return ret; + } + ++static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ++{ ++ return __tg3_writephy(tp, PHY_ADDR, reg, val); ++} ++ + static int tg3_bmcr_reset(struct tg3 *tp) + { + u32 phy_control; +@@ -2232,8 +2244,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) + tg3_frob_aux_power(tp); + + /* Workaround for unstable PLL clock */ +- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || +- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { ++ if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) && ++ /* !!! FIXME !!! */ ++ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || ++ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) { + u32 val = tr32(0x7d00); + + val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); +@@ -2725,6 +2739,14 @@ relink: + + tg3_phy_copper_begin(tp); + ++ if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) { ++ current_link_up = 1; ++ current_speed = SPEED_1000; //FIXME ++ current_duplex = DUPLEX_FULL; ++ tp->link_config.active_speed = current_speed; ++ tp->link_config.active_duplex = current_duplex; ++ } ++ + tg3_readphy(tp, MII_BMSR, &tmp); + if (!tg3_readphy(tp, MII_BMSR, &tmp) && + (tmp & BMSR_LSTATUS)) +@@ -5659,6 +5681,11 @@ static int tg3_poll_fw(struct tg3 *tp) + int i; + u32 val; + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { ++ /* We don't use firmware. */ ++ return 0; ++ } ++ + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { + /* Wait up to 20ms for init done. */ + for (i = 0; i < 200; i++) { +@@ -5902,6 +5929,14 @@ static int tg3_chip_reset(struct tg3 *tp) + tw32(0x5000, 0x400); + } + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { ++ /* BCM4785: In order to avoid repercussions from using potentially ++ * defective internal ROM, stop the Rx RISC CPU, which is not ++ * required. */ ++ tg3_stop_fw(tp); ++ tg3_halt_cpu(tp, RX_CPU_BASE); ++ } ++ + tw32(GRC_MODE, tp->grc_mode); + + if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { +@@ -6176,9 +6211,12 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) + return -ENODEV; + } + +- /* Clear firmware's nvram arbitration. */ +- if (tp->tg3_flags & TG3_FLAG_NVRAM) +- tw32(NVRAM_SWARB, SWARB_REQ_CLR0); ++ if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) { ++ /* Clear firmware's nvram arbitration. */ ++ if (tp->tg3_flags & TG3_FLAG_NVRAM) ++ tw32(NVRAM_SWARB, SWARB_REQ_CLR0); ++ } ++ + return 0; + } + +@@ -6259,6 +6297,11 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) + struct fw_info info; + int err, i; + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { ++ /* We don't use firmware. */ ++ return 0; ++ } ++ + info.text_base = TG3_FW_TEXT_ADDR; + info.text_len = TG3_FW_TEXT_LEN; + info.text_data = &tg3FwText[0]; +@@ -6817,6 +6860,11 @@ static int tg3_load_tso_firmware(struct tg3 *tp) + unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; + int err, i; + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { ++ /* We don't use firmware. */ ++ return 0; ++ } ++ + if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) + return 0; + +@@ -7776,6 +7824,11 @@ static void tg3_timer(unsigned long __opaque) + + spin_lock(&tp->lock); + ++ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) { ++ /* BCM4785: Flush posted writes from GbE to host memory. */ ++ tr32(HOSTCC_MODE); ++ } ++ + if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { + /* All of this garbage is because when using non-tagged + * IRQ status the mailbox/status_block protocol the chip +@@ -9469,6 +9522,11 @@ static int tg3_test_nvram(struct tg3 *tp) + __le32 *buf; + int i, j, k, err = 0, size; + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { ++ /* We don't have NVRAM. */ ++ return 0; ++ } ++ + if (tg3_nvram_read_swab(tp, 0, &magic) != 0) + return -EIO; + +@@ -10262,7 +10320,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) + return -EAGAIN; + + spin_lock_bh(&tp->lock); +- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); ++ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval); + spin_unlock_bh(&tp->lock); + + data->val_out = mii_regval; +@@ -10281,7 +10339,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) + return -EAGAIN; + + spin_lock_bh(&tp->lock); +- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); ++ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); + spin_unlock_bh(&tp->lock); + + return err; +@@ -10759,6 +10817,12 @@ static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) + /* Chips other than 5700/5701 use the NVRAM for fetching info. */ + static void __devinit tg3_nvram_init(struct tg3 *tp) + { ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { ++ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */ ++ tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); ++ return; ++ } ++ + tw32_f(GRC_EEPROM_ADDR, + (EEPROM_ADDR_FSM_RESET | + (EEPROM_DEFAULT_CLOCK_PERIOD << +@@ -10900,6 +10964,9 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) + { + int ret; + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) ++ return -ENODEV; ++ + if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) + return tg3_nvram_read_using_eeprom(tp, offset, val); + +@@ -11147,6 +11214,9 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) + { + int ret; + ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) ++ return -ENODEV; ++ + if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { + tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & + ~GRC_LCLCTRL_GPIO_OUTPUT1); +@@ -12205,7 +12275,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) + tp->write32 = tg3_write_flush_reg32; + } + +- + if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || + (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { + tp->write32_tx_mbox = tg3_write32_tx_mbox; +@@ -12241,6 +12310,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) + tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; + ++ if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) { ++ tp->write32_tx_mbox = tg3_write_flush_reg32; ++ tp->write32_rx_mbox = tg3_write_flush_reg32; ++ } ++ + /* Get eeprom hw config before calling tg3_set_power_state(). + * In particular, the TG3_FLG2_IS_NIC flag must be + * determined before calling tg3_set_power_state() so that +@@ -12640,6 +12714,10 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) + } + + if (!is_valid_ether_addr(&dev->dev_addr[0])) { ++ if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) ++ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); ++ } ++ if (!is_valid_ether_addr(&dev->dev_addr[0])) { + #ifdef CONFIG_SPARC + if (!tg3_get_default_macaddr_sparc(tp)) + return 0; +@@ -13131,6 +13209,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp) + case PHY_ID_BCM5704: return "5704"; + case PHY_ID_BCM5705: return "5705"; + case PHY_ID_BCM5750: return "5750"; ++ case PHY_ID_BCM5750_2: return "5750-2"; + case PHY_ID_BCM5752: return "5752"; + case PHY_ID_BCM5714: return "5714"; + case PHY_ID_BCM5780: return "5780"; +@@ -13317,6 +13396,13 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, + tp->msg_enable = tg3_debug; + else + tp->msg_enable = TG3_DEF_MSG_ENABLE; ++ if (pdev_is_ssb_gige_core(pdev)) { ++ tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE; ++ if (ssb_gige_must_flush_posted_writes(pdev)) ++ tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES; ++ if (ssb_gige_have_roboswitch(pdev)) ++ tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH; ++ } + + /* The word/byte swap controls here control register access byte + * swapping. DMA data byte swapping is controlled in the GRC_MODE +diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h +--- a/drivers/net/tg3.h ++++ b/drivers/net/tg3.h +@@ -2516,6 +2516,9 @@ struct tg3 { + #define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100 + #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200 + #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 ++#define TG3_FLG3_IS_SSB_CORE 0x00000800 ++#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00001000 ++#define TG3_FLG3_ROBOSWITCH 0x00002000 + + struct timer_list timer; + u16 timer_counter; +@@ -2574,6 +2577,7 @@ struct tg3 { + #define PHY_ID_BCM5714 0x60008340 + #define PHY_ID_BCM5780 0x60008350 + #define PHY_ID_BCM5755 0xbc050cc0 ++#define PHY_ID_BCM5750_2 0xbc050cd0 + #define PHY_ID_BCM5787 0xbc050ce0 + #define PHY_ID_BCM5756 0xbc050ed0 + #define PHY_ID_BCM5784 0xbc050fa0 +@@ -2613,7 +2617,7 @@ struct tg3 { + (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ + (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ + (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \ +- (X) == PHY_ID_BCM8002) ++ (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2) + + struct tg3_hw_stats *hw_stats; + dma_addr_t stats_mapping; diff --git a/target/linux/brcm47xx/patches-2.6.28/800-fix_cfe_detection.patch b/target/linux/brcm47xx/patches-2.6.28/800-fix_cfe_detection.patch new file mode 100644 index 0000000000..eb5ec49d5f --- /dev/null +++ b/target/linux/brcm47xx/patches-2.6.28/800-fix_cfe_detection.patch @@ -0,0 +1,108 @@ +diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c +--- a/arch/mips/bcm47xx/prom.c ++++ b/arch/mips/bcm47xx/prom.c +@@ -32,6 +32,7 @@ + #include <asm/fw/cfe/cfe_error.h> + + static int cfe_cons_handle; ++static void (* __prom_putchar)(char c); + + const char *get_system_type(void) + { +@@ -40,65 +41,40 @@ const char *get_system_type(void) + + void prom_putchar(char c) + { ++ if (__prom_putchar) ++ __prom_putchar(c); ++} ++ ++void prom_putchar_cfe(char c) ++{ + while (cfe_write(cfe_cons_handle, &c, 1) == 0) + ; + } + +-static __init void prom_init_cfe(void) ++static __init int prom_init_cfe(void) + { + uint32_t cfe_ept; + uint32_t cfe_handle; + uint32_t cfe_eptseal; +- int argc = fw_arg0; +- char **envp = (char **) fw_arg2; +- int *prom_vec = (int *) fw_arg3; + +- /* +- * Check if a loader was used; if NOT, the 4 arguments are +- * what CFE gives us (handle, 0, EPT and EPTSEAL) +- */ +- if (argc < 0) { +- cfe_handle = (uint32_t)argc; +- cfe_ept = (uint32_t)envp; +- cfe_eptseal = (uint32_t)prom_vec; +- } else { +- if ((int)prom_vec < 0) { +- /* +- * Old loader; all it gives us is the handle, +- * so use the "known" entrypoint and assume +- * the seal. +- */ +- cfe_handle = (uint32_t)prom_vec; +- cfe_ept = 0xBFC00500; +- cfe_eptseal = CFE_EPTSEAL; +- } else { +- /* +- * Newer loaders bundle the handle/ept/eptseal +- * Note: prom_vec is in the loader's useg +- * which is still alive in the TLB. +- */ +- cfe_handle = prom_vec[0]; +- cfe_ept = prom_vec[2]; +- cfe_eptseal = prom_vec[3]; +- } +- } ++ cfe_eptseal = (uint32_t) fw_arg3; ++ cfe_handle = (uint32_t) fw_arg0; ++ cfe_ept = (uint32_t) fw_arg2; + +- if (cfe_eptseal != CFE_EPTSEAL) { +- /* too early for panic to do any good */ +- printk(KERN_ERR "CFE's entrypoint seal doesn't match."); +- while (1) ; +- } ++ if (cfe_eptseal != CFE_EPTSEAL) ++ return -1; + + cfe_init(cfe_handle, cfe_ept); ++ return 0; + } + +-static __init void prom_init_console(void) ++static __init void prom_init_console_cfe(void) + { + /* Initialize CFE console */ + cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); + } + +-static __init void prom_init_cmdline(void) ++static __init void prom_init_cmdline_cfe(void) + { + char buf[CL_SIZE]; + +@@ -146,9 +122,12 @@ static __init void prom_init_mem(void) + + void __init prom_init(void) + { +- prom_init_cfe(); +- prom_init_console(); +- prom_init_cmdline(); ++ if (prom_init_cfe() == 0) { ++ prom_init_console_cfe(); ++ prom_init_cmdline_cfe(); ++ __prom_putchar = prom_putchar_cfe; ++ } ++ + prom_init_mem(); + } + |