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Diffstat (limited to 'target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch')
-rw-r--r--target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch72
1 files changed, 31 insertions, 41 deletions
diff --git a/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
index fb91dfae74..e0d225b154 100644
--- a/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx/patches-2.6.25/150-cpu_fixes.patch
@@ -1,8 +1,6 @@
-Index: linux-2.6.25.4/arch/mips/kernel/genex.S
-===================================================================
---- linux-2.6.25.4.orig/arch/mips/kernel/genex.S
-+++ linux-2.6.25.4/arch/mips/kernel/genex.S
-@@ -51,6 +51,10 @@ NESTED(except_vec1_generic, 0, sp)
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -51,6 +51,10 @@
NESTED(except_vec3_generic, 0, sp)
.set push
.set noat
@@ -13,10 +11,8 @@ Index: linux-2.6.25.4/arch/mips/kernel/genex.S
#if R5432_CP0_INTERRUPT_WAR
mfc0 k0, CP0_INDEX
#endif
-Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
-===================================================================
---- linux-2.6.25.4.orig/arch/mips/mm/c-r4k.c
-+++ linux-2.6.25.4/arch/mips/mm/c-r4k.c
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
@@ -33,6 +33,9 @@
#include <asm/cacheflush.h> /* for run_uncached() */
@@ -27,7 +23,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
/*
* Special Variant of smp_call_function for use by cache functions:
*
-@@ -97,6 +100,9 @@ static void __cpuinit r4k_blast_dcache_p
+@@ -97,6 +100,9 @@
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -37,7 +33,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
if (dc_lsize == 0)
r4k_blast_dcache_page = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -111,6 +117,9 @@ static void __cpuinit r4k_blast_dcache_p
+@@ -111,6 +117,9 @@
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -47,7 +43,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
if (dc_lsize == 0)
r4k_blast_dcache_page_indexed = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -125,6 +134,9 @@ static void __cpuinit r4k_blast_dcache_s
+@@ -125,6 +134,9 @@
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -57,7 +53,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -630,6 +642,8 @@ static void local_r4k_flush_cache_sigtra
+@@ -630,6 +642,8 @@
unsigned long addr = (unsigned long) arg;
R4600_HIT_CACHEOP_WAR_IMPL;
@@ -66,7 +62,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
if (dc_lsize)
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1215,6 +1229,17 @@ static void __cpuinit coherency_setup(vo
+@@ -1215,6 +1229,17 @@
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
@@ -84,7 +80,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1254,6 +1279,15 @@ void __cpuinit r4k_cache_init(void)
+@@ -1254,6 +1279,15 @@
break;
}
@@ -100,7 +96,7 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
probe_pcache();
setup_scache();
-@@ -1303,5 +1337,13 @@ void __cpuinit r4k_cache_init(void)
+@@ -1303,5 +1337,13 @@
build_clear_page();
build_copy_page();
local_r4k___flush_cache_all(NULL);
@@ -114,11 +110,9 @@ Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
coherency_setup();
+#endif
}
-Index: linux-2.6.25.4/arch/mips/mm/tlbex.c
-===================================================================
---- linux-2.6.25.4.orig/arch/mips/mm/tlbex.c
-+++ linux-2.6.25.4/arch/mips/mm/tlbex.c
-@@ -677,6 +677,9 @@ static void __cpuinit build_r4000_tlb_re
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -677,6 +677,9 @@
/* No need for uasm_i_nop */
}
@@ -128,7 +122,7 @@ Index: linux-2.6.25.4/arch/mips/mm/tlbex.c
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
-@@ -1084,6 +1087,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -1084,6 +1087,9 @@
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{
@@ -138,10 +132,8 @@ Index: linux-2.6.25.4/arch/mips/mm/tlbex.c
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
#else
-Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
-===================================================================
---- linux-2.6.25.4.orig/include/asm-mips/r4kcache.h
-+++ linux-2.6.25.4/include/asm-mips/r4kcache.h
+--- a/include/asm-mips/r4kcache.h
++++ b/include/asm-mips/r4kcache.h
@@ -17,6 +17,20 @@
#include <asm/cpu-features.h>
#include <asm/mipsmtregs.h>
@@ -163,7 +155,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
-@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
+@@ -150,6 +164,7 @@
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
@@ -171,7 +163,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
+@@ -169,6 +184,7 @@
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
@@ -179,7 +171,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
+@@ -176,6 +192,7 @@
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
@@ -187,7 +179,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
-@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
+@@ -208,6 +225,7 @@
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
@@ -195,7 +187,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
protected_cache_op(Hit_Invalidate_I, addr);
}
-@@ -219,6 +237,7 @@ static inline void protected_flush_icach
+@@ -219,6 +237,7 @@
*/
static inline void protected_writeback_dcache_line(unsigned long addr)
{
@@ -203,7 +195,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
protected_cache_op(Hit_Writeback_Inv_D, addr);
}
-@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
+@@ -339,8 +358,52 @@
: "r" (base), \
"i" (op));
@@ -257,7 +249,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
static inline void blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
-@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
+@@ -352,6 +415,7 @@
\
__##pfx##flush_prologue \
\
@@ -265,7 +257,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws, indexop); \
-@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
+@@ -366,6 +430,7 @@
\
__##pfx##flush_prologue \
\
@@ -273,7 +265,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
do { \
cache##lsize##_unroll32(start, hitop); \
start += lsize * 32; \
-@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
+@@ -384,6 +449,8 @@
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
@@ -282,7 +274,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -393,35 +460,37 @@ static inline void blast_##pfx##cache##l
+@@ -393,35 +460,37 @@
__##pfx##flush_epilogue \
}
@@ -337,7 +329,7 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
-@@ -431,13 +500,13 @@ static inline void prot##blast_##pfx##ca
+@@ -431,13 +500,13 @@
__##pfx##flush_epilogue \
}
@@ -358,10 +350,8 @@ Index: linux-2.6.25.4/include/asm-mips/r4kcache.h
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
#endif /* _ASM_R4KCACHE_H */
-Index: linux-2.6.25.4/include/asm-mips/stackframe.h
-===================================================================
---- linux-2.6.25.4.orig/include/asm-mips/stackframe.h
-+++ linux-2.6.25.4/include/asm-mips/stackframe.h
+--- a/include/asm-mips/stackframe.h
++++ b/include/asm-mips/stackframe.h
@@ -359,6 +359,10 @@
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 17:42:51 +0000