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Diffstat (limited to 'target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch')
-rw-r--r--target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch72
1 files changed, 36 insertions, 36 deletions
diff --git a/target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch b/target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch
index d19ba81fad..f155de70b4 100644
--- a/target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch
+++ b/target/linux/brcm47xx/patches-2.6.23/150-cpu_fixes.patch
@@ -1,8 +1,8 @@
-Index: linux-2.6.23/arch/mips/kernel/genex.S
+Index: linux-2.6.23.17/arch/mips/kernel/genex.S
===================================================================
---- linux-2.6.23.orig/arch/mips/kernel/genex.S 2007-10-13 11:29:46.219648163 +0200
-+++ linux-2.6.23/arch/mips/kernel/genex.S 2007-10-13 11:29:49.619841933 +0200
-@@ -51,6 +51,10 @@
+--- linux-2.6.23.17.orig/arch/mips/kernel/genex.S
++++ linux-2.6.23.17/arch/mips/kernel/genex.S
+@@ -51,6 +51,10 @@ NESTED(except_vec1_generic, 0, sp)
NESTED(except_vec3_generic, 0, sp)
.set push
.set noat
@@ -13,10 +13,10 @@ Index: linux-2.6.23/arch/mips/kernel/genex.S
#if R5432_CP0_INTERRUPT_WAR
mfc0 k0, CP0_INDEX
#endif
-Index: linux-2.6.23/arch/mips/mm/c-r4k.c
+Index: linux-2.6.23.17/arch/mips/mm/c-r4k.c
===================================================================
---- linux-2.6.23.orig/arch/mips/mm/c-r4k.c 2007-10-13 11:29:46.227648623 +0200
-+++ linux-2.6.23/arch/mips/mm/c-r4k.c 2007-10-13 11:29:49.619841933 +0200
+--- linux-2.6.23.17.orig/arch/mips/mm/c-r4k.c
++++ linux-2.6.23.17/arch/mips/mm/c-r4k.c
@@ -30,6 +30,9 @@
#include <asm/cacheflush.h> /* for run_uncached() */
@@ -27,7 +27,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
/*
* Special Variant of smp_call_function for use by cache functions:
*
-@@ -94,6 +97,9 @@
+@@ -94,6 +97,9 @@ static void __init r4k_blast_dcache_page
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -37,7 +37,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
if (dc_lsize == 0)
r4k_blast_dcache_page = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -108,6 +114,9 @@
+@@ -108,6 +114,9 @@ static void __init r4k_blast_dcache_page
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -47,7 +47,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
if (dc_lsize == 0)
r4k_blast_dcache_page_indexed = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -122,6 +131,9 @@
+@@ -122,6 +131,9 @@ static void __init r4k_blast_dcache_setu
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -57,7 +57,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -623,6 +635,8 @@
+@@ -638,6 +650,8 @@ static void local_r4k_flush_cache_sigtra
unsigned long addr = (unsigned long) arg;
R4600_HIT_CACHEOP_WAR_IMPL;
@@ -66,7 +66,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
if (dc_lsize)
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1198,6 +1212,17 @@
+@@ -1213,6 +1227,17 @@ static void __init coherency_setup(void)
* silly idea of putting something else there ...
*/
switch (current_cpu_data.cputype) {
@@ -84,7 +84,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1228,6 +1253,15 @@
+@@ -1243,6 +1268,15 @@ void __init r4k_cache_init(void)
/* Default cache error handler for R4000 and R5000 family */
set_uncached_handler (0x100, &except_vec2_generic, 0x80);
@@ -100,7 +100,7 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
probe_pcache();
setup_scache();
-@@ -1273,5 +1307,13 @@
+@@ -1288,5 +1322,13 @@ void __init r4k_cache_init(void)
build_clear_page();
build_copy_page();
local_r4k___flush_cache_all(NULL);
@@ -114,11 +114,11 @@ Index: linux-2.6.23/arch/mips/mm/c-r4k.c
coherency_setup();
+#endif
}
-Index: linux-2.6.23/arch/mips/mm/tlbex.c
+Index: linux-2.6.23.17/arch/mips/mm/tlbex.c
===================================================================
---- linux-2.6.23.orig/arch/mips/mm/tlbex.c 2007-10-13 11:29:46.235649074 +0200
-+++ linux-2.6.23/arch/mips/mm/tlbex.c 2007-10-13 11:35:46.076155216 +0200
-@@ -1273,6 +1273,9 @@
+--- linux-2.6.23.17.orig/arch/mips/mm/tlbex.c
++++ linux-2.6.23.17/arch/mips/mm/tlbex.c
+@@ -1273,6 +1273,9 @@ static void __init build_r4000_tlb_refil
/* No need for i_nop */
}
@@ -128,7 +128,7 @@ Index: linux-2.6.23/arch/mips/mm/tlbex.c
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
-@@ -1708,6 +1711,9 @@
+@@ -1708,6 +1711,9 @@ build_r4000_tlbchange_handler_head(u32 *
struct reloc **r, unsigned int pte,
unsigned int ptr)
{
@@ -138,10 +138,10 @@ Index: linux-2.6.23/arch/mips/mm/tlbex.c
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
#else
-Index: linux-2.6.23/include/asm-mips/r4kcache.h
+Index: linux-2.6.23.17/include/asm-mips/r4kcache.h
===================================================================
---- linux-2.6.23.orig/include/asm-mips/r4kcache.h 2007-10-13 11:29:46.255650214 +0200
-+++ linux-2.6.23/include/asm-mips/r4kcache.h 2007-10-13 11:29:49.631842613 +0200
+--- linux-2.6.23.17.orig/include/asm-mips/r4kcache.h
++++ linux-2.6.23.17/include/asm-mips/r4kcache.h
@@ -17,6 +17,20 @@
#include <asm/cpu-features.h>
#include <asm/mipsmtregs.h>
@@ -163,7 +163,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
-@@ -150,6 +164,7 @@
+@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
@@ -171,7 +171,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -169,6 +184,7 @@
+@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
@@ -179,7 +179,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -176,6 +192,7 @@
+@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
@@ -187,7 +187,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
-@@ -208,6 +225,7 @@
+@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
@@ -195,7 +195,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
protected_cache_op(Hit_Invalidate_I, addr);
}
-@@ -219,6 +237,7 @@
+@@ -219,6 +237,7 @@ static inline void protected_flush_icach
*/
static inline void protected_writeback_dcache_line(unsigned long addr)
{
@@ -203,7 +203,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
protected_cache_op(Hit_Writeback_Inv_D, addr);
}
-@@ -339,8 +358,52 @@
+@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
: "r" (base), \
"i" (op));
@@ -257,7 +257,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
static inline void blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
-@@ -352,6 +415,7 @@
+@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
\
__##pfx##flush_prologue \
\
@@ -265,7 +265,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws,indexop); \
-@@ -366,6 +430,7 @@
+@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
\
__##pfx##flush_prologue \
\
@@ -273,7 +273,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
do { \
cache##lsize##_unroll32(start,hitop); \
start += lsize * 32; \
-@@ -384,6 +449,8 @@
+@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
@@ -282,7 +282,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -393,28 +460,30 @@
+@@ -393,28 +460,30 @@ static inline void blast_##pfx##cache##l
__##pfx##flush_epilogue \
}
@@ -323,7 +323,7 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
-@@ -424,13 +493,13 @@
+@@ -424,13 +493,13 @@ static inline void prot##blast_##pfx##ca
__##pfx##flush_epilogue \
}
@@ -344,10 +344,10 @@ Index: linux-2.6.23/include/asm-mips/r4kcache.h
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
#endif /* _ASM_R4KCACHE_H */
-Index: linux-2.6.23/include/asm-mips/stackframe.h
+Index: linux-2.6.23.17/include/asm-mips/stackframe.h
===================================================================
---- linux-2.6.23.orig/include/asm-mips/stackframe.h 2007-10-13 11:29:46.263650671 +0200
-+++ linux-2.6.23/include/asm-mips/stackframe.h 2007-10-13 11:33:38.504885346 +0200
+--- linux-2.6.23.17.orig/include/asm-mips/stackframe.h
++++ linux-2.6.23.17/include/asm-mips/stackframe.h
@@ -350,6 +350,10 @@
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 16:45:54 +0000