diff options
Diffstat (limited to 'target/linux/brcm2708')
19 files changed, 49 insertions, 49 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0029-Add-dwc_otg-driver.patch b/target/linux/brcm2708/patches-4.4/0029-Add-dwc_otg-driver.patch index 54586c1423..69711f69e9 100644 --- a/target/linux/brcm2708/patches-4.4/0029-Add-dwc_otg-driver.patch +++ b/target/linux/brcm2708/patches-4.4/0029-Add-dwc_otg-driver.patch @@ -659,7 +659,7 @@ dwc_otg: Remove duplicate gadget probe/unregister function } --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c -@@ -4943,7 +4943,7 @@ static void port_event(struct usb_hub *h +@@ -4942,7 +4942,7 @@ static void port_event(struct usb_hub *h if (portchange & USB_PORT_STAT_C_OVERCURRENT) { u16 status = 0, unused; diff --git a/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch b/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch index b0f6777348..b9b139ce9b 100644 --- a/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch +++ b/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch @@ -16,7 +16,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1164,22 +1164,24 @@ static int bcm2835_clock_is_on(struct cl +@@ -1166,22 +1166,24 @@ static int bcm2835_clock_is_on(struct cl static u32 bcm2835_clock_choose_div(struct clk_hw *hw, unsigned long rate, @@ -49,7 +49,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> /* clamp to min divider of 1 */ div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS); -@@ -1219,7 +1221,7 @@ static long bcm2835_clock_round_rate(str +@@ -1221,7 +1223,7 @@ static long bcm2835_clock_round_rate(str unsigned long *parent_rate) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); @@ -58,7 +58,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div); } -@@ -1288,7 +1290,7 @@ static int bcm2835_clock_set_rate(struct +@@ -1290,7 +1292,7 @@ static int bcm2835_clock_set_rate(struct struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; diff --git a/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch b/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch index f0907c1cd4..0332be617e 100644 --- a/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch +++ b/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch @@ -24,7 +24,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1216,16 +1216,6 @@ static long bcm2835_clock_rate_from_divi +@@ -1218,16 +1218,6 @@ static long bcm2835_clock_rate_from_divi return temp; } @@ -41,7 +41,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, unsigned long parent_rate) { -@@ -1297,13 +1287,75 @@ static int bcm2835_clock_set_rate(struct +@@ -1299,13 +1289,75 @@ static int bcm2835_clock_set_rate(struct return 0; } @@ -118,7 +118,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> }; static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) -@@ -1319,7 +1371,9 @@ static const struct clk_ops bcm2835_vpu_ +@@ -1321,7 +1373,9 @@ static const struct clk_ops bcm2835_vpu_ .is_prepared = bcm2835_vpu_clock_is_on, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, @@ -129,7 +129,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> }; static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, -@@ -1413,45 +1467,23 @@ static struct clk *bcm2835_register_cloc +@@ -1415,45 +1469,23 @@ static struct clk *bcm2835_register_cloc { struct bcm2835_clock *clock; struct clk_init_data init; diff --git a/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch b/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch index 428a952096..aa7bc7d1b6 100644 --- a/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch +++ b/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch @@ -33,7 +33,7 @@ Signed-off-by: Michael Turquette <mturquette@baylibre.com> struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1601,6 +1611,9 @@ static int bcm2835_clk_probe(struct plat +@@ -1603,6 +1613,9 @@ static int bcm2835_clk_probe(struct plat cprman->regs + CM_PERIICTL, CM_GATE_BIT, 0, &cprman->regs_lock); diff --git a/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch b/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch index 737a1a9b64..80a4ba8d23 100644 --- a/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch +++ b/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch @@ -66,7 +66,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> }; struct bcm2835_pll { -@@ -1196,7 +1200,7 @@ static u32 bcm2835_clock_choose_div(stru +@@ -1198,7 +1202,7 @@ static u32 bcm2835_clock_choose_div(stru GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; u64 rem; @@ -75,7 +75,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> rem = do_div(temp, rate); div = temp; -@@ -1206,11 +1210,23 @@ static u32 bcm2835_clock_choose_div(stru +@@ -1208,11 +1212,23 @@ static u32 bcm2835_clock_choose_div(stru div += unused_frac_mask + 1; div &= ~unused_frac_mask; @@ -104,7 +104,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> return div; } -@@ -1304,9 +1320,26 @@ static int bcm2835_clock_set_rate(struct +@@ -1306,9 +1322,26 @@ static int bcm2835_clock_set_rate(struct struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); diff --git a/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch b/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch index 94f75ed567..5a4ae3c653 100644 --- a/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch +++ b/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch @@ -33,7 +33,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> const char *osc_name; struct clk_onecell_data onecell; -@@ -1344,7 +1341,7 @@ static int bcm2835_clock_set_rate(struct +@@ -1346,7 +1343,7 @@ static int bcm2835_clock_set_rate(struct } static int bcm2835_clock_determine_rate(struct clk_hw *hw, @@ -42,7 +42,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct clk_hw *parent, *best_parent = NULL; -@@ -1402,7 +1399,6 @@ static u8 bcm2835_clock_get_parent(struc +@@ -1404,7 +1401,6 @@ static u8 bcm2835_clock_get_parent(struc return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; } diff --git a/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch b/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch index b61bd04f9a..98f08c2905 100644 --- a/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch +++ b/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch @@ -103,7 +103,7 @@ Acked-by: Eric Anholt <eric@anholt.net> }; struct bcm2835_pll_divider { -@@ -1151,6 +1204,26 @@ static int bcm2835_pll_divider_set_rate( +@@ -1153,6 +1206,26 @@ static int bcm2835_pll_divider_set_rate( return 0; } @@ -130,7 +130,7 @@ Acked-by: Eric Anholt <eric@anholt.net> static const struct clk_ops bcm2835_pll_divider_clk_ops = { .is_prepared = bcm2835_pll_divider_is_on, .prepare = bcm2835_pll_divider_on, -@@ -1158,6 +1231,7 @@ static const struct clk_ops bcm2835_pll_ +@@ -1160,6 +1233,7 @@ static const struct clk_ops bcm2835_pll_ .recalc_rate = bcm2835_pll_divider_get_rate, .set_rate = bcm2835_pll_divider_set_rate, .round_rate = bcm2835_pll_divider_round_rate, @@ -138,7 +138,7 @@ Acked-by: Eric Anholt <eric@anholt.net> }; /* -@@ -1399,6 +1473,31 @@ static u8 bcm2835_clock_get_parent(struc +@@ -1401,6 +1475,31 @@ static u8 bcm2835_clock_get_parent(struc return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; } @@ -170,7 +170,7 @@ Acked-by: Eric Anholt <eric@anholt.net> static const struct clk_ops bcm2835_clock_clk_ops = { .is_prepared = bcm2835_clock_is_on, .prepare = bcm2835_clock_on, -@@ -1408,6 +1507,7 @@ static const struct clk_ops bcm2835_cloc +@@ -1410,6 +1509,7 @@ static const struct clk_ops bcm2835_cloc .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, @@ -178,7 +178,7 @@ Acked-by: Eric Anholt <eric@anholt.net> }; static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) -@@ -1426,6 +1526,7 @@ static const struct clk_ops bcm2835_vpu_ +@@ -1428,6 +1528,7 @@ static const struct clk_ops bcm2835_vpu_ .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, diff --git a/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch b/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch index a8b36ae536..58a4c5db36 100644 --- a/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch +++ b/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch @@ -56,7 +56,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1658,14 +1677,81 @@ static struct clk *bcm2835_register_cloc +@@ -1660,14 +1679,81 @@ static struct clk *bcm2835_register_cloc return devm_clk_register(cprman->dev, &clock->hw); } @@ -139,7 +139,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> if (!cprman) return -ENOMEM; -@@ -1682,80 +1768,15 @@ static int bcm2835_clk_probe(struct plat +@@ -1684,80 +1770,15 @@ static int bcm2835_clk_probe(struct plat platform_set_drvdata(pdev, cprman); diff --git a/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch b/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch index 712e14f699..0f1ad866ce 100644 --- a/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch +++ b/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch @@ -473,7 +473,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1594,7 +1177,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1596,7 +1179,7 @@ bcm2835_register_pll_divider(struct bcm2 memset(&init, 0, sizeof(init)); @@ -482,7 +482,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; -@@ -1693,50 +1276,401 @@ struct bcm2835_clk_desc { +@@ -1695,50 +1278,401 @@ struct bcm2835_clk_desc { const void *data; }; diff --git a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch index edf85d6dae..01dd778826 100644 --- a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch +++ b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch @@ -17,7 +17,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1638,6 +1638,13 @@ static const struct bcm2835_clk_desc clk +@@ -1640,6 +1640,13 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_HSMDIV, .int_bits = 4, .frac_bits = 8), diff --git a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch index 58fb0e2474..33d793742d 100644 --- a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch +++ b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch @@ -14,7 +14,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1387,6 +1387,22 @@ static const struct bcm2835_clk_desc clk +@@ -1389,6 +1389,22 @@ static const struct bcm2835_clk_desc clk .load_mask = CM_PLLA_LOADPER, .hold_mask = CM_PLLA_HOLDPER, .fixed_divider = 1), @@ -37,7 +37,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( -@@ -1501,6 +1517,22 @@ static const struct bcm2835_clk_desc clk +@@ -1503,6 +1519,22 @@ static const struct bcm2835_clk_desc clk .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, .fixed_divider = 1), diff --git a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch index 7efe7e0c9a..9ecb0e2bd2 100644 --- a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch +++ b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch @@ -26,7 +26,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> #define CM_EMMCCTL 0x1c0 #define CM_EMMCDIV 0x1c4 -@@ -1610,6 +1612,12 @@ static const struct bcm2835_clk_desc clk +@@ -1612,6 +1614,12 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_TSENSDIV, .int_bits = 5, .frac_bits = 0), @@ -39,7 +39,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* clocks with vpu parent mux */ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( -@@ -1624,6 +1632,7 @@ static const struct bcm2835_clk_desc clk +@@ -1626,6 +1634,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_ISPDIV, .int_bits = 4, .frac_bits = 8), @@ -47,7 +47,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* * Secondary SDRAM clock. Used for low-voltage modes when the PLL * in the SDRAM controller can't be used. -@@ -1655,6 +1664,36 @@ static const struct bcm2835_clk_desc clk +@@ -1657,6 +1666,36 @@ static const struct bcm2835_clk_desc clk .is_vpu_clock = true), /* clocks with per parent mux */ @@ -84,7 +84,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( -@@ -1663,6 +1702,29 @@ static const struct bcm2835_clk_desc clk +@@ -1665,6 +1704,29 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_EMMCDIV, .int_bits = 4, .frac_bits = 8), @@ -114,7 +114,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* HDMI state machine */ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( .name = "hsm", -@@ -1684,12 +1746,26 @@ static const struct bcm2835_clk_desc clk +@@ -1686,12 +1748,26 @@ static const struct bcm2835_clk_desc clk .int_bits = 12, .frac_bits = 12, .is_mash_clock = true), @@ -141,7 +141,7 @@ Reviewed-by: Eric Anholt <eric@anholt.net> /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( .name = "vec", -@@ -1698,6 +1774,20 @@ static const struct bcm2835_clk_desc clk +@@ -1700,6 +1776,20 @@ static const struct bcm2835_clk_desc clk .int_bits = 4, .frac_bits = 0), diff --git a/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch b/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch index 952ff01678..dcd6db28fa 100644 --- a/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch +++ b/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch @@ -27,7 +27,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> bool is_vpu_clock; bool is_mash_clock; }; -@@ -1242,7 +1244,7 @@ static struct clk *bcm2835_register_cloc +@@ -1244,7 +1246,7 @@ static struct clk *bcm2835_register_cloc init.parent_names = parents; init.num_parents = data->num_mux_parents; init.name = data->name; @@ -36,7 +36,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; -@@ -1661,6 +1663,7 @@ static const struct bcm2835_clk_desc clk +@@ -1663,6 +1665,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_VPUDIV, .int_bits = 12, .frac_bits = 8, diff --git a/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch b/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch index 8c56452e82..be63d82f6a 100644 --- a/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch +++ b/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch @@ -19,7 +19,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1246,6 +1246,15 @@ static struct clk *bcm2835_register_cloc +@@ -1248,6 +1248,15 @@ static struct clk *bcm2835_register_cloc init.name = data->name; init.flags = data->flags | CLK_IGNORE_UNUSED; @@ -35,7 +35,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; } else { -@@ -1720,13 +1729,15 @@ static const struct bcm2835_clk_desc clk +@@ -1722,13 +1731,15 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_GP1DIV, .int_bits = 12, .frac_bits = 12, diff --git a/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch b/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch index d2eefe81ed..8b62debd15 100644 --- a/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch +++ b/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch @@ -22,7 +22,7 @@ Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1020,16 +1020,28 @@ static int bcm2835_clock_set_rate(struct +@@ -1022,16 +1022,28 @@ static int bcm2835_clock_set_rate(struct return 0; } @@ -51,7 +51,7 @@ Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain /* * Select parent clock that results in the closest but lower rate */ -@@ -1037,6 +1049,17 @@ static int bcm2835_clock_determine_rate( +@@ -1039,6 +1051,17 @@ static int bcm2835_clock_determine_rate( parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; diff --git a/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch b/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch index 60ad59dec8..77f7aafe56 100644 --- a/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch +++ b/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch @@ -26,7 +26,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> #include <linux/clk/bcm2835.h> #include <linux/debugfs.h> #include <linux/module.h> -@@ -1839,6 +1840,25 @@ static const struct bcm2835_clk_desc clk +@@ -1841,6 +1842,25 @@ static const struct bcm2835_clk_desc clk .ctl_reg = CM_PERIICTL), }; @@ -52,7 +52,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; -@@ -1848,6 +1868,7 @@ static int bcm2835_clk_probe(struct plat +@@ -1850,6 +1870,7 @@ static int bcm2835_clk_probe(struct plat const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); size_t i; @@ -60,7 +60,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> cprman = devm_kzalloc(dev, sizeof(*cprman) + asize * sizeof(*clks), -@@ -1878,6 +1899,10 @@ static int bcm2835_clk_probe(struct plat +@@ -1880,6 +1901,10 @@ static int bcm2835_clk_probe(struct plat clks[i] = desc->clk_register(cprman, desc->data); } diff --git a/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch index c5233b5ed1..5d8d34433c 100644 --- a/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch +++ b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch @@ -16,7 +16,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1209,7 +1209,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1211,7 +1211,7 @@ bcm2835_register_pll_divider(struct bcm2 init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; diff --git a/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch b/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch index e0b3ba2949..e4b5b4526d 100644 --- a/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch +++ b/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch @@ -64,7 +64,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> struct clk_onecell_data onecell; struct clk *clks[]; -@@ -1168,7 +1186,7 @@ static struct clk *bcm2835_register_pll( +@@ -1170,7 +1188,7 @@ static struct clk *bcm2835_register_pll( memset(&init, 0, sizeof(init)); /* All of the PLLs derive from the external oscillator. */ @@ -73,7 +73,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> init.num_parents = 1; init.name = data->name; init.ops = &bcm2835_pll_clk_ops; -@@ -1251,17 +1269,21 @@ static struct clk *bcm2835_register_cloc +@@ -1253,17 +1271,21 @@ static struct clk *bcm2835_register_cloc struct bcm2835_clock *clock; struct clk_init_data init; const char *parents[1 << CM_SRC_BITS]; @@ -102,7 +102,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> } memset(&init, 0, sizeof(init)); -@@ -1883,8 +1905,18 @@ static int bcm2835_clk_probe(struct plat +@@ -1885,8 +1907,18 @@ static int bcm2835_clk_probe(struct plat if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); diff --git a/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch b/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch index 7d6e9f7c9f..3bcb1dab9e 100644 --- a/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch +++ b/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch @@ -11,7 +11,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -934,6 +934,9 @@ static long bcm2835_clock_rate_from_divi +@@ -936,6 +936,9 @@ static long bcm2835_clock_rate_from_divi const struct bcm2835_clock_data *data = clock->data; u64 temp; @@ -21,7 +21,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> /* * The divisor is a 12.12 fixed point field, but only some of * the bits are populated in any given clock. -@@ -957,7 +960,12 @@ static unsigned long bcm2835_clock_get_r +@@ -959,7 +962,12 @@ static unsigned long bcm2835_clock_get_r struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; @@ -35,7 +35,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); } -@@ -1403,6 +1411,28 @@ static const char *const bcm2835_clock_v +@@ -1405,6 +1413,28 @@ static const char *const bcm2835_clock_v __VA_ARGS__) /* @@ -64,7 +64,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net> * the real definition of all the pll, pll_dividers and clocks * these make use of the above REGISTER_* macros */ -@@ -1847,7 +1877,12 @@ static const struct bcm2835_clk_desc clk +@@ -1849,7 +1879,12 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_DSI1EDIV, .int_bits = 4, .frac_bits = 8), |