diff options
Diffstat (limited to 'target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch')
| -rw-r--r-- | target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch b/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch index 61fae23cff..0a06cabe68 100644 --- a/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch +++ b/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch @@ -76,7 +76,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* Must be last */ struct clk_hw_onecell_data onecell; -@@ -911,6 +932,9 @@ static long bcm2835_clock_rate_from_divi +@@ -913,6 +934,9 @@ static long bcm2835_clock_rate_from_divi const struct bcm2835_clock_data *data = clock->data; u64 temp; @@ -86,7 +86,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* * The divisor is a 12.12 fixed point field, but only some of * the bits are populated in any given clock. -@@ -934,7 +958,12 @@ static unsigned long bcm2835_clock_get_r +@@ -936,7 +960,12 @@ static unsigned long bcm2835_clock_get_r struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; @@ -100,7 +100,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); } -@@ -1213,7 +1242,7 @@ static struct clk_hw *bcm2835_register_p +@@ -1215,7 +1244,7 @@ static struct clk_hw *bcm2835_register_p memset(&init, 0, sizeof(init)); /* All of the PLLs derive from the external oscillator. */ @@ -109,7 +109,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> init.num_parents = 1; init.name = data->name; init.ops = &bcm2835_pll_clk_ops; -@@ -1299,18 +1328,22 @@ static struct clk_hw *bcm2835_register_c +@@ -1301,18 +1330,22 @@ static struct clk_hw *bcm2835_register_c struct bcm2835_clock *clock; struct clk_init_data init; const char *parents[1 << CM_SRC_BITS]; @@ -139,7 +139,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> } memset(&init, 0, sizeof(init)); -@@ -1446,6 +1479,47 @@ static const char *const bcm2835_clock_v +@@ -1448,6 +1481,47 @@ static const char *const bcm2835_clock_v __VA_ARGS__) /* @@ -187,7 +187,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> * the real definition of all the pll, pll_dividers and clocks * these make use of the above REGISTER_* macros */ -@@ -1908,6 +1982,18 @@ static const struct bcm2835_clk_desc clk +@@ -1910,6 +1984,18 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_DSI1EDIV, .int_bits = 4, .frac_bits = 8), @@ -206,7 +206,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* the gates */ -@@ -1966,8 +2052,19 @@ static int bcm2835_clk_probe(struct plat +@@ -1968,8 +2054,19 @@ static int bcm2835_clk_probe(struct plat if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); |