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Diffstat (limited to 'target/linux/brcm2708/patches-4.4/0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch')
-rw-r--r--target/linux/brcm2708/patches-4.4/0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch345
1 files changed, 0 insertions, 345 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch b/target/linux/brcm2708/patches-4.4/0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch
deleted file mode 100644
index 75128a74a1..0000000000
--- a/target/linux/brcm2708/patches-4.4/0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch
+++ /dev/null
@@ -1,345 +0,0 @@
-From 610288fc950dc72015acee534573cfdb398c48d2 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Tue, 8 Dec 2015 14:00:43 -0800
-Subject: [PATCH] drm/vc4: A few more non-functional changes to sync to
- upstream.
-
-At this point all that's left is the force-enable of HDMI connector,
-and using direct firmware calls to turn on V3D instead of the generic
-power domain support.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_v3d.c | 2 +-
- include/uapi/drm/vc4_drm.h | 182 +++++++++++++++++++++---------------------
- 2 files changed, 92 insertions(+), 92 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_v3d.c
-+++ b/drivers/gpu/drm/vc4/vc4_v3d.c
-@@ -109,7 +109,7 @@ static const struct {
-
- int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
- {
-- struct drm_info_node *node = (struct drm_info_node *) m->private;
-+ struct drm_info_node *node = (struct drm_info_node *)m->private;
- struct drm_device *dev = node->minor->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- int i;
---- a/include/uapi/drm/vc4_drm.h
-+++ b/include/uapi/drm/vc4_drm.h
-@@ -24,7 +24,7 @@
- #ifndef _UAPI_VC4_DRM_H_
- #define _UAPI_VC4_DRM_H_
-
--#include <drm/drm.h>
-+#include "drm.h"
-
- #define DRM_VC4_SUBMIT_CL 0x00
- #define DRM_VC4_WAIT_SEQNO 0x01
-@@ -34,25 +34,25 @@
- #define DRM_VC4_CREATE_SHADER_BO 0x05
- #define DRM_VC4_GET_HANG_STATE 0x06
-
--#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
--#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
--#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
--#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
--#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
--#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
--#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
-+#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
-+#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
-+#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
-+#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
-+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
-+#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
-+#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
-
- struct drm_vc4_submit_rcl_surface {
-- uint32_t hindex; /* Handle index, or ~0 if not present. */
-- uint32_t offset; /* Offset to start of buffer. */
-+ __u32 hindex; /* Handle index, or ~0 if not present. */
-+ __u32 offset; /* Offset to start of buffer. */
- /*
-- * Bits for either render config (color_write) or load/store packet.
-- * Bits should all be 0 for MSAA load/stores.
-+ * Bits for either render config (color_write) or load/store packet.
-+ * Bits should all be 0 for MSAA load/stores.
- */
-- uint16_t bits;
-+ __u16 bits;
-
- #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
-- uint16_t flags;
-+ __u16 flags;
- };
-
- /**
-@@ -76,7 +76,7 @@ struct drm_vc4_submit_cl {
- * then writes out the state updates and draw calls necessary per tile
- * to the tile allocation BO.
- */
-- uint64_t bin_cl;
-+ __u64 bin_cl;
-
- /* Pointer to the shader records.
- *
-@@ -85,16 +85,16 @@ struct drm_vc4_submit_cl {
- * reference to the shader record has enough information to determine
- * how many pointers are necessary (fixed number for shaders/uniforms,
- * and an attribute count), so those BO indices into bo_handles are
-- * just stored as uint32_ts before each shader record passed in.
-+ * just stored as __u32s before each shader record passed in.
- */
-- uint64_t shader_rec;
-+ __u64 shader_rec;
-
- /* Pointer to uniform data and texture handles for the textures
- * referenced by the shader.
- *
- * For each shader state record, there is a set of uniform data in the
- * order referenced by the record (FS, VS, then CS). Each set of
-- * uniform data has a uint32_t index into bo_handles per texture
-+ * uniform data has a __u32 index into bo_handles per texture
- * sample operation, in the order the QPU_W_TMUn_S writes appear in
- * the program. Following the texture BO handle indices is the actual
- * uniform data.
-@@ -103,52 +103,52 @@ struct drm_vc4_submit_cl {
- * because the kernel has to determine the sizes anyway during shader
- * code validation.
- */
-- uint64_t uniforms;
-- uint64_t bo_handles;
-+ __u64 uniforms;
-+ __u64 bo_handles;
-
- /* Size in bytes of the binner command list. */
-- uint32_t bin_cl_size;
-+ __u32 bin_cl_size;
- /* Size in bytes of the set of shader records. */
-- uint32_t shader_rec_size;
-+ __u32 shader_rec_size;
- /* Number of shader records.
- *
- * This could just be computed from the contents of shader_records and
- * the address bits of references to them from the bin CL, but it
- * keeps the kernel from having to resize some allocations it makes.
- */
-- uint32_t shader_rec_count;
-+ __u32 shader_rec_count;
- /* Size in bytes of the uniform state. */
-- uint32_t uniforms_size;
-+ __u32 uniforms_size;
-
- /* Number of BO handles passed in (size is that times 4). */
-- uint32_t bo_handle_count;
-+ __u32 bo_handle_count;
-
- /* RCL setup: */
-- uint16_t width;
-- uint16_t height;
-- uint8_t min_x_tile;
-- uint8_t min_y_tile;
-- uint8_t max_x_tile;
-- uint8_t max_y_tile;
-+ __u16 width;
-+ __u16 height;
-+ __u8 min_x_tile;
-+ __u8 min_y_tile;
-+ __u8 max_x_tile;
-+ __u8 max_y_tile;
- struct drm_vc4_submit_rcl_surface color_read;
- struct drm_vc4_submit_rcl_surface color_write;
- struct drm_vc4_submit_rcl_surface zs_read;
- struct drm_vc4_submit_rcl_surface zs_write;
- struct drm_vc4_submit_rcl_surface msaa_color_write;
- struct drm_vc4_submit_rcl_surface msaa_zs_write;
-- uint32_t clear_color[2];
-- uint32_t clear_z;
-- uint8_t clear_s;
-+ __u32 clear_color[2];
-+ __u32 clear_z;
-+ __u8 clear_s;
-
-- uint32_t pad:24;
-+ __u32 pad:24;
-
- #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
-- uint32_t flags;
-+ __u32 flags;
-
- /* Returned value of the seqno of this render job (for the
- * wait ioctl).
- */
-- uint64_t seqno;
-+ __u64 seqno;
- };
-
- /**
-@@ -159,8 +159,8 @@ struct drm_vc4_submit_cl {
- * block, just return the status."
- */
- struct drm_vc4_wait_seqno {
-- uint64_t seqno;
-- uint64_t timeout_ns;
-+ __u64 seqno;
-+ __u64 timeout_ns;
- };
-
- /**
-@@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno {
- * completed.
- */
- struct drm_vc4_wait_bo {
-- uint32_t handle;
-- uint32_t pad;
-- uint64_t timeout_ns;
-+ __u32 handle;
-+ __u32 pad;
-+ __u64 timeout_ns;
- };
-
- /**
-@@ -184,11 +184,30 @@ struct drm_vc4_wait_bo {
- * used in a future extension.
- */
- struct drm_vc4_create_bo {
-- uint32_t size;
-- uint32_t flags;
-+ __u32 size;
-+ __u32 flags;
- /** Returned GEM handle for the BO. */
-- uint32_t handle;
-- uint32_t pad;
-+ __u32 handle;
-+ __u32 pad;
-+};
-+
-+/**
-+ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
-+ *
-+ * This doesn't actually perform an mmap. Instead, it returns the
-+ * offset you need to use in an mmap on the DRM device node. This
-+ * means that tools like valgrind end up knowing about the mapped
-+ * memory.
-+ *
-+ * There are currently no values for the flags argument, but it may be
-+ * used in a future extension.
-+ */
-+struct drm_vc4_mmap_bo {
-+ /** Handle for the object being mapped. */
-+ __u32 handle;
-+ __u32 flags;
-+ /** offset into the drm node to use for subsequent mmap call. */
-+ __u64 offset;
- };
-
- /**
-@@ -201,43 +220,24 @@ struct drm_vc4_create_bo {
- */
- struct drm_vc4_create_shader_bo {
- /* Size of the data argument. */
-- uint32_t size;
-+ __u32 size;
- /* Flags, currently must be 0. */
-- uint32_t flags;
-+ __u32 flags;
-
- /* Pointer to the data. */
-- uint64_t data;
-+ __u64 data;
-
- /** Returned GEM handle for the BO. */
-- uint32_t handle;
-+ __u32 handle;
- /* Pad, must be 0. */
-- uint32_t pad;
--};
--
--/**
-- * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
-- *
-- * This doesn't actually perform an mmap. Instead, it returns the
-- * offset you need to use in an mmap on the DRM device node. This
-- * means that tools like valgrind end up knowing about the mapped
-- * memory.
-- *
-- * There are currently no values for the flags argument, but it may be
-- * used in a future extension.
-- */
--struct drm_vc4_mmap_bo {
-- /** Handle for the object being mapped. */
-- uint32_t handle;
-- uint32_t flags;
-- /** offset into the drm node to use for subsequent mmap call. */
-- uint64_t offset;
-+ __u32 pad;
- };
-
- struct drm_vc4_get_hang_state_bo {
-- uint32_t handle;
-- uint32_t paddr;
-- uint32_t size;
-- uint32_t pad;
-+ __u32 handle;
-+ __u32 paddr;
-+ __u32 size;
-+ __u32 pad;
- };
-
- /**
-@@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo {
- */
- struct drm_vc4_get_hang_state {
- /** Pointer to array of struct drm_vc4_get_hang_state_bo. */
-- uint64_t bo;
-+ __u64 bo;
- /**
- * On input, the size of the bo array. Output is the number
- * of bos to be returned.
- */
-- uint32_t bo_count;
-+ __u32 bo_count;
-
-- uint32_t start_bin, start_render;
-+ __u32 start_bin, start_render;
-
-- uint32_t ct0ca, ct0ea;
-- uint32_t ct1ca, ct1ea;
-- uint32_t ct0cs, ct1cs;
-- uint32_t ct0ra0, ct1ra0;
--
-- uint32_t bpca, bpcs;
-- uint32_t bpoa, bpos;
--
-- uint32_t vpmbase;
--
-- uint32_t dbge;
-- uint32_t fdbgo;
-- uint32_t fdbgb;
-- uint32_t fdbgr;
-- uint32_t fdbgs;
-- uint32_t errstat;
-+ __u32 ct0ca, ct0ea;
-+ __u32 ct1ca, ct1ea;
-+ __u32 ct0cs, ct1cs;
-+ __u32 ct0ra0, ct1ra0;
-+
-+ __u32 bpca, bpcs;
-+ __u32 bpoa, bpos;
-+
-+ __u32 vpmbase;
-+
-+ __u32 dbge;
-+ __u32 fdbgo;
-+ __u32 fdbgb;
-+ __u32 fdbgr;
-+ __u32 fdbgs;
-+ __u32 errstat;
-
- /* Pad that we may save more registers into in the future. */
-- uint32_t pad[16];
-+ __u32 pad[16];
- };
-
- #endif /* _UAPI_VC4_DRM_H_ */
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