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-rw-r--r--target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch369
1 files changed, 0 insertions, 369 deletions
diff --git a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
deleted file mode 100644
index d9e4dd78bb..0000000000
--- a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
+++ /dev/null
@@ -1,369 +0,0 @@
-diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S
---- linux-2.6.19.ref/arch/mips/kernel/genex.S 2006-11-29 22:57:37.000000000 +0100
-+++ linux-2.6.19/arch/mips/kernel/genex.S 2006-12-04 21:34:09.000000000 +0100
-@@ -73,6 +73,10 @@
- .set push
- .set mips3
- .set noat
-+#ifdef CONFIG_BCM947XX
-+ nop
-+ nop
-+#endif
- mfc0 k1, CP0_CAUSE
- li k0, 31<<2
- andi k1, k1, 0x7c
-diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
---- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100
-+++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:09.000000000 +0100
-@@ -13,6 +13,15 @@
- #include <linux/mm.h>
- #include <linux/bitops.h>
-
-+#ifdef CONFIG_BCM947XX
-+#include "../bcm947xx/include/typedefs.h"
-+#include "../bcm947xx/include/sbconfig.h"
-+#include "../bcm947xx/include/mipsinc.h"
-+#undef MTC0
-+#undef MFC0
-+#undef cache_op
-+#include <asm/paccess.h>
-+#endif
- #include <asm/bcache.h>
- #include <asm/bootinfo.h>
- #include <asm/cache.h>
-@@ -29,6 +38,9 @@
- #include <asm/cacheflush.h> /* for run_uncached() */
-
-
-+/* For enabling BCM4710 cache workarounds */
-+int bcm4710 = 0;
-+
- /*
- * Special Variant of smp_call_function for use by cache functions:
- *
-@@ -93,6 +105,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page = blast_dcache_page;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -107,6 +122,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page_indexed = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -121,6 +139,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache = blast_dcache;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -538,6 +559,9 @@
- r4k_blast_icache();
- else
- protected_blast_icache_range(start, end);
-+
-+ if (bcm4710)
-+ r4k_flush_cache_all();
- }
-
- static void r4k_flush_icache_range(unsigned long start, unsigned long end)
-@@ -618,6 +642,8 @@
- unsigned long addr = (unsigned long) arg;
-
- R4600_HIT_CACHEOP_WAR_IMPL;
-+ BCM4710_PROTECTED_FILL_TLB(addr);
-+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
- if (dc_lsize)
- protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1135,6 +1161,16 @@
- static void __init coherency_setup(void)
- {
- change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
-+#ifdef CONFIG_BCM947XX
-+ if (BCM330X(current_cpu_data.processor_id)) {
-+ __u32 cm = read_c0_diag();
-+ /* Enable icache */
-+ cm |= (1 << 31);
-+ /* Enable dcache */
-+ cm |= (1 << 30);
-+ write_c0_diag(cm);
-+ }
-+#endif
-
- /*
- * c0_status.cu=0 specifies that updates by the sc instruction use
-@@ -1173,6 +1209,15 @@
-
- /* Default cache error handler for R4000 and R5000 family */
- set_uncached_handler (0x100, &except_vec2_generic, 0x80);
-+
-+ /* Check if special workarounds are required */
-+#ifdef CONFIG_BCM947XX
-+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
-+ printk("Enabling BCM4710A0 cache workarounds.\n");
-+ bcm4710 = 1;
-+ } else
-+#endif
-+ bcm4710 = 0;
-
- probe_pcache();
- setup_scache();
-diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c
---- linux-2.6.19.ref/arch/mips/mm/tlbex.c 2006-12-04 21:33:48.000000000 +0100
-+++ linux-2.6.19/arch/mips/mm/tlbex.c 2006-12-04 21:34:09.000000000 +0100
-@@ -1174,6 +1174,10 @@
- #endif
- }
-
-+#ifdef CONFIG_BCM947XX
-+extern int bcm4710;
-+#endif
-+
- static void __init build_r4000_tlb_refill_handler(void)
- {
- u32 *p = tlb_handler;
-@@ -1188,6 +1192,12 @@
- memset(relocs, 0, sizeof(relocs));
- memset(final_handler, 0, sizeof(final_handler));
-
-+#ifdef CONFIG_BCM947XX
-+ if (bcm4710) {
-+ i_nop(&p);
-+ }
-+#endif
-+
- /*
- * create the plain linear handler
- */
-diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h
---- linux-2.6.19.ref/include/asm-mips/r4kcache.h 2006-11-29 22:57:37.000000000 +0100
-+++ linux-2.6.19/include/asm-mips/r4kcache.h 2006-12-04 21:34:09.000000000 +0100
-@@ -17,6 +17,18 @@
- #include <asm/cpu-features.h>
- #include <asm/mipsmtregs.h>
-
-+#ifdef CONFIG_BCM947XX
-+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
-+
-+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
-+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations. Two issues here:
-@@ -150,6 +162,7 @@
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Index_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -169,6 +182,7 @@
- static inline void flush_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -176,6 +190,7 @@
- static inline void invalidate_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Invalidate_D, addr);
- __dflush_epilogue
- }
-@@ -208,6 +223,7 @@
- */
- static inline void protected_flush_icache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Invalidate_I, addr);
- }
-
-@@ -219,6 +235,7 @@
- */
- static inline void protected_writeback_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
-
-@@ -339,8 +356,52 @@
- : "r" (base), \
- "i" (op));
-
-+static inline void blast_dcache(void)
-+{
-+ unsigned long start = KSEG0;
-+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+ unsigned long end = (start + dcache_size);
-+
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+
-+ BCM4710_FILL_TLB(start);
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Hit_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+ unsigned long ws_end = current_cpu_data.dcache.ways <<
-+ current_cpu_data.dcache.waybit;
-+ unsigned long ws, addr;
-+ for (ws = 0; ws < ws_end; ws += ws_inc) {
-+ start = page + ws;
-+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, addr);
-+ }
-+ }
-+}
-+
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
- static inline void blast_##pfx##cache##lsize(void) \
- { \
- unsigned long start = INDEX_BASE; \
-@@ -352,6 +413,7 @@
- \
- __##pfx##flush_prologue \
- \
-+ war \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
- for (addr = start; addr < end; addr += lsize * 32) \
- cache##lsize##_unroll32(addr|ws,indexop); \
-@@ -366,6 +428,7 @@
- \
- __##pfx##flush_prologue \
- \
-+ war \
- do { \
- cache##lsize##_unroll32(start,hitop); \
- start += lsize * 32; \
-@@ -384,6 +447,8 @@
- current_cpu_data.desc.waybit; \
- unsigned long ws, addr; \
- \
-+ war \
-+ \
- __##pfx##flush_prologue \
- \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -393,28 +458,30 @@
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
- static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
- unsigned long end) \
- { \
- unsigned long lsize = cpu_##desc##_line_size(); \
- unsigned long addr = start & ~(lsize - 1); \
- unsigned long aend = (end - 1) & ~(lsize - 1); \
-+ war \
- \
- __##pfx##flush_prologue \
- \
- while (1) { \
-+ war2 \
- prot##cache_op(hitop, addr); \
- if (addr == aend) \
- break; \
-@@ -424,13 +491,13 @@
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
-
- #endif /* _ASM_R4KCACHE_H */
-diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h
---- linux-2.6.19.ref/include/asm-mips/stackframe.h 2006-11-29 22:57:37.000000000 +0100
-+++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100
-@@ -334,6 +334,10 @@
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
- .set mips3
-+#ifdef CONFIG_BCM947XX
-+ nop
-+ nop
-+#endif
- eret
- .set mips0
- .endm