diff options
Diffstat (limited to 'target/linux/brcm-2.4/files/arch')
54 files changed, 0 insertions, 19811 deletions
diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/Makefile b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/Makefile deleted file mode 100644 index e08cf9acb4..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Makefile for the BCM947xx specific kernel interface routines -# under Linux. -# - -EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER - -O_TARGET := bcm947xx.o - -export-objs := export.o -obj-y := prom.o setup.o time.o sbmips.o gpio.o -obj-y += nvram.o cfe_env.o hndpmu.o -obj-y += sbutils.o utils.o bcmsrom.o hndchipc.o -obj-$(CONFIG_PCI) += sbpci.o pcibios.o -obj-y += export.o - -include $(TOPDIR)/Rules.make diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/bcmsrom.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/bcmsrom.c deleted file mode 100644 index 4cf73b5af8..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/bcmsrom.c +++ /dev/null @@ -1,2104 +0,0 @@ -/* - * Routines to access SPROM and to parse SROM/CIS variables. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#include <typedefs.h> -#include <bcmdefs.h> -#include <osl.h> -#include <stdarg.h> -#include <sbchipc.h> -#include <bcmdevs.h> -#include <bcmendian.h> -#include <sbpcmcia.h> -#include <pcicfg.h> -#include <sbconfig.h> -#include <sbutils.h> -#include <bcmsrom.h> -#include <bcmnvram.h> -#include "utils.h" - -/* debug/trace */ -#if defined(WLTEST) -#define BS_ERROR(args) printf args -#else -#define BS_ERROR(args) -#endif - -#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */ -#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */ - -typedef struct varbuf -{ - char *buf; /* pointer to current position */ - unsigned int size; /* current (residual) size in bytes */ -} varbuf_t; - -static int initvars_srom_sb (sb_t * sbh, osl_t * osh, void *curmap, - char **vars, uint * count); -static void _initvars_srom_pci (uint8 sromrev, uint16 * srom, uint off, - varbuf_t * b); -static int initvars_srom_pci (sb_t * sbh, void *curmap, char **vars, - uint * count); -static int initvars_cis_pcmcia (sb_t * sbh, osl_t * osh, char **vars, - uint * count); -#if !defined(BCMUSBDEV) && !defined(BCMSDIODEV) -static int initvars_flash_sb (sb_t * sbh, char **vars, uint * count); -#endif /* !BCMUSBDEV && !BCMSDIODEV */ -static int sprom_cmd_pcmcia (osl_t * osh, uint8 cmd); -static int sprom_read_pcmcia (osl_t * osh, uint16 addr, uint16 * data); -static int sprom_write_pcmcia (osl_t * osh, uint16 addr, uint16 data); -static int sprom_read_pci (osl_t * osh, uint16 * sprom, uint wordoff, - uint16 * buf, uint nwords, bool check_crc); - -static int initvars_table (osl_t * osh, char *start, char *end, char **vars, - uint * count); -static int initvars_flash (sb_t * sbh, osl_t * osh, char **vp, uint len); - -#ifdef BCMUSBDEV -static int get_sb_pcmcia_srom (sb_t * sbh, osl_t * osh, uint8 * pcmregs, - uint boff, uint16 * srom, uint bsz); -static int set_sb_pcmcia_srom (sb_t * sbh, osl_t * osh, uint8 * pcmregs, - uint boff, uint16 * srom, uint bsz); -static uint srom_size (sb_t * sbh, osl_t * osh); -#endif /* def BCMUSBDEV */ - -/* Initialization of varbuf structure */ -static void -varbuf_init (varbuf_t * b, char *buf, uint size) -{ - b->size = size; - b->buf = buf; -} - -/* append a null terminated var=value string */ -static int -varbuf_append (varbuf_t * b, const char *fmt, ...) -{ - va_list ap; - int r; - - if (b->size < 2) - return 0; - - va_start (ap, fmt); - r = vsnprintf (b->buf, b->size, fmt, ap); - va_end (ap); - - /* C99 snprintf behavior returns r >= size on overflow, - * others return -1 on overflow. - * All return -1 on format error. - * We need to leave room for 2 null terminations, one for the current var - * string, and one for final null of the var table. So check that the - * strlen written, r, leaves room for 2 chars. - */ - if ((r == -1) || (r > (int) (b->size - 2))) - { - b->size = 0; - return 0; - } - - /* skip over this string's null termination */ - r++; - b->size -= r; - b->buf += r; - - return r; -} - -/* - * Initialize local vars from the right source for this platform. - * Return 0 on success, nonzero on error. - */ -int -BCMINITFN (srom_var_init) (sb_t * sbh, uint bustype, void *curmap, - osl_t * osh, char **vars, uint * count) -{ - ASSERT (bustype == BUSTYPE (bustype)); - if (vars == NULL || count == NULL) - return (0); - - *vars = NULL; - *count = 0; - - switch (BUSTYPE (bustype)) - { - case SB_BUS: - case JTAG_BUS: - return initvars_srom_sb (sbh, osh, curmap, vars, count); - - case PCI_BUS: - ASSERT (curmap); /* can not be NULL */ - return initvars_srom_pci (sbh, curmap, vars, count); - - case PCMCIA_BUS: - return initvars_cis_pcmcia (sbh, osh, vars, count); - - - default: - ASSERT (0); - } - return (-1); -} - -/* support only 16-bit word read from srom */ -int -srom_read (sb_t * sbh, uint bustype, void *curmap, osl_t * osh, - uint byteoff, uint nbytes, uint16 * buf) -{ - void *srom; - uint i, off, nw; - - ASSERT (bustype == BUSTYPE (bustype)); - - /* check input - 16-bit access only */ - if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2)) - return 1; - - off = byteoff / 2; - nw = nbytes / 2; - - if (BUSTYPE (bustype) == PCI_BUS) - { - if (!curmap) - return 1; - srom = (uchar *) curmap + PCI_BAR0_SPROM_OFFSET; - if (sprom_read_pci (osh, srom, off, buf, nw, FALSE)) - return 1; - } - else if (BUSTYPE (bustype) == PCMCIA_BUS) - { - for (i = 0; i < nw; i++) - { - if (sprom_read_pcmcia - (osh, (uint16) (off + i), (uint16 *) (buf + i))) - return 1; - } - } - else if (BUSTYPE (bustype) == SB_BUS) - { -#ifdef BCMUSBDEV - if (SPROMBUS == PCMCIA_BUS) - { - uint origidx; - void *regs; - int rc; - bool wasup; - - origidx = sb_coreidx (sbh); - regs = sb_setcore (sbh, SB_PCMCIA, 0); - ASSERT (regs != NULL); - - if (!(wasup = sb_iscoreup (sbh))) - sb_core_reset (sbh, 0, 0); - - rc = get_sb_pcmcia_srom (sbh, osh, regs, byteoff, buf, nbytes); - - if (!wasup) - sb_core_disable (sbh, 0); - - sb_setcoreidx (sbh, origidx); - return rc; - } -#endif /* def BCMUSBDEV */ - - return 1; - } - else - { - return 1; - } - - return 0; -} - -/* support only 16-bit word write into srom */ -int -srom_write (sb_t * sbh, uint bustype, void *curmap, osl_t * osh, - uint byteoff, uint nbytes, uint16 * buf) -{ - uint16 *srom; - uint i, nw, crc_range; - uint16 image[SPROM_SIZE]; - uint8 crc; - volatile uint32 val32; - - ASSERT (bustype == BUSTYPE (bustype)); - - /* check input - 16-bit access only */ - if ((byteoff & 1) || (nbytes & 1)) - return 1; - - if (byteoff == 0x55aa) - { - /* Erase request */ - crc_range = 0; - memset ((void *) image, 0xff, nbytes); - nw = nbytes / 2; - } - else if ((byteoff == 0) && - ((nbytes == SPROM_SIZE * 2) || - (nbytes == (SPROM_CRC_RANGE * 2)) || - (nbytes == (SROM4_WORDS * 2)))) - { - /* Are we writing the whole thing at once? */ - crc_range = nbytes; - bcopy ((void *) buf, (void *) image, nbytes); - nw = nbytes / 2; - } - else - { - if ((byteoff + nbytes) > (SPROM_SIZE * 2)) - return 1; - - if (BUSTYPE (bustype) == PCMCIA_BUS) - { - crc_range = SPROM_SIZE * 2; - } - else - { - crc_range = SPROM_CRC_RANGE * 2; /* Tentative */ - } - - nw = crc_range / 2; - /* read first 64 words from srom */ - if (srom_read (sbh, bustype, curmap, osh, 0, crc_range, image)) - return 1; - if (image[SROM4_SIGN] == SROM4_SIGNATURE) - { - nw = SROM4_WORDS; - crc_range = nw * 2; - if (srom_read (sbh, bustype, curmap, osh, 0, crc_range, image)) - return 1; - } - /* make changes */ - bcopy ((void *) buf, (void *) &image[byteoff / 2], nbytes); - } - - if (crc_range) - { - /* calculate crc */ - htol16_buf (image, crc_range); - crc = ~hndcrc8 ((uint8 *) image, crc_range - 1, 0xff); - ltoh16_buf (image, crc_range); - image[nw - 1] = (crc << 8) | (image[nw - 1] & 0xff); - } - - if (BUSTYPE (bustype) == PCI_BUS) - { - srom = (uint16 *) ((uchar *) curmap + PCI_BAR0_SPROM_OFFSET); - /* enable writes to the SPROM */ - val32 = OSL_PCI_READ_CONFIG (osh, PCI_SPROM_CONTROL, sizeof (uint32)); - val32 |= SPROM_WRITEEN; - OSL_PCI_WRITE_CONFIG (osh, PCI_SPROM_CONTROL, sizeof (uint32), val32); - bcm_mdelay (WRITE_ENABLE_DELAY); - /* write srom */ - for (i = 0; i < nw; i++) - { - W_REG (osh, &srom[i], image[i]); - bcm_mdelay (WRITE_WORD_DELAY); - } - /* disable writes to the SPROM */ - OSL_PCI_WRITE_CONFIG (osh, PCI_SPROM_CONTROL, sizeof (uint32), val32 & - ~SPROM_WRITEEN); - } - else if (BUSTYPE (bustype) == PCMCIA_BUS) - { - /* enable writes to the SPROM */ - if (sprom_cmd_pcmcia (osh, SROM_WEN)) - return 1; - bcm_mdelay (WRITE_ENABLE_DELAY); - /* write srom */ - for (i = 0; i < nw; i++) - { - sprom_write_pcmcia (osh, (uint16) (i), image[i]); - bcm_mdelay (WRITE_WORD_DELAY); - } - /* disable writes to the SPROM */ - if (sprom_cmd_pcmcia (osh, SROM_WDS)) - return 1; - } - else if (BUSTYPE (bustype) == SB_BUS) - { -#ifdef BCMUSBDEV - if (SPROMBUS == PCMCIA_BUS) - { - uint origidx; - void *regs; - int rc; - bool wasup; - - origidx = sb_coreidx (sbh); - regs = sb_setcore (sbh, SB_PCMCIA, 0); - ASSERT (regs != NULL); - - if (!(wasup = sb_iscoreup (sbh))) - sb_core_reset (sbh, 0, 0); - - rc = set_sb_pcmcia_srom (sbh, osh, regs, byteoff, buf, nbytes); - - if (!wasup) - sb_core_disable (sbh, 0); - - sb_setcoreidx (sbh, origidx); - return rc; - } -#endif /* def BCMUSBDEV */ - return 1; - } - else - { - return 1; - } - - bcm_mdelay (WRITE_ENABLE_DELAY); - return 0; -} - -#ifdef BCMUSBDEV -#define SB_PCMCIA_READ(osh, regs, fcr) \ - R_REG(osh, (volatile uint8 *)(regs) + 0x600 + (fcr) - 0x700 / 2) -#define SB_PCMCIA_WRITE(osh, regs, fcr, v) \ - W_REG(osh, (volatile uint8 *)(regs) + 0x600 + (fcr) - 0x700 / 2, v) - -/* set PCMCIA srom command register */ -static int -srom_cmd_sb_pcmcia (osl_t * osh, uint8 * pcmregs, uint8 cmd) -{ - uint8 status = 0; - uint wait_cnt = 0; - - /* write srom command register */ - SB_PCMCIA_WRITE (osh, pcmregs, SROM_CS, cmd); - - /* wait status */ - while (++wait_cnt < 1000000) - { - status = SB_PCMCIA_READ (osh, pcmregs, SROM_CS); - if (status & SROM_DONE) - return 0; - OSL_DELAY (1); - } - - BS_ERROR (("sr_cmd: Give up after %d tries, stat = 0x%x\n", wait_cnt, - status)); - return 1; -} - -/* read a word from the PCMCIA srom over SB */ -static int -srom_read_sb_pcmcia (osl_t * osh, uint8 * pcmregs, uint16 addr, uint16 * data) -{ - uint8 addr_l, addr_h, data_l, data_h; - - addr_l = (uint8) ((addr * 2) & 0xff); - addr_h = (uint8) (((addr * 2) >> 8) & 0xff); - - /* set address */ - SB_PCMCIA_WRITE (osh, pcmregs, SROM_ADDRH, addr_h); - SB_PCMCIA_WRITE (osh, pcmregs, SROM_ADDRL, addr_l); - - /* do read */ - if (srom_cmd_sb_pcmcia (osh, pcmregs, SROM_READ)) - return 1; - - /* read data */ - data_h = SB_PCMCIA_READ (osh, pcmregs, SROM_DATAH); - data_l = SB_PCMCIA_READ (osh, pcmregs, SROM_DATAL); - *data = ((uint16) data_h << 8) | data_l; - - return 0; -} - -/* write a word to the PCMCIA srom over SB */ -static int -srom_write_sb_pcmcia (osl_t * osh, uint8 * pcmregs, uint16 addr, uint16 data) -{ - uint8 addr_l, addr_h, data_l, data_h; - int rc; - - addr_l = (uint8) ((addr * 2) & 0xff); - addr_h = (uint8) (((addr * 2) >> 8) & 0xff); - - /* set address */ - SB_PCMCIA_WRITE (osh, pcmregs, SROM_ADDRH, addr_h); - SB_PCMCIA_WRITE (osh, pcmregs, SROM_ADDRL, addr_l); - - data_l = (uint8) (data & 0xff); - data_h = (uint8) ((data >> 8) & 0xff); - - /* write data */ - SB_PCMCIA_WRITE (osh, pcmregs, SROM_DATAH, data_h); - SB_PCMCIA_WRITE (osh, pcmregs, SROM_DATAL, data_l); - - /* do write */ - rc = srom_cmd_sb_pcmcia (osh, pcmregs, SROM_WRITE); - OSL_DELAY (20000); - return rc; -} - -/* - * Read the srom for the pcmcia-srom over sb case. - * Return 0 on success, nonzero on error. - */ -static int -get_sb_pcmcia_srom (sb_t * sbh, osl_t * osh, uint8 * pcmregs, - uint boff, uint16 * srom, uint bsz) -{ - uint i, nw, woff, wsz; - int err = 0; - - /* read must be at word boundary */ - ASSERT ((boff & 1) == 0 && (bsz & 1) == 0); - - /* read sprom size and validate the parms */ - if ((nw = srom_size (sbh, osh)) == 0) - { - BS_ERROR (("get_sb_pcmcia_srom: sprom size unknown\n")); - err = -1; - goto out; - } - if (boff + bsz > 2 * nw) - { - BS_ERROR (("get_sb_pcmcia_srom: sprom size exceeded\n")); - err = -2; - goto out; - } - - /* read in sprom contents */ - for (woff = boff / 2, wsz = bsz / 2, i = 0; - woff < nw && i < wsz; woff++, i++) - { - if (srom_read_sb_pcmcia (osh, pcmregs, (uint16) woff, &srom[i])) - { - BS_ERROR (("get_sb_pcmcia_srom: sprom read failed\n")); - err = -3; - goto out; - } - } - -out: - return err; -} - -/* - * Write the srom for the pcmcia-srom over sb case. - * Return 0 on success, nonzero on error. - */ -static int -set_sb_pcmcia_srom (sb_t * sbh, osl_t * osh, uint8 * pcmregs, - uint boff, uint16 * srom, uint bsz) -{ - uint i, nw, woff, wsz; - uint16 word; - uint8 crc; - int err = 0; - - /* write must be at word boundary */ - ASSERT ((boff & 1) == 0 && (bsz & 1) == 0); - - /* read sprom size and validate the parms */ - if ((nw = srom_size (sbh, osh)) == 0) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom size unknown\n")); - err = -1; - goto out; - } - if (boff + bsz > 2 * nw) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom size exceeded\n")); - err = -2; - goto out; - } - - /* enable write */ - if (srom_cmd_sb_pcmcia (osh, pcmregs, SROM_WEN)) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom wen failed\n")); - err = -3; - goto out; - } - - /* write buffer to sprom */ - for (woff = boff / 2, wsz = bsz / 2, i = 0; - woff < nw && i < wsz; woff++, i++) - { - if (srom_write_sb_pcmcia (osh, pcmregs, (uint16) woff, srom[i])) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom write failed\n")); - err = -4; - goto out; - } - } - - /* fix crc */ - crc = 0xff; - for (woff = 0; woff < nw; woff++) - { - if (srom_read_sb_pcmcia (osh, pcmregs, (uint16) woff, &word)) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom fix crc read failed\n")); - err = -5; - goto out; - } - word = htol16 (word); - crc = hndcrc8 ((uint8 *) & word, woff != nw - 1 ? 2 : 1, crc); - } - word = (~crc << 8) + (ltoh16 (word) & 0xff); - if (srom_write_sb_pcmcia (osh, pcmregs, (uint16) (woff - 1), word)) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom fix crc write failed\n")); - err = -6; - goto out; - } - - /* disable write */ - if (srom_cmd_sb_pcmcia (osh, pcmregs, SROM_WDS)) - { - BS_ERROR (("set_sb_pcmcia_srom: sprom wds failed\n")); - err = -7; - goto out; - } - -out: - return err; -} -#endif /* def BCMUSBDEV */ - -int -srom_parsecis (osl_t * osh, uint8 * pcis[], uint ciscnt, char **vars, - uint * count) -{ - char eabuf[32]; - char *base; - varbuf_t b; - uint8 *cis, tup, tlen, sromrev = 1; - int i, j; - uint varsize; - bool ag_init = FALSE; - uint32 w32; - uint funcid; - uint cisnum; - int32 boardnum = -1; - - ASSERT (vars); - ASSERT (count); - - base = MALLOC (osh, MAXSZ_NVRAM_VARS); - ASSERT (base); - if (!base) - return -2; - - varbuf_init (&b, base, MAXSZ_NVRAM_VARS); - - eabuf[0] = '\0'; - for (cisnum = 0; cisnum < ciscnt; cisnum++) - { - cis = *pcis++; - i = 0; - funcid = 0; - do - { - tup = cis[i++]; - tlen = cis[i++]; - if ((i + tlen) >= CIS_SIZE) - break; - - switch (tup) - { - case CISTPL_VERS_1: - /* assume the strings are good if the version field checks out */ - if (((cis[i + 1] << 8) + cis[i]) >= 0x0008) - { - varbuf_append (&b, "manf=%s", &cis[i + 2]); - varbuf_append (&b, "productname=%s", - &cis[i + 3 + strlen ((char *) &cis[i + 2])]); - break; - } - - case CISTPL_MANFID: - varbuf_append (&b, "manfid=0x%x", (cis[i + 1] << 8) + cis[i]); - varbuf_append (&b, "prodid=0x%x", - (cis[i + 3] << 8) + cis[i + 2]); - break; - - case CISTPL_FUNCID: - funcid = cis[i]; - break; - - case CISTPL_FUNCE: - switch (funcid) - { - default: - /* set macaddr if HNBU_MACADDR not seen yet */ - if (eabuf[0] == '\0' && cis[i] == LAN_NID) - { - ASSERT (cis[i + 1] == ETHER_ADDR_LEN); - bcm_ether_ntoa ((struct ether_addr *) &cis[i + 2], - eabuf); - } - /* set boardnum if HNBU_BOARDNUM not seen yet */ - if (boardnum == -1) - boardnum = (cis[i + 6] << 8) + cis[i + 7]; - break; - } - break; - - case CISTPL_CFTABLE: - varbuf_append (&b, "regwindowsz=%d", - (cis[i + 7] << 8) | cis[i + 6]); - break; - - case CISTPL_BRCM_HNBU: - switch (cis[i]) - { - case HNBU_SROMREV: - sromrev = cis[i + 1]; - varbuf_append (&b, "sromrev=%d", sromrev); - break; - - case HNBU_CHIPID: - varbuf_append (&b, "vendid=0x%x", (cis[i + 2] << 8) + - cis[i + 1]); - varbuf_append (&b, "devid=0x%x", (cis[i + 4] << 8) + - cis[i + 3]); - if (tlen >= 7) - { - varbuf_append (&b, "chiprev=%d", - (cis[i + 6] << 8) + cis[i + 5]); - } - if (tlen >= 9) - { - varbuf_append (&b, "subvendid=0x%x", - (cis[i + 8] << 8) + cis[i + 7]); - } - if (tlen >= 11) - { - varbuf_append (&b, "subdevid=0x%x", - (cis[i + 10] << 8) + cis[i + 9]); - /* subdevid doubles for boardtype */ - varbuf_append (&b, "boardtype=0x%x", - (cis[i + 10] << 8) + cis[i + 9]); - } - break; - - case HNBU_BOARDREV: - varbuf_append (&b, "boardrev=0x%x", cis[i + 1]); - break; - - case HNBU_AA: - varbuf_append (&b, "aa2g=%d", cis[i + 1]); - break; - - case HNBU_AG: - varbuf_append (&b, "ag0=%d", cis[i + 1]); - ag_init = TRUE; - break; - - case HNBU_ANT5G: - varbuf_append (&b, "aa5g=%d", cis[i + 1]); - varbuf_append (&b, "ag1=%d", cis[i + 2]); - break; - - case HNBU_CC: - ASSERT (sromrev == 1); - varbuf_append (&b, "cc=%d", cis[i + 1]); - break; - - case HNBU_PAPARMS: - if (tlen == 2) - { - ASSERT (sromrev == 1); - varbuf_append (&b, "pa0maxpwr=%d", cis[i + 1]); - } - else if (tlen >= 9) - { - if (tlen == 10) - { - ASSERT (sromrev >= 2); - varbuf_append (&b, "opo=%d", cis[i + 9]); - } - else - ASSERT (tlen == 9); - - for (j = 0; j < 3; j++) - { - varbuf_append (&b, "pa0b%d=%d", j, - (cis[i + (j * 2) + 2] << 8) + - cis[i + (j * 2) + 1]); - } - varbuf_append (&b, "pa0itssit=%d", cis[i + 7]); - varbuf_append (&b, "pa0maxpwr=%d", cis[i + 8]); - } - else - ASSERT (tlen >= 9); - break; - - case HNBU_PAPARMS5G: - ASSERT ((sromrev == 2) || (sromrev == 3)); - for (j = 0; j < 3; j++) - { - varbuf_append (&b, "pa1b%d=%d", j, - (cis[i + (j * 2) + 2] << 8) + - cis[i + (j * 2) + 1]); - } - for (j = 3; j < 6; j++) - { - varbuf_append (&b, "pa1lob%d=%d", j - 3, - (cis[i + (j * 2) + 2] << 8) + - cis[i + (j * 2) + 1]); - } - for (j = 6; j < 9; j++) - { - varbuf_append (&b, "pa1hib%d=%d", j - 6, - (cis[i + (j * 2) + 2] << 8) + - cis[i + (j * 2) + 1]); - } - varbuf_append (&b, "pa1itssit=%d", cis[i + 19]); - varbuf_append (&b, "pa1maxpwr=%d", cis[i + 20]); - varbuf_append (&b, "pa1lomaxpwr=%d", cis[i + 21]); - varbuf_append (&b, "pa1himaxpwr=%d", cis[i + 22]); - break; - - case HNBU_OEM: - ASSERT (sromrev == 1); - varbuf_append (&b, "oem=%02x%02x%02x%02x%02x%02x%02x%02x", - cis[i + 1], cis[i + 2], - cis[i + 3], cis[i + 4], - cis[i + 5], cis[i + 6], - cis[i + 7], cis[i + 8]); - break; - - case HNBU_BOARDFLAGS: - w32 = (cis[i + 2] << 8) + cis[i + 1]; - if (tlen == 5) - w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16); - varbuf_append (&b, "boardflags=0x%x", w32); - break; - - case HNBU_LEDS: - if (cis[i + 1] != 0xff) - { - varbuf_append (&b, "ledbh0=%d", cis[i + 1]); - } - if (cis[i + 2] != 0xff) - { - varbuf_append (&b, "ledbh1=%d", cis[i + 2]); - } - if (cis[i + 3] != 0xff) - { - varbuf_append (&b, "ledbh2=%d", cis[i + 3]); - } - if (cis[i + 4] != 0xff) - { - varbuf_append (&b, "ledbh3=%d", cis[i + 4]); - } - break; - - case HNBU_CCODE: - ASSERT (sromrev > 1); - if ((cis[i + 1] == 0) || (cis[i + 2] == 0)) - varbuf_append (&b, "ccode="); - else - varbuf_append (&b, "ccode=%c%c", cis[i + 1], cis[i + 2]); - varbuf_append (&b, "cctl=0x%x", cis[i + 3]); - break; - - case HNBU_CCKPO: - ASSERT (sromrev > 2); - varbuf_append (&b, "cckpo=0x%x", - (cis[i + 2] << 8) | cis[i + 1]); - break; - - case HNBU_OFDMPO: - ASSERT (sromrev > 2); - varbuf_append (&b, "ofdmpo=0x%x", - (cis[i + 4] << 24) | - (cis[i + 3] << 16) | - (cis[i + 2] << 8) | cis[i + 1]); - break; - - case HNBU_RDLID: - varbuf_append (&b, "rdlid=0x%x", - (cis[i + 2] << 8) | cis[i + 1]); - break; - - case HNBU_RDLRNDIS: - varbuf_append (&b, "rdlrndis=%d", cis[i + 1]); - break; - - case HNBU_RDLRWU: - varbuf_append (&b, "rdlrwu=%d", cis[i + 1]); - break; - - case HNBU_RDLSN: - varbuf_append (&b, "rdlsn=%d", - (cis[i + 2] << 8) | cis[i + 1]); - break; - - case HNBU_XTALFREQ: - varbuf_append (&b, "xtalfreq=%d", - (cis[i + 4] << 24) | - (cis[i + 3] << 16) | - (cis[i + 2] << 8) | cis[i + 1]); - break; - - case HNBU_RSSISMBXA2G: - ASSERT (sromrev == 3); - varbuf_append (&b, "rssismf2g=%d", cis[i + 1] & 0xf); - varbuf_append (&b, "rssismc2g=%d", (cis[i + 1] >> 4) & 0xf); - varbuf_append (&b, "rssisav2g=%d", cis[i + 2] & 0x7); - varbuf_append (&b, "bxa2g=%d", (cis[i + 2] >> 3) & 0x3); - break; - - case HNBU_RSSISMBXA5G: - ASSERT (sromrev == 3); - varbuf_append (&b, "rssismf5g=%d", cis[i + 1] & 0xf); - varbuf_append (&b, "rssismc5g=%d", (cis[i + 1] >> 4) & 0xf); - varbuf_append (&b, "rssisav5g=%d", cis[i + 2] & 0x7); - varbuf_append (&b, "bxa5g=%d", (cis[i + 2] >> 3) & 0x3); - break; - - case HNBU_TRI2G: - ASSERT (sromrev == 3); - varbuf_append (&b, "tri2g=%d", cis[i + 1]); - break; - - case HNBU_TRI5G: - ASSERT (sromrev == 3); - varbuf_append (&b, "tri5gl=%d", cis[i + 1]); - varbuf_append (&b, "tri5g=%d", cis[i + 2]); - varbuf_append (&b, "tri5gh=%d", cis[i + 3]); - break; - - case HNBU_RXPO2G: - ASSERT (sromrev == 3); - varbuf_append (&b, "rxpo2g=%d", cis[i + 1]); - break; - - case HNBU_RXPO5G: - ASSERT (sromrev == 3); - varbuf_append (&b, "rxpo5g=%d", cis[i + 1]); - break; - - case HNBU_BOARDNUM: - boardnum = (cis[i + 2] << 8) + cis[i + 1]; - break; - - case HNBU_MACADDR: - bcm_ether_ntoa ((struct ether_addr *) &cis[i + 1], eabuf); - break; - - case HNBU_BOARDTYPE: - varbuf_append (&b, "boardtype=0x%x", - (cis[i + 2] << 8) + cis[i + 1]); - break; - -#if defined(BCMCCISSR3) - case HNBU_SROM3SWRGN: - { - uint16 srom[35]; - uint8 srev = cis[i + 1 + 70]; - ASSERT (srev == 3); - /* make tuple value 16-bit aligned and parse it */ - bcopy (&cis[i + 1], srom, sizeof (srom)); - _initvars_srom_pci (srev, srom, SROM3_SWRGN_OFF, &b); - /* create extra variables */ - varbuf_append (&b, "vendid=0x%x", - (cis[i + 1 + 73] << 8) + cis[i + 1 + 72]); - varbuf_append (&b, "devid=0x%x", - (cis[i + 1 + 75] << 8) + cis[i + 1 + 74]); - varbuf_append (&b, "xtalfreq=%d", - (cis[i + 1 + 77] << 8) + cis[i + 1 + 76]); - /* 2.4G antenna gain is included in SROM */ - ag_init = TRUE; - /* Ethernet MAC address is included in SROM */ - eabuf[0] = 0; - boardnum = -1; - break; - } -#endif - } - break; - } - i += tlen; - } - while (tup != CISTPL_END); - } - - if (boardnum != -1) - { - varbuf_append (&b, "boardnum=%d", boardnum); - } - - if (eabuf[0]) - { - varbuf_append (&b, "macaddr=%s", eabuf); - } - - /* if there is no antenna gain field, set default */ - if (ag_init == FALSE) - { - varbuf_append (&b, "ag0=%d", 0xff); - } - - /* final nullbyte terminator */ - ASSERT (b.size >= 1); - *b.buf++ = '\0'; - varsize = (uint) (b.buf - base); - ASSERT (varsize < MAXSZ_NVRAM_VARS); - if (varsize < MAXSZ_NVRAM_VARS) - { - char *new_buf; - new_buf = (char *) MALLOC (osh, varsize); - ASSERT (new_buf); - if (new_buf) - { - bcopy (base, new_buf, varsize); - MFREE (osh, base, MAXSZ_NVRAM_VARS); - base = new_buf; - } - } - - *vars = base; - *count = varsize; - - return (0); -} - - -/* set PCMCIA sprom command register */ -static int -sprom_cmd_pcmcia (osl_t * osh, uint8 cmd) -{ - uint8 status = 0; - uint wait_cnt = 1000; - - /* write sprom command register */ - OSL_PCMCIA_WRITE_ATTR (osh, SROM_CS, &cmd, 1); - - /* wait status */ - while (wait_cnt--) - { - OSL_PCMCIA_READ_ATTR (osh, SROM_CS, &status, 1); - if (status & SROM_DONE) - return 0; - } - - return 1; -} - -/* read a word from the PCMCIA srom */ -static int -sprom_read_pcmcia (osl_t * osh, uint16 addr, uint16 * data) -{ - uint8 addr_l, addr_h, data_l, data_h; - - addr_l = (uint8) ((addr * 2) & 0xff); - addr_h = (uint8) (((addr * 2) >> 8) & 0xff); - - /* set address */ - OSL_PCMCIA_WRITE_ATTR (osh, SROM_ADDRH, &addr_h, 1); - OSL_PCMCIA_WRITE_ATTR (osh, SROM_ADDRL, &addr_l, 1); - - /* do read */ - if (sprom_cmd_pcmcia (osh, SROM_READ)) - return 1; - - /* read data */ - data_h = data_l = 0; - OSL_PCMCIA_READ_ATTR (osh, SROM_DATAH, &data_h, 1); - OSL_PCMCIA_READ_ATTR (osh, SROM_DATAL, &data_l, 1); - - *data = (data_h << 8) | data_l; - return 0; -} - -/* write a word to the PCMCIA srom */ -static int -sprom_write_pcmcia (osl_t * osh, uint16 addr, uint16 data) -{ - uint8 addr_l, addr_h, data_l, data_h; - - addr_l = (uint8) ((addr * 2) & 0xff); - addr_h = (uint8) (((addr * 2) >> 8) & 0xff); - data_l = (uint8) (data & 0xff); - data_h = (uint8) ((data >> 8) & 0xff); - - /* set address */ - OSL_PCMCIA_WRITE_ATTR (osh, SROM_ADDRH, &addr_h, 1); - OSL_PCMCIA_WRITE_ATTR (osh, SROM_ADDRL, &addr_l, 1); - - /* write data */ - OSL_PCMCIA_WRITE_ATTR (osh, SROM_DATAH, &data_h, 1); - OSL_PCMCIA_WRITE_ATTR (osh, SROM_DATAL, &data_l, 1); - - /* do write */ - return sprom_cmd_pcmcia (osh, SROM_WRITE); -} - -/* - * Read in and validate sprom. - * Return 0 on success, nonzero on error. - */ -static int -sprom_read_pci (osl_t * osh, uint16 * sprom, uint wordoff, uint16 * buf, - uint nwords, bool check_crc) -{ - int err = 0; - uint i; - - /* read the sprom */ - for (i = 0; i < nwords; i++) - { -#ifdef BCMQT - buf[i] = R_REG (osh, &sprom[wordoff + i]); -#endif - buf[i] = R_REG (osh, &sprom[wordoff + i]); - } - - if (check_crc) - { - if (buf[0] == 0xffff) - { - /* The hardware thinks that an srom that starts with 0xffff - * is blank, regardless of the rest of the content, so declare - * it bad. - */ - BS_ERROR (("%s: buf[0] = 0x%x, returning bad-crc\n", __FUNCTION__, - buf[0])); - return 1; - } - - /* fixup the endianness so crc8 will pass */ - htol16_buf (buf, nwords * 2); - if (hndcrc8 ((uint8 *) buf, nwords * 2, 0xff) != 0x9f) - err = 1; - /* now correct the endianness of the byte array */ - ltoh16_buf (buf, nwords * 2); - } - - return err; -} - -/* -* Create variable table from memory. -* Return 0 on success, nonzero on error. -*/ -static int -BCMINITFN (initvars_table) (osl_t * osh, char *start, char *end, char **vars, - uint * count) -{ - int c = (int) (end - start); - - /* do it only when there is more than just the null string */ - if (c > 1) - { - char *vp = MALLOC (osh, c); - ASSERT (vp); - if (!vp) - return BCME_NOMEM; - bcopy (start, vp, c); - *vars = vp; - *count = c; - } - else - { - *vars = NULL; - *count = 0; - } - - return 0; -} - -/* - * Find variables with <devpath> from flash. 'base' points to the beginning - * of the table upon enter and to the end of the table upon exit when success. - * Return 0 on success, nonzero on error. - */ -static int -initvars_flash (sb_t * sbh, osl_t * osh, char **base, uint len) -{ - char *vp = *base; - char *flash; - int err; - char *s; - uint l, dl, copy_len; - char devpath[SB_DEVPATH_BUFSZ]; - - /* allocate memory and read in flash */ - if (!(flash = MALLOC (osh, NVRAM_SPACE))) - return BCME_NOMEM; - if ((err = nvram_getall (flash, NVRAM_SPACE))) - goto exit; - - sb_devpath (sbh, devpath, sizeof (devpath)); - - /* grab vars with the <devpath> prefix in name */ - dl = strlen (devpath); - for (s = flash; s && *s; s += l + 1) - { - l = strlen (s); - - /* skip non-matching variable */ - if (strncmp (s, devpath, dl)) - continue; - - /* is there enough room to copy? */ - copy_len = l - dl + 1; - if (len < copy_len) - { - err = BCME_BUFTOOSHORT; - goto exit; - } - - /* no prefix, just the name=value */ - strncpy (vp, &s[dl], copy_len); - vp += copy_len; - len -= copy_len; - } - - /* add null string as terminator */ - if (len < 1) - { - err = BCME_BUFTOOSHORT; - goto exit; - } - *vp++ = '\0'; - - *base = vp; - -exit:MFREE (osh, flash, NVRAM_SPACE); - return err; -} - -#if !defined(BCMUSBDEV) && !defined(BCMSDIODEV) -/* - * Initialize nonvolatile variable table from flash. - * Return 0 on success, nonzero on error. - */ -static int -initvars_flash_sb (sb_t * sbh, char **vars, uint * count) -{ - osl_t *osh = sb_osh (sbh); - char *vp, *base; - int err; - - ASSERT (vars); - ASSERT (count); - - base = vp = MALLOC (osh, MAXSZ_NVRAM_VARS); - ASSERT (vp); - if (!vp) - return BCME_NOMEM; - - if ((err = initvars_flash (sbh, osh, &vp, MAXSZ_NVRAM_VARS)) == 0) - err = initvars_table (osh, base, vp, vars, count); - - MFREE (osh, base, MAXSZ_NVRAM_VARS); - - return err; -} -#endif /* !BCMUSBDEV && !BCMSDIODEV */ - -#ifdef WLTEST -char mfgsromvars[256]; -char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0" - "et0macaddr=00:11:22:33:44:52\0" - "et1macaddr=00:11:22:33:44:53\0" - "boardtype=0xffff\0" - "boardrev=0x10\0" "boardflags=8\0" "sromrev=2\0" "aa2g=3\0" "\0"; -#define MFGSROM_DEFVARSLEN 149 /* default srom len */ -#endif /* WL_TEST */ - -/* - * Initialize nonvolatile variable table from sprom. - * Return 0 on success, nonzero on error. - */ - -typedef struct -{ - const char *name; - uint32 revmask; - uint32 flags; - uint16 off; - uint16 mask; -} sromvar_t; - -#define SRFL_MORE 1 /* value continues as described by the next entry */ -#define SRFL_NOFFS 2 /* value bits can't be all one's */ -#define SRFL_PRHEX 4 /* value is in hexdecimal format */ -#define SRFL_PRSIGN 8 /* value is in signed decimal format */ -#define SRFL_CCODE 0x10 /* value is in country code format */ -#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ -#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */ - -/* Assumptions: - * - Ethernet address spins across 3 consective words - * - * Table rules: - * - Add multiple entries next to each other if a value spins across multiple words - * (even multiple fields in the same word) with each entry except the last having - * it's SRFL_MORE bit set. - * - Ethernet address entry does not follow above rule and must not have SRFL_MORE - * bit set. Its SRFL_ETHADDR bit implies it takes multiple words. - * - The last entry's name field must be NULL to indicate the end of the table. Other - * entries must have non-NULL name. - */ - -static const sromvar_t pci_sromvars[] = { - {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, - {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, - {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, - {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, - {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, - {"", 0, 0, SROM_BFL2, 0xffff}, - {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, - {"", 0, 0, SROM3_BFL2, 0xffff}, - {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff}, - {"", 0, 0, SROM4_BFL1, 0xffff}, - {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff}, - {"", 0, 0, SROM5_BFL1, 0xffff}, - {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff}, - {"", 0, 0, SROM8_BFL1, 0xffff}, - {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff}, - {"", 0, 0, SROM4_BFL3, 0xffff}, - {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff}, - {"", 0, 0, SROM5_BFL3, 0xffff}, - {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff}, - {"", 0, 0, SROM8_BFL3, 0xffff}, - {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, - {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, - {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, - {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, - {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, - {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff}, - {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, - {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, - {"regrev", 0x00000010, 0, SROM4_REGREV, 0xff}, - {"regrev", 0x000000e0, 0, SROM5_REGREV, 0xff}, - {"regrev", 0xffffff00, 0, SROM8_REGREV, 0xff}, - {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff}, - {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00}, - {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff}, - {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00}, - {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff}, - {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00}, - {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff}, - {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00}, - {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff}, - {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00}, - {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff}, - {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00}, - {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff}, - {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, - {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff}, - {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, - {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, - {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, - {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, - {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0xff}, - {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff}, - {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, - {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, - {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, - {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00}, - {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff}, - {"opo", 0x0000000c, 0, SROM_OPO, 0xff}, - {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0xff}, - {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, - {"aa2g", 0x000000f0, 0, SROM4_AA, 0xff}, - {"aa2g", 0xffffff00, 0, SROM8_AA, 0xff}, - {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, - {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, - {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00}, - {"ag0", 0x0000000e, 0, SROM_AG10, 0xff}, - {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, - {"ag0", 0x000000f0, 0, SROM4_AG10, 0xff}, - {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, - {"ag2", 0x000000f0, 0, SROM4_AG32, 0xff}, - {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, - {"ag0", 0xffffff00, 0, SROM8_AG10, 0xff}, - {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00}, - {"ag2", 0xffffff00, 0, SROM8_AG32, 0xff}, - {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00}, - {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, - {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, - {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, - {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, - {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, - {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, - {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, - {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, - {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, - {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, - {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, - {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, - {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff}, - {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, - {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, - {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, - {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, - {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, - {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, - {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, - {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, - {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, - {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00}, - {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff}, - {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00}, - {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff}, - {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, - {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, - {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, - {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, - {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800}, - {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700}, - {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0}, - {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f}, - {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, - {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, - {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, - {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, - {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800}, - {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700}, - {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0}, - {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f}, - {"tri2g", 0x00000008, 0, SROM_TRI52G, 0xff}, - {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, - {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0xff}, - {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, - {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0xff}, - {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00}, - {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0xff}, - {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00}, - {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff}, - {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, - {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff}, - {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, - {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, - {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, - {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, - {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, - {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, - {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, - {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0xff}, - {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, - {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff}, - {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, - {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0xff}, - {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, - {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff}, - {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, - {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0xff}, - {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, - {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff}, - {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, - {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0xff}, - {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, - {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff}, - {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, - {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, - {"cck2gpo", 0xffffff00, 0, SROM8_2G_CCKPO, 0xffff}, - {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, - {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, - {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, - {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, - {"ofdm2gpo", 0xffffff00, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, - {"ofdm5gpo", 0xffffff00, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, - {"ofdm5glpo", 0xffffff00, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, - {"ofdm5ghpo", 0xffffff00, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, - {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, - {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, - {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, - {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, - {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, - {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, - {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, - {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, - {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, - {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, - {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, - {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, - {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, - {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, - {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, - {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, - {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, - {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, - {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, - {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, - {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, - {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, - {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, - {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, - {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, - {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, - {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, - {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, - {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, - {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, - {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, - {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, - {"mcs2gpo0", 0xffffff00, 0, SROM8_2G_MCSPO, 0xffff}, - {"mcs2gpo1", 0xffffff00, 0, SROM8_2G_MCSPO + 1, 0xffff}, - {"mcs2gpo2", 0xffffff00, 0, SROM8_2G_MCSPO + 2, 0xffff}, - {"mcs2gpo3", 0xffffff00, 0, SROM8_2G_MCSPO + 3, 0xffff}, - {"mcs2gpo4", 0xffffff00, 0, SROM8_2G_MCSPO + 4, 0xffff}, - {"mcs2gpo5", 0xffffff00, 0, SROM8_2G_MCSPO + 5, 0xffff}, - {"mcs2gpo6", 0xffffff00, 0, SROM8_2G_MCSPO + 6, 0xffff}, - {"mcs2gpo7", 0xffffff00, 0, SROM8_2G_MCSPO + 7, 0xffff}, - {"mcs5gpo0", 0xffffff00, 0, SROM8_5G_MCSPO, 0xffff}, - {"mcs5gpo1", 0xffffff00, 0, SROM8_5G_MCSPO + 1, 0xffff}, - {"mcs5gpo2", 0xffffff00, 0, SROM8_5G_MCSPO + 2, 0xffff}, - {"mcs5gpo3", 0xffffff00, 0, SROM8_5G_MCSPO + 3, 0xffff}, - {"mcs5gpo4", 0xffffff00, 0, SROM8_5G_MCSPO + 4, 0xffff}, - {"mcs5gpo5", 0xffffff00, 0, SROM8_5G_MCSPO + 5, 0xffff}, - {"mcs5gpo6", 0xffffff00, 0, SROM8_5G_MCSPO + 6, 0xffff}, - {"mcs5gpo7", 0xffffff00, 0, SROM8_5G_MCSPO + 7, 0xffff}, - {"mcs5glpo0", 0xffffff00, 0, SROM8_5GL_MCSPO, 0xffff}, - {"mcs5glpo1", 0xffffff00, 0, SROM8_5GL_MCSPO + 1, 0xffff}, - {"mcs5glpo2", 0xffffff00, 0, SROM8_5GL_MCSPO + 2, 0xffff}, - {"mcs5glpo3", 0xffffff00, 0, SROM8_5GL_MCSPO + 3, 0xffff}, - {"mcs5glpo4", 0xffffff00, 0, SROM8_5GL_MCSPO + 4, 0xffff}, - {"mcs5glpo5", 0xffffff00, 0, SROM8_5GL_MCSPO + 5, 0xffff}, - {"mcs5glpo6", 0xffffff00, 0, SROM8_5GL_MCSPO + 6, 0xffff}, - {"mcs5glpo7", 0xffffff00, 0, SROM8_5GL_MCSPO + 7, 0xffff}, - {"mcs5ghpo0", 0xffffff00, 0, SROM8_5GH_MCSPO, 0xffff}, - {"mcs5ghpo1", 0xffffff00, 0, SROM8_5GH_MCSPO + 1, 0xffff}, - {"mcs5ghpo2", 0xffffff00, 0, SROM8_5GH_MCSPO + 2, 0xffff}, - {"mcs5ghpo3", 0xffffff00, 0, SROM8_5GH_MCSPO + 3, 0xffff}, - {"mcs5ghpo4", 0xffffff00, 0, SROM8_5GH_MCSPO + 4, 0xffff}, - {"mcs5ghpo5", 0xffffff00, 0, SROM8_5GH_MCSPO + 5, 0xffff}, - {"mcs5ghpo6", 0xffffff00, 0, SROM8_5GH_MCSPO + 6, 0xffff}, - {"mcs5ghpo7", 0xffffff00, 0, SROM8_5GH_MCSPO + 7, 0xffff}, - {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, - {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, - {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, - {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, - {"cddpo", 0xffffff00, 0, SROM8_CDDPO, 0xffff}, - {"stbcpo", 0xffffff00, 0, SROM8_STBCPO, 0xffff}, - {"bw40po", 0xffffff00, 0, SROM8_BW40PO, 0xffff}, - {"bwduppo", 0xffffff00, 0, SROM8_BWDUPPO, 0xffff}, - {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, - {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, - {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, - {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff}, - {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, - {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, - {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, - {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, - {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, - {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, - {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff}, - {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff}, - {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff}, - {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff}, - {NULL, 0, 0, 0, 0} -}; - -static const sromvar_t perpath_pci_sromvars[] = { - {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff}, - {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, - {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, - {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, - {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, - {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, - {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, - {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff}, - {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff}, - {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, - {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, - {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, - {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, - {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, - {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, - {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, - {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, - {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, - {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, - {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, - {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, - {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, - {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff}, - {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00}, - {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00}, - {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, - {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, - {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, - {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff}, - {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff}, - {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00}, - {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, - {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, - {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, - {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, - {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, - {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, - {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, - {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, - {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, - {NULL, 0, 0, 0, 0} -}; - -/* Parse SROM and create name=value pairs. 'srom' points to - * the SROM word array. 'off' specifies the offset of the - * first word 'srom' points to, which should be either 0 or - * SROM3_SWRG_OFF (full SROM or software region). - */ - -static uint -mask_shift (uint16 mask) -{ - uint i; - for (i = 0; i < (sizeof (mask) << 3); i++) - { - if (mask & (1 << i)) - return i; - } - ASSERT (mask); - return 0; -} - -static uint -mask_width (uint16 mask) -{ - int i; - for (i = (sizeof (mask) << 3) - 1; i >= 0; i--) - { - if (mask & (1 << i)) - return (uint) (i - mask_shift (mask) + 1); - } - ASSERT (mask); - return 0; -} - -#ifdef BCMDBG_ASSERT -static bool -mask_valid (uint16 mask) -{ - uint shift = mask_shift (mask); - uint width = mask_width (mask); - return mask == ((~0 << shift) & ~(~0 << (shift + width))); -} -#endif - -static void -_initvars_srom_pci (uint8 sromrev, uint16 * srom, uint off, varbuf_t * b) -{ - uint16 w; - uint32 val; - const sromvar_t *srv; - uint width; - uint flags; - uint32 sr = (1 << sromrev); - - varbuf_append (b, "sromrev=%d", sromrev); - - for (srv = pci_sromvars; srv->name != NULL; srv++) - { - const char *name; - - if ((srv->revmask & sr) == 0) - continue; - - if (srv->off < off) - continue; - - flags = srv->flags; - name = srv->name; - - if (flags & SRFL_ETHADDR) - { - char eabuf[ETHER_ADDR_STR_LEN]; - struct ether_addr ea; - - ea.octet[0] = (srom[srv->off - off] >> 8) & 0xff; - ea.octet[1] = srom[srv->off - off] & 0xff; - ea.octet[2] = (srom[srv->off + 1 - off] >> 8) & 0xff; - ea.octet[3] = srom[srv->off + 1 - off] & 0xff; - ea.octet[4] = (srom[srv->off + 2 - off] >> 8) & 0xff; - ea.octet[5] = srom[srv->off + 2 - off] & 0xff; - bcm_ether_ntoa (&ea, eabuf); - - varbuf_append (b, "%s=%s", name, eabuf); - } - else - { - ASSERT (mask_valid (srv->mask)); - ASSERT (mask_width (srv->mask)); - - w = srom[srv->off - off]; - val = (w & srv->mask) >> mask_shift (srv->mask); - width = mask_width (srv->mask); - - while (srv->flags & SRFL_MORE) - { - srv++; - ASSERT (srv->name); - - if (srv->off == 0 || srv->off < off) - continue; - - ASSERT (mask_valid (srv->mask)); - ASSERT (mask_width (srv->mask)); - - w = srom[srv->off - off]; - val += ((w & srv->mask) >> mask_shift (srv->mask)) << width; - width += mask_width (srv->mask); - } - - if ((flags & SRFL_NOFFS) && ((int) val == (1 << width) - 1)) - continue; - - if (flags & SRFL_CCODE) - { - if (val == 0) - varbuf_append (b, "ccode="); - else - varbuf_append (b, "ccode=%c%c", (val >> 8), (val & 0xff)); - } - /* LED Powersave duty cycle has to be scaled: - *(oncount >> 24) (offcount >> 8) - */ - else if (flags & SRFL_LEDDC) - { - uint32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */ - (((val & 0xff)) << 8); /* offcount */ - varbuf_append (b, "leddc=%d", w32); - } - else if (flags & SRFL_PRHEX) - varbuf_append (b, "%s=0x%x", name, val); - else if ((flags & SRFL_PRSIGN) && (val & (1 << (width - 1)))) - varbuf_append (b, "%s=%d", name, (int) (val | (~0 << width))); - else - varbuf_append (b, "%s=%u", name, val); - } - } - - if (sromrev >= 4) - { - /* Do per-path variables */ - uint p, pb, psz; - - if (sromrev >= 8) - { - pb = SROM8_PATH0; - psz = SROM8_PATH1 - SROM8_PATH0; - } - else - { - pb = SROM4_PATH0; - psz = SROM4_PATH1 - SROM4_PATH0; - } - - for (p = 0; p < MAX_PATH; p++) - { - for (srv = perpath_pci_sromvars; srv->name != NULL; srv++) - { - if ((srv->revmask & sr) == 0) - continue; - - if (pb + srv->off < off) - continue; - - w = srom[pb + srv->off - off]; - ASSERT (mask_valid (srv->mask)); - val = (w & srv->mask) >> mask_shift (srv->mask); - width = mask_width (srv->mask); - - /* Cheating: no per-path var is more than 1 word */ - - if ((srv->flags & SRFL_NOFFS) - && ((int) val == (1 << width) - 1)) - continue; - - if (srv->flags & SRFL_PRHEX) - varbuf_append (b, "%s%d=0x%x", srv->name, p, val); - else - varbuf_append (b, "%s%d=%d", srv->name, p, val); - } - pb += psz; - } - } -} - -static int -initvars_srom_pci (sb_t * sbh, void *curmap, char **vars, uint * count) -{ - uint16 *srom; - uint8 sromrev = 0; - uint32 sr; - varbuf_t b; - char *vp, *base = NULL; - osl_t *osh = sb_osh (sbh); - bool flash = FALSE; - char *value; - int err; - - /* - * Apply CRC over SROM content regardless SROM is present or not, - * and use variable <devpath>sromrev's existance in flash to decide - * if we should return an error when CRC fails or read SROM variables - * from flash. - */ - srom = MALLOC (osh, SROM_MAX); - ASSERT (srom); - if (!srom) - return -2; - - err = - sprom_read_pci (osh, (void *) ((int8 *) curmap + PCI_BAR0_SPROM_OFFSET), - 0, srom, SROM_WORDS, TRUE); - - if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) || - ((sbh->buscoretype == SB_PCIE) && (sbh->buscorerev >= 6))) - { - /* sromrev >= 4, read more */ - err = - sprom_read_pci (osh, - (void *) ((int8 *) curmap + PCI_BAR0_SPROM_OFFSET), 0, - srom, SROM4_WORDS, TRUE); - sromrev = srom[SROM4_CRCREV] & 0xff; - } - else if (err == 0) - { - /* srom is good and is rev < 4 */ - /* top word of sprom contains version and crc8 */ - sromrev = srom[SROM_CRCREV] & 0xff; - /* bcm4401 sroms misprogrammed */ - if (sromrev == 0x10) - sromrev = 1; - } - - if (err) - { -#ifdef WLTEST - uint32 val; - - BS_ERROR (("SROM Crc Error, so see if we could use a default\n")); - val = OSL_PCI_READ_CONFIG (osh, PCI_SPROM_CONTROL, sizeof (uint32)); - if (val & SPROM_OTPIN_USE) - { - BS_ERROR (("srom crc failed with OTP, use default vars....\n")); - vp = base = mfgsromvars; - if (sb_chip (sbh) == BCM4311_CHIP_ID) - { - const char *devid = "devid=0x4311"; - const size_t devid_strlen = strlen (devid); - BS_ERROR (("setting the devid to be 4311\n")); - bcopy (devid, vp, devid_strlen + 1); - vp += devid_strlen + 1; - } - bcopy (defaultsromvars, vp, MFGSROM_DEFVARSLEN); - vp += MFGSROM_DEFVARSLEN; - goto varsdone; - } - else - { -#endif /* WLTEST */ - BS_ERROR (("srom crc failed with SPROM....\n")); - if (!(value = sb_getdevpathvar (sbh, "sromrev"))) - { - err = -1; - goto errout; - } - sromrev = (uint8) simple_strtoul (value, NULL, 0); - flash = TRUE; -#ifdef WLTEST - } -#endif /* WLTEST */ - } - - /* Bitmask for the sromrev */ - sr = 1 << sromrev; - - /* srom version check - * Current valid versions: 1, 2, 3, 4, 5, 8 - */ - if ((sr & 0x13e) == 0) - { - err = -2; - goto errout; - } - - ASSERT (vars); - ASSERT (count); - - base = vp = MALLOC (osh, MAXSZ_NVRAM_VARS); - ASSERT (vp); - if (!vp) - { - err = -2; - goto errout; - } - - /* read variables from flash */ - if (flash) - { - if ((err = initvars_flash (sbh, osh, &vp, MAXSZ_NVRAM_VARS))) - goto errout; - goto varsdone; - } - - varbuf_init (&b, base, MAXSZ_NVRAM_VARS); - - /* parse SROM into name=value pairs. */ - _initvars_srom_pci (sromrev, srom, 0, &b); - - /* final nullbyte terminator */ - ASSERT (b.size >= 1); - vp = b.buf; - *vp++ = '\0'; - - ASSERT ((vp - base) <= MAXSZ_NVRAM_VARS); - -varsdone: - err = initvars_table (osh, base, vp, vars, count); - -errout: -#ifdef WLTEST - if (base && (base != mfgsromvars)) -#else - if (base) -#endif - MFREE (osh, base, MAXSZ_NVRAM_VARS); - - MFREE (osh, srom, SROM_MAX); - return err; -} - -/* - * Read the cis and call parsecis to initialize the vars. - * Return 0 on success, nonzero on error. - */ -static int -initvars_cis_pcmcia (sb_t * sbh, osl_t * osh, char **vars, uint * count) -{ - uint8 *cis = NULL; - int rc; - uint data_sz; - - data_sz = (sb_pcmciarev (sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE; - - if ((cis = MALLOC (osh, data_sz)) == NULL) - return (-2); - - if (sb_pcmciarev (sbh) == 1) - { - if (srom_read - (sbh, PCMCIA_BUS, (void *) NULL, osh, 0, data_sz, (uint16 *) cis)) - { - MFREE (osh, cis, data_sz); - return (-1); - } - /* fix up endianess for 16-bit data vs 8-bit parsing */ - htol16_buf ((uint16 *) cis, data_sz); - } - else - OSL_PCMCIA_READ_ATTR (osh, 0, cis, data_sz); - - rc = srom_parsecis (osh, &cis, 1, vars, count); - - MFREE (osh, cis, data_sz); - - return (rc); -} - - -static int -BCMINITFN (initvars_srom_sb) (sb_t * sbh, osl_t * osh, void *curmap, - char **vars, uint * varsz) -{ -#if defined(BCMSDIODEV) - /* CIS is read and supplied by the host */ - return BCME_OK; -#elif defined(BCMUSBDEV) - static bool srvars = FALSE; /* Use OTP/SPROM as global variables */ - - int sel = 0; /* where to read the srom. 0 - nowhere, 1 - otp, 2 - sprom */ - uint sz = 0; /* srom size in bytes */ - void *oh = NULL; - int rc = BCME_OK; - - /* Bail out if we've dealt with OTP/SPROM before! */ - if (srvars) - return 0; - -#if defined(BCM4328) - if (sbh->chip == BCM4328_CHIP_ID) - { - /* Access the SPROM if it is present */ - if ((sz = srom_size (sbh, osh)) != 0) - { - sz <<= 1; - sel = 2; - } - } -#endif -#if defined(BCM4325) - if (sbh->chip == BCM4325_CHIP_ID) - { - uint32 cst = sbh->chipst & CST4325_SPROM_OTP_SEL_MASK; - - /* Access OTP if it is present, powered on, and programmed */ - if ((oh = otp_init (sbh)) != NULL && (otp_status (oh) & OTPS_GUP_SW)) - { - sz = otp_size (oh); - sel = 1; - } - /* Access the SPROM if it is present and allow to be accessed */ - else if ((cst == CST4325_OTP_PWRDN || cst == CST4325_SPROM_SEL) && - (sz = srom_size (sbh, osh)) != 0) - { - sz <<= 1; - sel = 2; - } - } -#endif /* BCM4325 */ - - /* Read CIS in OTP/SPROM */ - if (sel != 0) - { - uint16 *srom; - uint8 *body = NULL; - - ASSERT (sz); - - /* Allocate memory */ - if ((srom = (uint16 *) MALLOC (osh, sz)) == NULL) - return BCME_NOMEM; - - /* Read CIS */ - switch (sel) - { - case 1: - rc = otp_read_region (oh, OTP_SW_RGN, srom, sz); - body = (uint8 *) srom; - break; - case 2: - rc = srom_read (sbh, SB_BUS, curmap, osh, 0, sz, srom); - /* sprom has 8 byte h/w header */ - body = (uint8 *) srom + SBSDIO_SPROM_CIS_OFFSET; - break; - default: - /* impossible to come here */ - ASSERT (0); - break; - } - - /* Parse CIS */ - if (rc == BCME_OK) - { - uint i, tpls = 0xffffffff; - /* # sdiod fns + common + extra */ - uint8 *cis[SBSDIO_NUM_FUNCTION + 2]; - uint ciss = 0; - - /* each word is in host endian */ - htol16_buf ((uint8 *) srom, sz); - - ASSERT (body); - - /* count cis tuple chains */ - for (i = 0; i < sz && ciss < ARRAYSIZE (cis) && tpls != 0; i++) - { - cis[ciss++] = &body[i]; - for (tpls = 0; i < sz - 1; tpls++) - { - if (body[i++] == CISTPL_END) - break; - i += body[i] + 1; - } - } - - /* call parser routine only when there are tuple chains */ - if (ciss > 1) - rc = srom_parsecis (osh, cis, ciss, vars, varsz); - } - - /* Clean up */ - MFREE (osh, srom, sz); - - /* Make SROM variables global */ - if (rc == BCME_OK) - { - rc = nvram_append ((void *) sbh, *vars, *varsz); - srvars = TRUE; - - /* Tell the caller there is no individual SROM variables */ - *vars = NULL; - *varsz = 0; - } - } - - return rc; -#else /* !BCMUSBDEV && !BCMSDIODEV */ - /* Search flash nvram section for srom variables */ - return initvars_flash_sb (sbh, vars, varsz); -#endif /* !BCMUSBDEV && !BCMSDIODEV */ -} - -#ifdef BCMUSBDEV -/* Return sprom size in 16-bit words */ -static uint -srom_size (sb_t * sbh, osl_t * osh) -{ - uint size = 0; - if (SPROMBUS == PCMCIA_BUS) - { - uint32 origidx; - sdpcmd_regs_t *pcmregs; - bool wasup; - - origidx = sb_coreidx (sbh); - pcmregs = sb_setcore (sbh, SB_PCMCIA, 0); - ASSERT (pcmregs); - - if (!(wasup = sb_iscoreup (sbh))) - sb_core_reset (sbh, 0, 0); - - /* not worry about earlier core revs */ - if (sb_corerev (sbh) < 8) - goto done; - - /* SPROM is accessible only in PCMCIA mode unless there is SDIO clock */ - if (!(R_REG (osh, &pcmregs->corestatus) & CS_PCMCIAMODE)) - goto done; - - switch (SB_PCMCIA_READ (osh, pcmregs, SROM_INFO) & SRI_SZ_MASK) - { - case 1: - size = 256; /* SROM_INFO == 1 means 4kbit */ - break; - case 2: - size = 1024; /* SROM_INFO == 2 means 16kbit */ - break; - default: - break; - } - - done: - if (!wasup) - sb_core_disable (sbh, 0); - - sb_setcoreidx (sbh, origidx); - } - return size; -} -#endif /* def BCMUSBDEV */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/cfe_env.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/cfe_env.c deleted file mode 100644 index 22ef0c55b2..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/cfe_env.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * NVRAM variable manipulation (Linux kernel half) - * - * Copyright 2001-2003, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <asm/io.h> -#include <asm/uaccess.h> - -#include <typedefs.h> -#include <osl.h> -#include <bcmendian.h> - -#define NVRAM_SIZE (0x1ff0) -static char _nvdata[NVRAM_SIZE] __initdata; -static char _valuestr[256] __initdata; - -/* - * TLV types. These codes are used in the "type-length-value" - * encoding of the items stored in the NVRAM device (flash or EEPROM) - * - * The layout of the flash/nvram is as follows: - * - * <type> <length> <data ...> <type> <length> <data ...> <type_end> - * - * The type code of "ENV_TLV_TYPE_END" marks the end of the list. - * The "length" field marks the length of the data section, not - * including the type and length fields. - * - * Environment variables are stored as follows: - * - * <type_env> <length> <flags> <name> = <value> - * - * If bit 0 (low bit) is set, the length is an 8-bit value. - * If bit 0 (low bit) is clear, the length is a 16-bit value - * - * Bit 7 set indicates "user" TLVs. In this case, bit 0 still - * indicates the size of the length field. - * - * Flags are from the constants below: - * - */ -#define ENV_LENGTH_16BITS 0x00 /* for low bit */ -#define ENV_LENGTH_8BITS 0x01 - -#define ENV_TYPE_USER 0x80 - -#define ENV_CODE_SYS(n,l) (((n)<<1)|(l)) -#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER) - -/* - * The actual TLV types we support - */ - -#define ENV_TLV_TYPE_END 0x00 -#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS) - -/* - * Environment variable flags - */ - -#define ENV_FLG_NORMAL 0x00 /* normal read/write */ -#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */ -#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */ - -#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */ -#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */ - - -/* ********************************************************************* - * _nvram_read(buffer,offset,length) - * - * Read data from the NVRAM device - * - * Input parameters: - * buffer - destination buffer - * offset - offset of data to read - * length - number of bytes to read - * - * Return value: - * number of bytes read, or <0 if error occured - ********************************************************************* */ -static int -_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length) -{ - int i; - if (offset > NVRAM_SIZE) - return -1; - - for ( i = 0; i < length; i++) { - buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i]; - } - return length; -} - - -static char* -_strnchr(const char *dest,int c,size_t cnt) -{ - while (*dest && (cnt > 0)) { - if (*dest == c) return (char *) dest; - dest++; - cnt--; - } - return NULL; -} - - - -/* - * Core support API: Externally visible. - */ - -/* - * Get the value of an NVRAM variable - * @param name name of variable to get - * @return value of variable or NULL if undefined - */ - -char* -cfe_env_get(unsigned char *nv_buf, char* name) -{ - int size; - unsigned char *buffer; - unsigned char *ptr; - unsigned char *envval; - unsigned int reclen; - unsigned int rectype; - int offset; - int flg; - - size = NVRAM_SIZE; - buffer = &_nvdata[0]; - - ptr = buffer; - offset = 0; - - /* Read the record type and length */ - if (_nvram_read(nv_buf, ptr,offset,1) != 1) { - goto error; - } - - while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) { - - /* Adjust pointer for TLV type */ - rectype = *(ptr); - offset++; - size--; - - /* - * Read the length. It can be either 1 or 2 bytes - * depending on the code - */ - if (rectype & ENV_LENGTH_8BITS) { - /* Read the record type and length - 8 bits */ - if (_nvram_read(nv_buf, ptr,offset,1) != 1) { - goto error; - } - reclen = *(ptr); - size--; - offset++; - } - else { - /* Read the record type and length - 16 bits, MSB first */ - if (_nvram_read(nv_buf, ptr,offset,2) != 2) { - goto error; - } - reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1); - size -= 2; - offset += 2; - } - - if (reclen > size) - break; /* should not happen, bad NVRAM */ - - switch (rectype) { - case ENV_TLV_TYPE_ENV: - /* Read the TLV data */ - if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen) - goto error; - flg = *ptr++; - envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1)); - if (envval) { - *envval++ = '\0'; - memcpy(_valuestr,envval,(reclen-1)-(envval-ptr)); - _valuestr[(reclen-1)-(envval-ptr)] = '\0'; -#if 0 - printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr); -#endif - if(!strcmp(ptr, name)){ - return _valuestr; - } - if((strlen(ptr) > 1) && !strcmp(&ptr[1], name)) - return _valuestr; - } - break; - - default: - /* Unknown TLV type, skip it. */ - break; - } - - /* - * Advance to next TLV - */ - - size -= (int)reclen; - offset += reclen; - - /* Read the next record type */ - ptr = buffer; - if (_nvram_read(nv_buf, ptr,offset,1) != 1) - goto error; - } - -error: - return NULL; - -} - diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/export.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/export.c deleted file mode 100644 index 35a578aa67..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/export.c +++ /dev/null @@ -1,75 +0,0 @@ -#include <linux/module.h> - -#define _export(n) \ - void n(void); \ - EXPORT_SYMBOL(n); - -_export(bcm947xx_sbh) - -_export(sb_alp_clock) -_export(sb_attach) -_export(sb_kattach) -_export(sb_backplane64) -_export(sb_boardtype) -_export(sb_boardvendor) -_export(sb_btcgpiowar) -_export(sb_bus) -_export(sb_chip) -_export(sb_chiprev) -_export(sb_chipcrev) -_export(sb_chippkg) -_export(sb_clkctl_clk) -_export(sb_clkctl_fast_pwrup_delay) -_export(sb_clkctl_init) -_export(sb_clkctl_xtal) -_export(sb_core_disable) -_export(sb_core_reset) -_export(sb_core_tofixup) -_export(sb_coreflags) -_export(sb_coreflags_wo) -_export(sb_coreflagshi) -_export(sb_coreidx) -_export(sb_coreregs) -_export(sb_corerev) -_export(sb_coreunit) -_export(sb_detach) -_export(sb_deviceremoved) -_export(sb_gpiosetcore) -_export(sb_gpiocontrol) -_export(sb_gpiointmask) -_export(sb_gpiointpolarity) -_export(sb_gpioled) -_export(sb_gpioin) -_export(sb_gpioout) -_export(sb_gpioouten) -_export(sb_gpiopull) -_export(sb_gpiotimerval) -_export(sb_irq) -_export(sb_iscoreup) -_export(sb_pci_setup) -_export(sb_pci_sleep) -_export(sb_pci_down) -_export(sb_pci_up) -_export(sb_pcirev) -_export(sb_pcmcia_init) -_export(sb_pcmciarev) -_export(sb_pmu_paref_ldo_enable) -_export(sb_pmu_rcal) -_export(sb_pmu_set_ldo_voltage) -_export(sb_deregister_intr_callback) -_export(sb_register_intr_callback) -_export(sb_setcore) -_export(sb_setcoreidx) -_export(sb_war16165) -_export(sb_war42780_clkreq) -_export(sb_osh) - -_export(getvar) -_export(getintvar) - -_export(nvram_get) -_export(nvram_getall) - -_export(srom_read) -_export(srom_write) - diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/Makefile b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/Makefile deleted file mode 100644 index 7e03a34980..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Makefile for the BCM947xx specific kernel interface routines -# under Linux. -# -EXTRA_CFLAGS += -fno-delayed-branch -USE_STANDARD_AS_RULE := true - -O_TARGET := brcm.o - -obj-y := int-handler.o irq.o - -include $(TOPDIR)/Rules.make diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/int-handler.S b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/int-handler.S deleted file mode 100644 index b4e93618c1..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/int-handler.S +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Generic interrupt handler for Broadcom MIPS boards - * - * Copyright 2004, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> - -#include <asm/asm.h> -#include <asm/mipsregs.h> -#include <asm/regdef.h> -#include <asm/stackframe.h> - -/* - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Combined hardware interrupt (hw0) - * 3 Hardware - * 4 Hardware - * 5 Hardware - * 6 Hardware - * 7 R4k timer - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(brcmIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - .set noreorder - - jal brcm_irq_dispatch - move a0, sp - - j ret_from_irq - nop - - END(brcmIRQ) diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/irq.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/irq.c deleted file mode 100644 index cf680a73de..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/generic/irq.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Generic interrupt control functions for Broadcom MIPS boards - * - * Copyright 2004, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/irq.h> - -#include <asm/irq.h> -#include <asm/mipsregs.h> -#include <asm/gdb-stub.h> - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -extern asmlinkage void brcmIRQ(void); -extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs); - -void -brcm_irq_dispatch(struct pt_regs *regs) -{ - u32 cause; - - cause = read_c0_cause() & - read_c0_status() & - CAUSEF_IP; - -#ifdef CONFIG_KERNPROF - change_c0_status(cause | 1, 1); -#else - clear_c0_status(cause); -#endif - - if (cause & CAUSEF_IP7) - do_IRQ(7, regs); - if (cause & CAUSEF_IP2) - do_IRQ(2, regs); - if (cause & CAUSEF_IP3) - do_IRQ(3, regs); - if (cause & CAUSEF_IP4) - do_IRQ(4, regs); - if (cause & CAUSEF_IP5) - do_IRQ(5, regs); - if (cause & CAUSEF_IP6) - do_IRQ(6, regs); -} - -static void -enable_brcm_irq(unsigned int irq) -{ - if (irq < 8) - set_c0_status(1 << (irq + 8)); - else - set_c0_status(IE_IRQ0); -} - -static void -disable_brcm_irq(unsigned int irq) -{ - if (irq < 8) - clear_c0_status(1 << (irq + 8)); - else - clear_c0_status(IE_IRQ0); -} - -static void -ack_brcm_irq(unsigned int irq) -{ - /* Already done in brcm_irq_dispatch */ -} - -static unsigned int -startup_brcm_irq(unsigned int irq) -{ - enable_brcm_irq(irq); - - return 0; /* never anything pending */ -} - -static void -end_brcm_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_brcm_irq(irq); -} - -static struct hw_interrupt_type brcm_irq_type = { - typename: "MIPS", - startup: startup_brcm_irq, - shutdown: disable_brcm_irq, - enable: enable_brcm_irq, - disable: disable_brcm_irq, - ack: ack_brcm_irq, - end: end_brcm_irq, - NULL -}; - -void __init -init_IRQ(void) -{ - int i; - - for (i = 0; i < NR_IRQS; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].handler = &brcm_irq_type; - } - - set_except_vector(0, brcmIRQ); - change_c0_status(ST0_IM, ALLINTS); - -#ifdef CONFIG_REMOTE_DEBUG - printk("Breaking into debugger...\n"); - set_debug_traps(); - breakpoint(); -#endif -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/gpio.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/gpio.c deleted file mode 100644 index a0aba5d2a7..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/gpio.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * GPIO char driver - * - * Copyright 2005, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/fs.h> -#include <linux/miscdevice.h> -#include <asm/uaccess.h> - -#include <typedefs.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmdevs.h> - -static sb_t *gpio_sbh; -static int gpio_major; -static devfs_handle_t gpio_dir; -static struct { - char *name; - devfs_handle_t handle; -} gpio_file[] = { - { "in", NULL }, - { "out", NULL }, - { "outen", NULL }, - { "control", NULL } -}; - -static int -gpio_open(struct inode *inode, struct file * file) -{ - if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file)) - return -ENODEV; - - MOD_INC_USE_COUNT; - return 0; -} - -static int -gpio_release(struct inode *inode, struct file * file) -{ - MOD_DEC_USE_COUNT; - return 0; -} - -static ssize_t -gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos) -{ - u32 val; - - switch (MINOR(file->f_dentry->d_inode->i_rdev)) { - case 0: - val = sb_gpioin(gpio_sbh); - break; - case 1: - val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY); - break; - case 2: - val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY); - break; - case 3: - val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY); - break; - default: - return -ENODEV; - } - - if (put_user(val, (u32 *) buf)) - return -EFAULT; - - return sizeof(val); -} - -static ssize_t -gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos) -{ - u32 val; - - if (get_user(val, (u32 *) buf)) - return -EFAULT; - - switch (MINOR(file->f_dentry->d_inode->i_rdev)) { - case 0: - return -EACCES; - case 1: - sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY); - break; - case 2: - sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY); - break; - case 3: - sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY); - break; - default: - return -ENODEV; - } - - return sizeof(val); -} - -static struct file_operations gpio_fops = { - owner: THIS_MODULE, - open: gpio_open, - release: gpio_release, - read: gpio_read, - write: gpio_write, -}; - -static int __init -gpio_init(void) -{ - int i; - - if (!(gpio_sbh = sb_kattach(SB_OSH))) - return -ENODEV; - - sb_gpiosetcore(gpio_sbh); - - if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0) - return gpio_major; - - gpio_dir = devfs_mk_dir(NULL, "gpio", NULL); - - for (i = 0; i < ARRAYSIZE(gpio_file); i++) { - gpio_file[i].handle = devfs_register(gpio_dir, - gpio_file[i].name, - DEVFS_FL_DEFAULT, gpio_major, i, - S_IFCHR | S_IRUGO | S_IWUGO, - &gpio_fops, NULL); - } - - return 0; -} - -static void __exit -gpio_exit(void) -{ - int i; - - for (i = 0; i < ARRAYSIZE(gpio_file); i++) - devfs_unregister(gpio_file[i].handle); - devfs_unregister(gpio_dir); - devfs_unregister_chrdev(gpio_major, "gpio"); - sb_detach(gpio_sbh); -} - -module_init(gpio_init); -module_exit(gpio_exit); diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndchipc.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndchipc.c deleted file mode 100644 index 4e58bf18ab..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndchipc.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * BCM47XX support code for some chipcommon facilities (uart, jtagm) - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <typedefs.h> -#include <bcmdefs.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmdevs.h> -#include <bcmnvram.h> -#include <sbconfig.h> -#include <sbchipc.h> -#include <sbextif.h> -#include <hndchipc.h> -#include <hndcpu.h> - -/* debug/trace */ -#define CC_ERROR(args) - -#ifdef BCMDBG -#define CC_MSG(args) printf args -#else -#define CC_MSG(args) -#endif /* BCMDBG */ - -/* interested chipcommon interrupt source - * - GPIO - * - EXTIF - * - ECI - * - PMU - * - UART - */ -#define MAX_CC_INT_SOURCE 5 - -/* chipc secondary isr info */ -typedef struct { - uint intmask; /* int mask */ - cc_isr_fn isr; /* secondary isr handler */ - void *cbdata; /* pointer to private data */ -} cc_isr_info_t; - -static cc_isr_info_t cc_isr_desc[MAX_CC_INT_SOURCE]; - -/* chip common intmask */ -static uint32 cc_intmask = 0; - -static bool BCMINITFN(serial_exists) (osl_t * osh, uint8 * regs) { - uint8 save_mcr, status1; - - save_mcr = R_REG(osh, ®s[UART_MCR]); - W_REG(osh, ®s[UART_MCR], UART_MCR_LOOP | 0x0a); - status1 = R_REG(osh, ®s[UART_MSR]) & 0xf0; - W_REG(osh, ®s[UART_MCR], save_mcr); - - return (status1 == 0x90); -} - -static void __init sb_extif_serial_init(sb_t * sbh, void *regs, - sb_serial_init_fn add) -{ - osl_t *osh = sb_osh(sbh); - extifregs_t *eir = (extifregs_t *) regs; - sbconfig_t *sb; - ulong base; - uint irq; - int i, n; - - /* Determine external UART register base */ - sb = (sbconfig_t *) ((ulong) eir + SBCONFIGOFF); - base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1))); - - /* Determine IRQ */ - irq = sb_irq(sbh); - - /* Disable GPIO interrupt initially */ - W_REG(osh, &eir->gpiointpolarity, 0); - W_REG(osh, &eir->gpiointmask, 0); - - /* Search for external UARTs */ - n = 2; - for (i = 0; i < 2; i++) { - regs = (void *)REG_MAP(base + (i * 8), 8); - if (serial_exists(osh, regs)) { - /* Set GPIO 1 to be the external UART IRQ */ - W_REG(osh, &eir->gpiointmask, 2); - /* XXXDetermine external UART clock */ - if (add) - add(regs, irq, 13500000, 0); - } - } - - /* Add internal UART if enabled */ - if (R_REG(osh, &eir->corecontrol) & CC_UE) - if (add) - add((void *)&eir->uartdata, irq, sb_clock(sbh), 2); -} - -/* - * Initializes UART access. The callback function will be called once - * per found UART. - */ -void BCMINITFN(sb_serial_init) (sb_t * sbh, sb_serial_init_fn add) { - osl_t *osh; - void *regs; - chipcregs_t *cc; - uint32 rev, cap, pll, baud_base, div; - uint irq; - int i, n; - - osh = sb_osh(sbh); - - regs = sb_setcore(sbh, SB_EXTIF, 0); - if (regs) { - sb_extif_serial_init(sbh, regs, add); - return; - } - - cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0); - ASSERT(cc); - - /* Determine core revision and capabilities */ - rev = sbh->ccrev; - cap = sbh->cccaps; - pll = cap & CC_CAP_PLL_MASK; - - /* Determine IRQ */ - irq = sb_irq(sbh); - - if (pll == PLL_TYPE1) { - /* PLL clock */ - baud_base = sb_clock_rate(pll, - R_REG(osh, &cc->clockcontrol_n), - R_REG(osh, &cc->clockcontrol_m2)); - div = 1; - } else { - /* 5354 chip common uart uses a constant clock - * frequency of 25MHz */ - if (sb_corerev(sbh) == 20) { - /* Set the override bit so we don't divide it */ - W_REG(osh, &cc->corecontrol, CC_UARTCLKO); - baud_base = 25000000; - } else if (rev >= 11 && rev != 15) { - /* Fixed ALP clock */ - baud_base = sb_alp_clock(sbh); - div = 1; - /* Turn off UART clock before switching clock source */ - if (rev >= 21) - AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN); - /* Set the override bit so we don't divide it */ - OR_REG(osh, &cc->corecontrol, CC_UARTCLKO); - if (rev >= 21) - OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN); - } else if (rev >= 3) { - /* Internal backplane clock */ - baud_base = sb_clock(sbh); - div = 2; /* Minimum divisor */ - W_REG(osh, &cc->clkdiv, - ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div)); - } else { - /* Fixed internal backplane clock */ - baud_base = 88000000; - div = 48; - } - - /* Clock source depends on strapping if UartClkOverride is unset */ - if ((rev > 0) - && ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) { - if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) { - /* Internal divided backplane clock */ - baud_base /= div; - } else { - /* Assume external clock of 1.8432 MHz */ - baud_base = 1843200; - } - } - } - - /* Add internal UARTs */ - n = cap & CC_CAP_UARTS_MASK; - for (i = 0; i < n; i++) { - /* Register offset changed after revision 0 */ - if (rev) - regs = (void *)((ulong) & cc->uart0data + (i * 256)); - else - regs = (void *)((ulong) & cc->uart0data + (i * 8)); - - if (add) - add(regs, irq, baud_base, 0); - } -} - -#if 0 -/* - * Initialize jtag master and return handle for - * jtag_rwreg. Returns NULL on failure. - */ -void *sb_jtagm_init(sb_t * sbh, uint clkd, bool exttap) -{ - void *regs; - - if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) { - chipcregs_t *cc = (chipcregs_t *) regs; - uint32 tmp; - - /* - * Determine jtagm availability from - * core revision and capabilities. - */ - - /* - * Corerev 10 has jtagm, but the only chip - * with it does not have a mips, and - * the layout of the jtagcmd register is - * different. We'll only accept >= 11. - */ - if (sbh->ccrev < 11) - return (NULL); - - if ((sbh->cccaps & CC_CAP_JTAGP) == 0) - return (NULL); - - /* Set clock divider if requested */ - if (clkd != 0) { - tmp = R_REG(osh, &cc->clkdiv); - tmp = - (tmp & ~CLKD_JTAG) | ((clkd << CLKD_JTAG_SHIFT) & - CLKD_JTAG); - W_REG(osh, &cc->clkdiv, tmp); - } - - /* Enable jtagm */ - tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0); - W_REG(osh, &cc->jtagctrl, tmp); - } - - return (regs); -} - -void sb_jtagm_disable(osl_t * osh, void *h) -{ - chipcregs_t *cc = (chipcregs_t *) h; - - W_REG(osh, &cc->jtagctrl, R_REG(osh, &cc->jtagctrl) & ~JCTRL_EN); -} - -/* - * Read/write a jtag register. Assumes a target with - * 8 bit IR and 32 bit DR. - */ -#define IRWIDTH 8 /* Default Instruction Register width */ -#define DRWIDTH 32 /* Default Data Register width */ - -uint32 jtag_rwreg(osl_t * osh, void *h, uint32 ir, uint32 dr) -{ - chipcregs_t *cc = (chipcregs_t *) h; - uint32 tmp; - - W_REG(osh, &cc->jtagir, ir); - W_REG(osh, &cc->jtagdr, dr); - tmp = JCMD_START | JCMD_ACC_IRDR | - ((IRWIDTH - 1) << JCMD_IRW_SHIFT) | (DRWIDTH - 1); - W_REG(osh, &cc->jtagcmd, tmp); - while (((tmp = R_REG(osh, &cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) { - /* OSL_DELAY(1); */ - } - - tmp = R_REG(osh, &cc->jtagdr); - return (tmp); -} -#endif - -/* - * Interface to register chipc secondary isr - */ -bool -BCMINITFN(sb_cc_register_isr) (sb_t * sbh, cc_isr_fn isr, uint32 ccintmask, - void *cbdata) { - bool done = FALSE; - chipcregs_t *regs; - uint origidx; - uint i; - - /* Save the current core index */ - origidx = sb_coreidx(sbh); - regs = sb_setcore(sbh, SB_CC, 0); - ASSERT(regs); - - for (i = 0; i < MAX_CC_INT_SOURCE; i++) { - if (cc_isr_desc[i].isr == NULL) { - cc_isr_desc[i].isr = isr; - cc_isr_desc[i].cbdata = cbdata; - cc_isr_desc[i].intmask = ccintmask; - done = TRUE; - break; - } - } - - if (done) { - cc_intmask = R_REG(sb_osh(sbh), ®s->intmask); - cc_intmask |= ccintmask; - W_REG(sb_osh(sbh), ®s->intmask, cc_intmask); - } - - /* restore original coreidx */ - sb_setcoreidx(sbh, origidx); - return done; -} - -/* - * chipc primary interrupt handler - */ -void sb_cc_isr(sb_t * sbh, chipcregs_t * regs) -{ - uint32 ccintstatus; - uint32 intstatus; - uint32 i; - - /* prior to rev 21 chipc interrupt means uart and gpio */ - if (sbh->ccrev >= 21) - ccintstatus = R_REG(sb_osh(sbh), ®s->intstatus) & cc_intmask; - else - ccintstatus = (CI_UART | CI_GPIO); - - for (i = 0; i < MAX_CC_INT_SOURCE; i++) { - if ((cc_isr_desc[i].isr != NULL) && - (intstatus = (cc_isr_desc[i].intmask & ccintstatus))) { - (cc_isr_desc[i].isr) (cc_isr_desc[i].cbdata, intstatus); - } - } -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndpmu.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndpmu.c deleted file mode 100644 index 0e95f2cfe9..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/hndpmu.c +++ /dev/null @@ -1,1256 +0,0 @@ -/* - * Misc utility routines for accessing PMU corerev specific features - * of the SiliconBackplane-based Broadcom chips. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#include <typedefs.h> -#include <bcmdefs.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmdevs.h> -#include <sbconfig.h> -#include <sbchipc.h> -#include <hndpmu.h> - -/* debug/trace */ -#define PMU_ERROR(args) - -#ifdef BCMDBG -#define PMU_MSG(args) printf args -#else -#define PMU_MSG(args) -#endif /* BCMDBG */ - -/* PMU & control */ -/* PMU rev 0 pll control for BCM4328 and BCM5354 */ -static void sb_pmu0_pllinit0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc, - uint32 xtal); -static uint32 sb_pmu0_alpclk0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc); -static uint32 sb_pmu0_cpuclk0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc); -/* PMU rev 0 pll control for BCM4325 BCM4329 */ -static void sb_pmu1_pllinit0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc, - uint32 xtal); -static uint32 sb_pmu1_cpuclk0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc); -static uint32 sb_pmu1_alpclk0 (sb_t * sbh, osl_t * osh, chipcregs_t * cc); - -/* Setup switcher voltage */ -void -BCMINITFN (sb_pmu_set_switcher_voltage) (sb_t * sbh, osl_t * osh, - uint8 bb_voltage, uint8 rf_voltage) -{ - chipcregs_t *cc; - uint origidx; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - W_REG (osh, &cc->regcontrol_addr, 0x01); - W_REG (osh, &cc->regcontrol_data, (uint32) (bb_voltage & 0x1f) << 22); - - W_REG (osh, &cc->regcontrol_addr, 0x00); - W_REG (osh, &cc->regcontrol_data, (uint32) (rf_voltage & 0x1f) << 14); - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} - -void -sb_pmu_set_ldo_voltage (sb_t * sbh, osl_t * osh, uint8 ldo, uint8 voltage) -{ - uint8 sr_cntl_shift, rc_shift, shift, mask; - uint32 addr; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - case BCM5354_CHIP_ID: - switch (ldo) - { - case SET_LDO_VOLTAGE_LDO1: - addr = 2; - sr_cntl_shift = 8; - rc_shift = 17; - mask = 0xf; - break; - case SET_LDO_VOLTAGE_LDO2: - addr = 3; - sr_cntl_shift = 0; - rc_shift = 1; - mask = 0xf; - break; - case SET_LDO_VOLTAGE_LDO3: - addr = 3; - sr_cntl_shift = 0; - rc_shift = 9; - mask = 0xf; - break; - case SET_LDO_VOLTAGE_PAREF: - addr = 3; - sr_cntl_shift = 0; - rc_shift = 17; - mask = 0x3f; - break; - default: - ASSERT (FALSE); - return; - } - break; - case BCM4312_CHIP_ID: - switch (ldo) - { - case SET_LDO_VOLTAGE_PAREF: - addr = 0; - sr_cntl_shift = 0; - rc_shift = 21; - mask = 0x3f; - break; - default: - ASSERT (FALSE); - return; - } - break; - default: - ASSERT (FALSE); - return; - } - - shift = sr_cntl_shift + rc_shift; - - sb_corereg (sbh, SB_CC_IDX, OFFSETOF (chipcregs_t, regcontrol_addr), - ~0, addr); - sb_corereg (sbh, SB_CC_IDX, OFFSETOF (chipcregs_t, regcontrol_data), - mask << shift, (voltage & mask) << shift); -} - -void -sb_pmu_paref_ldo_enable (sb_t * sbh, osl_t * osh, bool enable) -{ - uint ldo = 0; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - ldo = RES4328_PA_REF_LDO; - break; - case BCM5354_CHIP_ID: - ldo = RES5354_PA_REF_LDO; - break; - case BCM4312_CHIP_ID: - ldo = RES4312_PA_REF_LDO; - break; - default: - return; - } - - sb_corereg (sbh, SB_CC_IDX, OFFSETOF (chipcregs_t, min_res_mask), - PMURES_BIT (ldo), enable ? PMURES_BIT (ldo) : 0); -} - -uint16 BCMINITFN (sb_pmu_fast_pwrup_delay) (sb_t * sbh, osl_t * osh) -{ - uint16 delay = PMU_MAX_TRANSITION_DLY; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - delay = 7000; - break; - - case BCM4325_CHIP_ID: - case BCM4312_CHIP_ID: -#ifdef BCMQT - delay = 70; -#else - delay = 2800; -#endif - break; - - default: - PMU_MSG (("No PMU fast power up delay specified " - "for chip %x rev %d, using default %d us\n", - sbh->chip, sbh->chiprev, delay)); - break; - } - - return delay; -} - -uint32 BCMINITFN (sb_pmu_force_ilp) (sb_t * sbh, osl_t * osh, bool force) -{ - chipcregs_t *cc; - uint origidx; - uint32 oldpmucontrol; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - oldpmucontrol = R_REG (osh, &cc->pmucontrol); - if (force) - W_REG (osh, &cc->pmucontrol, oldpmucontrol & - ~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN)); - else - W_REG (osh, &cc->pmucontrol, oldpmucontrol | - (PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN)); - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); - - return oldpmucontrol; -} - -/* Setup min/max resources and up/down timers */ -typedef struct -{ - uint8 resnum; - uint16 updown; -} pmu_res_updown_t; - -typedef struct -{ - uint8 resnum; - int8 action; /* 0 - set, 1 - add, -1 - remove */ - uint32 depend_mask; -} pmu_res_depend_t; - -static const pmu_res_updown_t -BCMINITDATA (bcm4328a0_res_updown)[] = -{ - { - RES4328_EXT_SWITCHER_PWM, 0x0101}, - { - RES4328_BB_SWITCHER_PWM, 0x1f01}, - { - RES4328_BB_SWITCHER_BURST, 0x010f}, - { - RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, - { - RES4328_ILP_REQUEST, 0x0202}, - { - RES4328_RADIO_SWITCHER_PWM, 0x0f01}, - { - RES4328_RADIO_SWITCHER_BURST, 0x0f01}, - { - RES4328_ROM_SWITCH, 0x0101}, - { - RES4328_PA_REF_LDO, 0x0f01}, - { - RES4328_RADIO_LDO, 0x0f01}, - { - RES4328_AFE_LDO, 0x0f01}, - { - RES4328_PLL_LDO, 0x0f01}, - { - RES4328_BG_FILTBYP, 0x0101}, - { - RES4328_TX_FILTBYP, 0x0101}, - { - RES4328_RX_FILTBYP, 0x0101}, - { - RES4328_XTAL_PU, 0x0101}, - { - RES4328_XTAL_EN, 0xa001}, - { - RES4328_BB_PLL_FILTBYP, 0x0101}, - { - RES4328_RF_PLL_FILTBYP, 0x0101}, - { - RES4328_BB_PLL_PU, 0x0701} -}; - -static const pmu_res_depend_t -BCMINITDATA (bcm4328a0_res_depend)[] = -{ - /* Adjust ILP request resource not to force ext/BB switchers into burst mode */ - { - RES4328_ILP_REQUEST, 0, - PMURES_BIT (RES4328_EXT_SWITCHER_PWM) | - PMURES_BIT (RES4328_BB_SWITCHER_PWM)} -}; - -#ifdef BCMQT /* for power save on slow QT/small beacon interval */ -static const pmu_res_updown_t -BCMINITDATA (bcm4325a0_res_updown_qt)[] = -{ - { - RES4325_HT_AVAIL, 0x0300}, - { - RES4325_BBPLL_PWRSW_PU, 0x0101}, - { - RES4325_RFPLL_PWRSW_PU, 0x0101}, - { - RES4325_ALP_AVAIL, 0x0100}, - { - RES4325_XTAL_PU, 0x1000}, - { - RES4325_LNLDO1_PU, 0x0800}, - { - RES4325_CLDO_CBUCK_PWM, 0x0101}, - { - RES4325_CBUCK_PWM, 0x0803} -}; -#else -static const pmu_res_updown_t -BCMINITDATA (bcm4325a0_res_updown)[] = -{ - { - RES4325_XTAL_PU, 0x1501} -}; -#endif /* !BCMQT */ - -static const pmu_res_depend_t -BCMINITDATA (bcm4325a0_res_depend)[] = -{ - /* Adjust HT Avail resource dependencies */ - { - RES4325_HT_AVAIL, 1, - PMURES_BIT (RES4325_RX_PWRSW_PU) | PMURES_BIT (RES4325_TX_PWRSW_PU) | - PMURES_BIT (RES4325_LOGEN_PWRSW_PU) | PMURES_BIT (RES4325_AFE_PWRSW_PU)} -}; - -void BCMINITFN (sb_pmu_res_init) (sb_t * sbh, osl_t * osh) -{ - chipcregs_t *cc; - uint origidx; - const pmu_res_updown_t *pmu_res_updown_table = NULL; - int pmu_res_updown_table_sz = 0; - const pmu_res_depend_t *pmu_res_depend_table = NULL; - int pmu_res_depend_table_sz = 0; - uint32 min_mask = 0, max_mask = 0; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - /* Down to ILP request excluding ROM */ - min_mask = PMURES_BIT (RES4328_EXT_SWITCHER_PWM) | - PMURES_BIT (RES4328_BB_SWITCHER_PWM) | PMURES_BIT (RES4328_XTAL_EN); -#ifdef BCMROMOFFLOAD - /* Including ROM */ - min_mask |= PMURES_BIT (RES4328_ROM_SWITCH); -#endif - /* Allow (but don't require) PLL to turn on */ - max_mask = 0xfffff; - pmu_res_updown_table = bcm4328a0_res_updown; - pmu_res_updown_table_sz = ARRAYSIZE (bcm4328a0_res_updown); - pmu_res_depend_table = bcm4328a0_res_depend; - pmu_res_depend_table_sz = ARRAYSIZE (bcm4328a0_res_depend); - break; - case BCM4312_CHIP_ID: - /* keep default - * min_mask = 0xcbb; max_mask = 0x7ffff; - * pmu_res_updown_table_sz = 0; - * pmu_res_depend_table_sz = 0; - */ - break; - case BCM5354_CHIP_ID: - /* Allow (but don't require) PLL to turn on */ - max_mask = 0xfffff; - break; - - case BCM4325_CHIP_ID: - /* Leave OTP powered up and power it down later. */ - min_mask = - PMURES_BIT (RES4325_CBUCK_BURST) | PMURES_BIT (RES4325_LNLDO2_PU); - if (((sbh->chipst & CST4325_PMUTOP_2B_MASK) >> - CST4325_PMUTOP_2B_SHIFT) == 1) - min_mask |= PMURES_BIT (RES4325_CLDO_CBUCK_BURST); - /* Allow (but don't require) PLL to turn on */ - max_mask = 0x3fffff; -#ifdef BCMQT - pmu_res_updown_table = bcm4325a0_res_updown_qt; - pmu_res_updown_table_sz = ARRAYSIZE (bcm4325a0_res_updown_qt); -#else - pmu_res_updown_table = bcm4325a0_res_updown; - pmu_res_updown_table_sz = ARRAYSIZE (bcm4325a0_res_updown); - pmu_res_depend_table = bcm4325a0_res_depend; - pmu_res_depend_table_sz = ARRAYSIZE (bcm4325a0_res_depend); -#endif - break; - - default: - break; - } - - /* Program up/down timers */ - while (pmu_res_updown_table_sz--) - { - ASSERT (pmu_res_updown_table); - W_REG (osh, &cc->res_table_sel, - pmu_res_updown_table[pmu_res_updown_table_sz].resnum); - W_REG (osh, &cc->res_updn_timer, - pmu_res_updown_table[pmu_res_updown_table_sz].updown); - } - - /* Program resource dependencies table */ - while (pmu_res_depend_table_sz--) - { - ASSERT (pmu_res_depend_table); - W_REG (osh, &cc->res_table_sel, - pmu_res_depend_table[pmu_res_depend_table_sz].resnum); - switch (pmu_res_depend_table[pmu_res_depend_table_sz].action) - { - case 0: - W_REG (osh, &cc->res_dep_mask, - pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask); - break; - case 1: - OR_REG (osh, &cc->res_dep_mask, - pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask); - break; - case -1: - AND_REG (osh, &cc->res_dep_mask, - ~pmu_res_depend_table[pmu_res_depend_table_sz]. - depend_mask); - break; - default: - ASSERT (0); - break; - } - } - - /* program min resource mask */ - if (min_mask) - { - PMU_MSG (("Changing min_res_mask to 0x%x\n", min_mask)); - W_REG (osh, &cc->min_res_mask, min_mask); - } - /* program max resource mask */ - if (max_mask) - { - PMU_MSG (("Changing max_res_mask to 0x%x\n", max_mask)); - W_REG (osh, &cc->max_res_mask, max_mask); - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} - -/* setup pll and query clock speed */ -typedef struct -{ - uint16 freq; - uint8 xf; - uint8 wbint; - uint32 wbfrac; -} pmu0_xtaltab0_t; - -/* the following table is based on 880Mhz Fvco */ -#define PMU0_PLL0_FVCO 880000 /* Fvco 880Mhz */ -static const pmu0_xtaltab0_t -BCMINITDATA (pmu0_xtaltab0)[] = -{ - { - 12000, 1, 73, 349525}, - { - 13000, 2, 67, 725937}, - { - 14400, 3, 61, 116508}, - { - 15360, 4, 57, 305834}, - { - 16200, 5, 54, 336579}, - { - 16800, 6, 52, 399457}, - { - 19200, 7, 45, 873813}, - { - 19800, 8, 44, 466033}, - { - 20000, 9, 44, 0}, - { - 25000, 10, 70, 419430}, - { - 26000, 11, 67, 725937}, - { - 30000, 12, 58, 699050}, - { - 38400, 13, 45, 873813}, - { - 40000, 14, 45, 0}, - { - 0, 0, 0, 0} -}; - -#ifdef BCMUSBDEV -#define PMU0_XTAL0_DEFAULT 11 -#else -#define PMU0_XTAL0_DEFAULT 8 -#endif - -#ifdef BCMUSBDEV -/* - * Set new backplane PLL clock frequency - */ -static void BCMINITFN (sb_pmu0_sbclk4328) (sb_t * sbh, int freq) -{ - uint32 tmp, oldmax, oldmin, origidx; - chipcregs_t *cc; - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - /* Set new backplane PLL clock */ - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL0); - tmp = R_REG (osh, &cc->pllcontrol_data); - tmp &= ~(PMU0_PLL0_PC0_DIV_ARM_MASK); - tmp |= freq << PMU0_PLL0_PC0_DIV_ARM_SHIFT; - W_REG (osh, &cc->pllcontrol_data, tmp); - - /* Power cycle BB_PLL_PU by disabling/enabling it to take on new freq */ - /* Disable PLL */ - oldmin = R_REG (osh, &cc->min_res_mask); - oldmax = R_REG (osh, &cc->max_res_mask); - W_REG (osh, &cc->min_res_mask, oldmin & ~PMURES_BIT (RES4328_BB_PLL_PU)); - W_REG (osh, &cc->max_res_mask, oldmax & ~PMURES_BIT (RES4328_BB_PLL_PU)); - - /* It takes over several hundred usec to re-enable the PLL since the - * sequencer state machines run on ILP clock. Set delay at 450us to be safe. - * - * Be sure PLL is powered down first before re-enabling it. - */ - - OSL_DELAY (PLL_DELAY); - SPINWAIT ((R_REG (osh, &cc->res_state) & PMURES_BIT (RES4328_BB_PLL_PU)), - PLL_DELAY * 3); - - if (R_REG (osh, &cc->res_state) & PMURES_BIT (RES4328_BB_PLL_PU)) - { - /* If BB_PLL not powered down yet, new backplane PLL clock - * may not take effect. - * - * Still early during bootup so no serial output here. - */ - PMU_ERROR (("Fatal: BB_PLL not power down yet!\n")); - ASSERT (! - (R_REG (osh, &cc->res_state) & PMURES_BIT (RES4328_BB_PLL_PU))); - } - - /* Enable PLL */ - W_REG (osh, &cc->max_res_mask, oldmax); - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} -#endif /* BCMUSBDEV */ - -/* Set up PLL registers in the PMU as per the crystal speed. - * Uses xtalfreq variable, or passed-in default. - */ -static void -BCMINITFN (sb_pmu0_pllinit0) (sb_t * sbh, osl_t * osh, chipcregs_t * cc, - uint32 xtal) -{ - uint32 tmp; - const pmu0_xtaltab0_t *xt; - - if ((sb_chip (sbh) == BCM5354_CHIP_ID) && (xtal == 0)) - { - /* 5354 has xtal freq of 25MHz */ - xtal = 25000; - } - - /* Find the frequency in the table */ - for (xt = pmu0_xtaltab0; xt->freq; xt++) - if (xt->freq == xtal) - break; - if (xt->freq == 0) - xt = &pmu0_xtaltab0[PMU0_XTAL0_DEFAULT]; - - PMU_MSG (("XTAL %d (%d)\n", xtal, xt->xf)); - - /* Check current PLL state */ - tmp = (R_REG (osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> - PCTL_XTALFREQ_SHIFT; - if (tmp == xt->xf) - { - PMU_MSG (("PLL already programmed for %d.%d MHz\n", - (xt->freq / 1000), (xt->freq % 1000))); - -#ifdef BCMUSBDEV - if (sbh->chip == BCM4328_CHIP_ID) - sb_pmu0_sbclk4328 (sbh, PMU0_PLL0_PC0_DIV_ARM_88MHZ); -#endif - return; - } - - if (tmp) - { - PMU_MSG (("Reprogramming PLL for %d.%d MHz (was %d.%dMHz)\n", - (xt->freq / 1000), (xt->freq % 1000), - (pmu0_xtaltab0[tmp - 1].freq / 1000), - (pmu0_xtaltab0[tmp - 1].freq % 1000))); - } - else - { - PMU_MSG (("Programming PLL for %d.%d MHz\n", (xt->freq / 1000), - (xt->freq % 1000))); - } - - /* Make sure the PLL is off */ - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - AND_REG (osh, &cc->min_res_mask, ~PMURES_BIT (RES4328_BB_PLL_PU)); - AND_REG (osh, &cc->max_res_mask, ~PMURES_BIT (RES4328_BB_PLL_PU)); - break; - case BCM5354_CHIP_ID: - AND_REG (osh, &cc->min_res_mask, ~PMURES_BIT (RES5354_BB_PLL_PU)); - AND_REG (osh, &cc->max_res_mask, ~PMURES_BIT (RES5354_BB_PLL_PU)); - break; - default: - ASSERT (0); - } - SPINWAIT (R_REG (osh, &cc->clk_ctl_st) & CCS0_HTAVAIL, - PMU_MAX_TRANSITION_DLY); - ASSERT (!(R_REG (osh, &cc->clk_ctl_st) & CCS0_HTAVAIL)); - - PMU_MSG (("Done masking\n")); - - /* Write PDIV in pllcontrol[0] */ - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL0); - tmp = R_REG (osh, &cc->pllcontrol_data); - if (xt->freq >= PMU0_PLL0_PC0_PDIV_FREQ) - tmp |= PMU0_PLL0_PC0_PDIV_MASK; - else - tmp &= ~PMU0_PLL0_PC0_PDIV_MASK; - W_REG (osh, &cc->pllcontrol_data, tmp); - - /* Write WILD in pllcontrol[1] */ - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL1); - tmp = R_REG (osh, &cc->pllcontrol_data); - tmp = - ((tmp & ~(PMU0_PLL0_PC1_WILD_INT_MASK | PMU0_PLL0_PC1_WILD_FRAC_MASK)) | - (((xt-> - wbint << PMU0_PLL0_PC1_WILD_INT_SHIFT) & PMU0_PLL0_PC1_WILD_INT_MASK) - | ((xt->wbfrac << PMU0_PLL0_PC1_WILD_FRAC_SHIFT) & - PMU0_PLL0_PC1_WILD_FRAC_MASK))); - if (xt->wbfrac == 0) - tmp |= PMU0_PLL0_PC1_STOP_MOD; - else - tmp &= ~PMU0_PLL0_PC1_STOP_MOD; - W_REG (osh, &cc->pllcontrol_data, tmp); - - /* Write WILD in pllcontrol[2] */ - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL2); - tmp = R_REG (osh, &cc->pllcontrol_data); - tmp = ((tmp & ~PMU0_PLL0_PC2_WILD_INT_MASK) | - ((xt->wbint >> PMU0_PLL0_PC2_WILD_INT_SHIFT) & - PMU0_PLL0_PC2_WILD_INT_MASK)); - W_REG (osh, &cc->pllcontrol_data, tmp); - - PMU_MSG (("Done pll\n")); - - /* Write XtalFreq. Set the divisor also. */ - tmp = R_REG (osh, &cc->pmucontrol); - tmp = ((tmp & ~PCTL_ILP_DIV_MASK) | - (((((xt->freq + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) & - PCTL_ILP_DIV_MASK)); - tmp = ((tmp & ~PCTL_XTALFREQ_MASK) | - ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK)); - W_REG (osh, &cc->pmucontrol, tmp); -} - -static uint32 -BCMINITFN (sb_pmu0_alpclk0) (sb_t * sbh, osl_t * osh, chipcregs_t * cc) -{ - const pmu0_xtaltab0_t *xt; - uint32 xf; - - /* Find the frequency in the table */ - xf = (R_REG (osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> - PCTL_XTALFREQ_SHIFT; - for (xt = pmu0_xtaltab0; xt->freq; xt++) - if (xt->xf == xf) - break; - if (xt->freq == 0) - xt = &pmu0_xtaltab0[PMU0_XTAL0_DEFAULT]; - - return xt->freq * 1000; -} - -static uint32 -BCMINITFN (sb_pmu0_cpuclk0) (sb_t * sbh, osl_t * osh, chipcregs_t * cc) -{ - const pmu0_xtaltab0_t *xt; - uint32 xf, tmp, divarm; -#ifdef BCMDBG - uint32 pdiv, wbint, wbfrac, fvco; -#endif - - if (sb_chip (sbh) == BCM5354_CHIP_ID) - { - /* 5354 gets sb clock of 120MHz from main pll */ - return 120000000; - } - - /* Find the xtal frequency in the table */ - xf = (R_REG (osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> - PCTL_XTALFREQ_SHIFT; - for (xt = pmu0_xtaltab0; xt->freq; xt++) - if (xt->xf == xf) - break; - if (xt->freq == 0) - xt = &pmu0_xtaltab0[PMU0_XTAL0_DEFAULT]; - - /* Read divarm from pllcontrol[0] */ - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL0); - tmp = R_REG (osh, &cc->pllcontrol_data); - divarm = (tmp & PMU0_PLL0_PC0_DIV_ARM_MASK) >> PMU0_PLL0_PC0_DIV_ARM_SHIFT; - -#ifdef BCMDBG - /* Calculate Fvco based on xtal freq, pdiv, and wild */ - pdiv = tmp & PMU0_PLL0_PC0_PDIV_MASK; - - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL1); - tmp = R_REG (osh, &cc->pllcontrol_data); - wbfrac = - (tmp & PMU0_PLL0_PC1_WILD_FRAC_MASK) >> PMU0_PLL0_PC1_WILD_FRAC_SHIFT; - wbint = (tmp & PMU0_PLL0_PC1_WILD_INT_MASK) >> PMU0_PLL0_PC1_WILD_INT_SHIFT; - - W_REG (osh, &cc->pllcontrol_addr, PMU0_PLL0_PLLCTL2); - tmp = R_REG (osh, &cc->pllcontrol_data); - wbint += - (tmp & PMU0_PLL0_PC2_WILD_INT_MASK) << PMU0_PLL0_PC2_WILD_INT_SHIFT; - - fvco = (xt->freq * wbint) << 8; - fvco += (xt->freq * (wbfrac >> 10)) >> 2; - fvco += (xt->freq * (wbfrac & 0x3ff)) >> 10; - fvco >>= 8; - fvco >>= pdiv; - fvco /= 1000; - fvco *= 1000; - - PMU_MSG (("sb_pmu0_cpuclk0: wbint %u wbfrac %u fvco %u\n", - wbint, wbfrac, fvco)); - ASSERT (fvco == PMU0_PLL0_FVCO); -#endif /* BCMDBG */ - - /* Return ARM/SB clock */ - return PMU0_PLL0_FVCO / (divarm + PMU0_PLL0_PC0_DIV_ARM_BASE) * 1000; -} - -/* PMU corerev 1 pll programming for BCM4325 */ -/* setup pll and query clock speed */ -typedef struct -{ - uint16 fref; - uint8 xf; - uint8 p1div; - uint8 p2div; - uint8 ndiv_int; - uint32 ndiv_frac; -} pmu1_xtaltab0_t; - -/* the following table is based on 880Mhz Fvco */ -#define PMU1_PLL0_FVCO 880000 /* Fvco 880Mhz */ -static const pmu1_xtaltab0_t -BCMINITDATA (pmu1_xtaltab0)[] = -{ - { - 12000, 1, 3, 22, 0x9, 0xFFFFEF}, - { - 13000, 2, 1, 6, 0xb, 0x483483}, - { - 14400, 3, 1, 10, 0xa, 0x1C71C7}, - { - 15360, 4, 1, 5, 0xb, 0x755555}, - { - 16200, 5, 1, 10, 0x5, 0x6E9E06}, - { - 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, - { - 19200, 7, 1, 9, 0x5, 0x17B425}, - { - 19800, 8, 1, 11, 0x4, 0xA57EB}, - { - 20000, 9, 1, 11, 0x4, 0x0}, - { - 24000, 10, 3, 11, 0xa, 0x0}, - { - 25000, 11, 5, 16, 0xb, 0x0}, - { - 26000, 12, 1, 2, 0x10, 0xEC4EC4}, - { - 30000, 13, 3, 8, 0xb, 0x0}, - { - 38400, 14, 1, 5, 0x4, 0x955555}, - { - 40000, 15, 1, 2, 0xb, 0}, - { - 0, 0, 0, 0, 0, 0} -}; - -/* Default to 15360Khz crystal */ -#define PMU1_XTAL0_DEFAULT 3 - -static uint32 -BCMINITFN (sb_pmu1_alpclk0) (sb_t * sbh, osl_t * osh, chipcregs_t * cc) -{ - const pmu1_xtaltab0_t *xt; - uint32 xf; - - /* Find the frequency in the table */ - xf = (R_REG (osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> - PCTL_XTALFREQ_SHIFT; - for (xt = pmu1_xtaltab0; xt->fref; xt++) - if (xt->xf == xf) - break; - if (xt->fref == 0) - xt = &pmu1_xtaltab0[PMU1_XTAL0_DEFAULT]; - - return xt->fref * 1000; -} - -/* Set up PLL registers in the PMU as per the crystal speed. - * Uses xtalfreq variable, or passed-in default. - */ -static void -BCMINITFN (sb_pmu1_pllinit0) (sb_t * sbh, osl_t * osh, chipcregs_t * cc, - uint32 xtal) -{ - const pmu1_xtaltab0_t *xt; - uint32 tmp; - uint32 buf_strength = 0; - - /* 4312: assume default works */ - if (sbh->chip == BCM4312_CHIP_ID) - return; - - /* Find the frequency in the table */ - for (xt = pmu1_xtaltab0; xt->fref; xt++) - if (xt->fref == xtal) - break; - if (xt->fref == 0) - xt = &pmu1_xtaltab0[PMU1_XTAL0_DEFAULT]; - - PMU_MSG (("XTAL %d (%d)\n", xtal, xt->xf)); - - /* Check current PLL state */ - if (((R_REG (osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> - PCTL_XTALFREQ_SHIFT) == xt->xf) - { - PMU_MSG (("PLL already programmed for %d.%d MHz\n", - (xt->fref / 1000), (xt->fref % 1000))); - return; - } - - PMU_MSG (("Programming PLL for %d.%d MHz\n", (xt->fref / 1000), - (xt->fref % 1000))); - - /* Make sure the PLL is off */ - switch (sbh->chip) - { - case BCM4325_CHIP_ID: - AND_REG (osh, &cc->min_res_mask, - ~(PMURES_BIT (RES4325_BBPLL_PWRSW_PU) | - PMURES_BIT (RES4325_HT_AVAIL))); - AND_REG (osh, &cc->max_res_mask, - ~(PMURES_BIT (RES4325_BBPLL_PWRSW_PU) | - PMURES_BIT (RES4325_HT_AVAIL))); - - /* Change the BBPLL drive strength to 2 for all channels */ - buf_strength = 0x222222; - break; - default: - ASSERT (0); - } - SPINWAIT (R_REG (osh, &cc->clk_ctl_st) & CCS_HTAVAIL, - PMU_MAX_TRANSITION_DLY); - ASSERT (!(R_REG (osh, &cc->clk_ctl_st) & CCS_HTAVAIL)); - - PMU_MSG (("Done masking\n")); - - /* Write p1div and p2div to pllcontrol[0] */ - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); - tmp = R_REG (osh, &cc->pllcontrol_data) & - ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK); - tmp |= - ((xt-> - p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) | ((xt-> - p2div - << - PMU1_PLL0_PC0_P2DIV_SHIFT) - & - PMU1_PLL0_PC0_P2DIV_MASK); - W_REG (osh, &cc->pllcontrol_data, tmp); - - /* Write ndiv_int and ndiv_mode to pllcontrol[2] */ - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); - tmp = R_REG (osh, &cc->pllcontrol_data) & - ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK); - tmp |= - ((xt-> - ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) & PMU1_PLL0_PC2_NDIV_INT_MASK) - | ((1 << PMU1_PLL0_PC2_NDIV_MODE_SHIFT) & PMU1_PLL0_PC2_NDIV_MODE_MASK); - W_REG (osh, &cc->pllcontrol_data, tmp); - - /* Write ndiv_frac to pllcontrol[3] */ - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); - tmp = R_REG (osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK; - tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) & - PMU1_PLL0_PC3_NDIV_FRAC_MASK); - W_REG (osh, &cc->pllcontrol_data, tmp); - - if (buf_strength) - { - PMU_MSG (("Adjusting PLL buffer drive strength: %x\n", buf_strength)); - - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); - tmp = R_REG (osh, &cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK; - tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT); - W_REG (osh, &cc->pllcontrol_data, tmp); - } - - PMU_MSG (("Done pll\n")); - - /* Write XtalFreq. Set the divisor also. */ - tmp = R_REG (osh, &cc->pmucontrol) & - ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK); - tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) & - PCTL_ILP_DIV_MASK) | - ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK); - W_REG (osh, &cc->pmucontrol, tmp); -} - - -static uint32 -BCMINITFN (sb_pmu1_cpuclk0) (sb_t * sbh, osl_t * osh, chipcregs_t * cc) -{ - const pmu1_xtaltab0_t *xt; - uint32 xf, tmp, m1div; -#ifdef BCMDBG - uint32 ndiv_int, ndiv_frac, p2div, p1div, fvco; -#endif - - /* Find the xtal frequency in the table */ - xf = (R_REG (osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> - PCTL_XTALFREQ_SHIFT; - for (xt = pmu1_xtaltab0; xt->fref; xt++) - if (xt->xf == xf) - break; - if (xt->fref == 0) - xt = &pmu1_xtaltab0[PMU1_XTAL0_DEFAULT]; - - /* Read m1div from pllcontrol[1] */ - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); - tmp = R_REG (osh, &cc->pllcontrol_data); - m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT; - -#ifdef BCMDBG - /* Read p2div/p1div from pllcontrol[0] */ - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); - tmp = R_REG (osh, &cc->pllcontrol_data); - p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT; - p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT; - - /* Calculate Fvco based on xtal freq and ndiv and pdiv */ - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); - tmp = R_REG (osh, &cc->pllcontrol_data); - ndiv_int = - (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT; - - W_REG (osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); - tmp = R_REG (osh, &cc->pllcontrol_data); - ndiv_frac = - (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >> PMU1_PLL0_PC3_NDIV_FRAC_SHIFT; - - fvco = (xt->fref * ndiv_int) << 8; - fvco += (xt->fref * (ndiv_frac >> 12)) >> 4; - fvco += (xt->fref * (ndiv_frac & 0xfff)) >> 12; - fvco >>= 8; - fvco *= p2div; - fvco /= p1div; - fvco /= 1000; - fvco *= 1000; - - PMU_MSG (("sb_pmu0_cpuclk0: ndiv_int %u ndiv_frac %u " - "p2div %u p1div %u fvco %u\n", - ndiv_int, ndiv_frac, p2div, p1div, fvco)); - ASSERT (fvco == PMU1_PLL0_FVCO); -#endif /* BCMDBG */ - - /* Return ARM/SB clock */ - return PMU1_PLL0_FVCO / m1div * 1000; -} - -void BCMINITFN (sb_pmu_pll_init) (sb_t * sbh, osl_t * osh, uint xtalfreq) -{ - chipcregs_t *cc; - uint origidx; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - sb_pmu0_pllinit0 (sbh, osh, cc, xtalfreq); - break; - case BCM5354_CHIP_ID: - sb_pmu0_pllinit0 (sbh, osh, cc, xtalfreq); - break; - case BCM4325_CHIP_ID: - sb_pmu1_pllinit0 (sbh, osh, cc, xtalfreq); - break; - case BCM4312_CHIP_ID: - sb_pmu1_pllinit0 (sbh, osh, cc, xtalfreq); - break; - default: - PMU_MSG (("No PLL init done for chip %x rev %d pmurev %d\n", - sbh->chip, sbh->chiprev, sbh->pmurev)); - break; - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} - -uint32 BCMINITFN (sb_pmu_alp_clock) (sb_t * sbh, osl_t * osh) -{ - chipcregs_t *cc; - uint origidx; - uint32 clock = ALP_CLOCK; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - clock = sb_pmu0_alpclk0 (sbh, osh, cc); - break; - case BCM5354_CHIP_ID: - clock = sb_pmu0_alpclk0 (sbh, osh, cc); - break; - case BCM4325_CHIP_ID: - clock = sb_pmu1_alpclk0 (sbh, osh, cc); - break; - case BCM4312_CHIP_ID: - clock = sb_pmu1_alpclk0 (sbh, osh, cc); - /* always 20Mhz */ - clock = 20000 * 1000; - break; - default: - PMU_MSG (("No ALP clock specified " - "for chip %x rev %d pmurev %d, using default %d Hz\n", - sbh->chip, sbh->chiprev, sbh->pmurev, clock)); - break; - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); - return clock; -} - -uint BCMINITFN (sb_pmu_cpu_clock) (sb_t * sbh, osl_t * osh) -{ - chipcregs_t *cc; - uint origidx; - uint32 clock = HT_CLOCK; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - switch (sbh->chip) - { - case BCM4328_CHIP_ID: - clock = sb_pmu0_cpuclk0 (sbh, osh, cc); - break; - case BCM5354_CHIP_ID: - clock = sb_pmu0_cpuclk0 (sbh, osh, cc); - break; - case BCM4325_CHIP_ID: - clock = sb_pmu1_cpuclk0 (sbh, osh, cc); - break; - case BCM4312_CHIP_ID: - clock = sb_pmu1_cpuclk0 (sbh, osh, cc); - break; - default: - PMU_MSG (("No CPU clock specified " - "for chip %x rev %d pmurev %d, using default %d Hz\n", - sbh->chip, sbh->chiprev, sbh->pmurev, clock)); - break; - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); - return clock; -} - -void BCMINITFN (sb_pmu_init) (sb_t * sbh, osl_t * osh) -{ - chipcregs_t *cc; - uint origidx; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - if (sbh->pmurev >= 1) - { - if (sbh->chip == BCM4325_CHIP_ID && sbh->chiprev <= 1) - AND_REG (osh, &cc->pmucontrol, ~PCTL_NOILP_ON_WAIT); - else - OR_REG (osh, &cc->pmucontrol, PCTL_NOILP_ON_WAIT); - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} - -void BCMINITFN (sb_pmu_otp_power) (sb_t * sbh, osl_t * osh, bool on) -{ - chipcregs_t *cc; - uint origidx; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - switch (sbh->chip) - { - case BCM4325_CHIP_ID: - if (on) - { - OR_REG (osh, &cc->min_res_mask, PMURES_BIT (RES4325_LNLDO2_PU)); - if (sbh->boardflags & BFL_BUCKBOOST) - AND_REG (osh, &cc->min_res_mask, - ~PMURES_BIT (RES4325_BUCK_BOOST_PWM)); - OSL_DELAY (500); - } - else - { - if (sbh->boardflags & BFL_BUCKBOOST) - OR_REG (osh, &cc->min_res_mask, - PMURES_BIT (RES4325_BUCK_BOOST_PWM)); - AND_REG (osh, &cc->min_res_mask, ~PMURES_BIT (RES4325_LNLDO2_PU)); - } - break; - default: - break; - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} - -void -sb_pmu_rcal (sb_t * sbh, osl_t * osh) -{ - chipcregs_t *cc; - uint origidx; - - ASSERT (sbh->cccaps & CC_CAP_PMU); - - /* Remember original core before switch to chipc */ - origidx = sb_coreidx (sbh); - cc = sb_setcore (sbh, SB_CC, 0); - ASSERT (cc); - - switch (sbh->chip) - { - case BCM4325_CHIP_ID: - { - uint8 rcal_code; - uint32 val; - - /* Kick RCal */ - W_REG (osh, &cc->chipcontrol_addr, 1); - AND_REG (osh, &cc->chipcontrol_data, ~0x04); - OR_REG (osh, &cc->chipcontrol_data, 0x04); - - /* Wait for completion */ - SPINWAIT (0 == (R_REG (osh, &cc->chipstatus) & 0x08), - 10 * 1000 * 1000); - ASSERT (R_REG (osh, &cc->chipstatus) & 0x08); - - /* Drop the LSB to convert from 5 bit code to 4 bit code */ - rcal_code = (uint8) (R_REG (osh, &cc->chipstatus) >> 5) & 0x0f; - PMU_MSG (("RCal completed, status 0x%x, code 0x%x\n", - R_REG (osh, &cc->chipstatus), rcal_code)); - - /* Write RCal code into pmu_vreg_ctrl[32:29] */ - W_REG (osh, &cc->regcontrol_addr, 0); - val = R_REG (osh, &cc->regcontrol_data) & ~((uint32) 0x07 << 29); - val |= (uint32) (rcal_code & 0x07) << 29; - W_REG (osh, &cc->regcontrol_data, val); - W_REG (osh, &cc->regcontrol_addr, 1); - val = R_REG (osh, &cc->regcontrol_data) & ~(uint32) 0x01; - val |= (uint32) ((rcal_code >> 3) & 0x01); - W_REG (osh, &cc->regcontrol_data, val); - - /* Write RCal code into pmu_chip_ctrl[33:30] */ - W_REG (osh, &cc->chipcontrol_addr, 0); - val = R_REG (osh, &cc->chipcontrol_data) & ~((uint32) 0x03 << 30); - val |= (uint32) (rcal_code & 0x03) << 30; - W_REG (osh, &cc->chipcontrol_data, val); - W_REG (osh, &cc->chipcontrol_addr, 1); - val = R_REG (osh, &cc->chipcontrol_data) & ~(uint32) 0x03; - val |= (uint32) ((rcal_code >> 2) & 0x03); - W_REG (osh, &cc->chipcontrol_data, val); - - /* Set override in pmu_chip_ctrl[29] */ - W_REG (osh, &cc->chipcontrol_addr, 0); - OR_REG (osh, &cc->chipcontrol_data, (0x01 << 29)); - - /* Power off RCal block */ - W_REG (osh, &cc->chipcontrol_addr, 1); - AND_REG (osh, &cc->chipcontrol_data, ~0x04); - - break; - } - default: - break; - } - - /* Return to original core */ - sb_setcoreidx (sbh, origidx); -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h deleted file mode 100644 index c099717f10..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * BCM4710 address space map and definitions - * Think twice before adding to this file, this is not the kitchen sink - * These definitions are not guaranteed for all 47xx chips, only the 4710 - * - * Copyright 2004, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _bcm4710_h_ -#define _bcm4710_h_ - -/* Address map */ -#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */ -#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */ -#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */ -#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */ -#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */ - -/* Core register space */ -#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */ -#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */ -#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */ -#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */ -#define BCM4710_REG_USB 0x18004000 /* USB core registers */ -#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */ -#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */ -#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */ -#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */ - -#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */ -#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */ -#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */ -#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */ -#define BCM4710_PROG 0x1f800000 /* Programable interface */ -#define BCM4710_FLASH 0x1fc00000 /* Flash */ - -#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ - -#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300) - -#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000) -#define BCM4710_LED (BCM4710_EXTIF + 0x00900000) - -#define SBFLAG_PCI 0 -#define SBFLAG_ENET0 1 -#define SBFLAG_ILINE20 2 -#define SBFLAG_CODEC 3 -#define SBFLAG_USB 4 -#define SBFLAG_EXTIF 5 -#define SBFLAG_ENET1 6 - -#ifdef CONFIG_HWSIM -#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0) -#else -#define BCM4710_TRACE(trval) -#endif - - -/* BCM94702 CPCI -ExtIF used for LocalBus devs */ - -#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF -#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000) -#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000) -#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR -#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000) -#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000) -#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/ -#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0) - -#define LED_REG(x) \ - (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x))) - -/* - * Reset function implemented in PLD. Read or write should trigger hard reset - */ -#define SYS_HARD_RESET() \ - { for (;;) \ - *( (volatile unsigned char *)\ - KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \ - } - -#endif /* _bcm4710_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h deleted file mode 100644 index 4185167d75..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdefs.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Misc system wide definitions - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _bcmdefs_h_ -#define _bcmdefs_h_ - -/* - * One doesn't need to include this file explicitly, gets included automatically if - * typedefs.h is included. - */ - -/* Reclaiming text and data : - * The following macros specify special linker sections that can be reclaimed - * after a system is considered 'up'. - */ -#if defined(__GNUC__) && defined(BCMRECLAIM) -extern bool bcmreclaimed; -#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data -#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn -#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */ -#define BCMINITDATA(_data) _data -#define BCMINITFN(_fn) _fn -#define bcmreclaimed 0 -#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */ - -/* Reclaim uninit functions if BCMNODOWN is defined */ -/* and if they are not already removed by -gc-sections */ -#ifdef BCMNODOWN -#define BCMUNINITFN(_fn) BCMINITFN(_fn) -#else -#define BCMUNINITFN(_fn) _fn -#endif - -#ifdef BCMRECLAIM -#define CONST -#else -#define CONST const -#endif /* BCMRECLAIM */ - -/* Compatibility with old-style BCMRECLAIM */ -#define BCMINIT(_id) _id - - -/* Put some library data/code into ROM to reduce RAM requirements */ -#if defined(__GNUC__) && defined(BCMROMOFFLOAD) -#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data -#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn -#else -#define BCMROMDATA(_data) _data -#define BCMROMFN(_fn) _fn -#endif - -/* Bus types */ -#define SB_BUS 0 /* Silicon Backplane */ -#define PCI_BUS 1 /* PCI target */ -#define PCMCIA_BUS 2 /* PCMCIA target */ -#define SDIO_BUS 3 /* SDIO target */ -#define JTAG_BUS 4 /* JTAG */ -#define NO_BUS 0xFF /* Bus that does not support R/W REG */ - -/* Allows optimization for single-bus support */ -#ifdef BCMBUSTYPE -#define BUSTYPE(bus) (BCMBUSTYPE) -#else -#define BUSTYPE(bus) (bus) -#endif - -/* Defines for DMA Address Width - Shared between OSL and HNDDMA */ -#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */ -#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */ -#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */ - -#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */ -#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */ -#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */ -#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */ - -/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF). - * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL. - * There is a compile time check in wlc.c which ensure that this value is at least as big - * as TXOFF. This value is used in dma_rxfill (hnddma.c). - */ -#define BCMEXTRAHDROOM 160 - -/* Headroom required for dongle-to-host communication. Packets allocated - * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should - * leave this much room in front for low-level message headers which may - * be needed to get across the dongle bus to the host. (These messages - * don't go over the network, so room for the full WL header above would - * be a waste.) - */ -#define BCMDONGLEHDRSZ 8 - -/* Max. nvram variable table size */ -#define MAXSZ_NVRAM_VARS 4096 - - -#endif /* _bcmdefs_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h deleted file mode 100644 index 5d0bb92d94..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Broadcom device-specific manifest constants. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _BCMDEVS_H -#define _BCMDEVS_H - -/* PCI vendor IDs */ -#define VENDOR_EPIGRAM 0xfeda -#define VENDOR_BROADCOM 0x14e4 -#define VENDOR_3COM 0x10b7 -#define VENDOR_NETGEAR 0x1385 -#define VENDOR_DIAMOND 0x1092 -#define VENDOR_DELL 0x1028 -#define VENDOR_HP 0x0e11 -#define VENDOR_APPLE 0x106b -#define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ -#define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ -#define VENDOR_TI 0x104c /* Texas Instruments */ - -/* PCMCIA vendor IDs */ -#define VENDOR_BROADCOM_PCMCIA 0x02d0 - -/* SDIO vendor IDs */ -#define VENDOR_BROADCOM_SDIO 0x00BF - -/* PCI Device IDs */ -#define BCM4210_DEVICE_ID 0x1072 /* never used */ -#define BCM4230_DEVICE_ID 0x1086 /* never used */ -#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ -#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ -#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ -#define BCM4211_DEVICE_ID 0x4211 -#define BCM4231_DEVICE_ID 0x4231 -#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ -#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */ -#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */ -#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */ -#define BCM4328_D11DUAL_ID 0x4314 /* 4328 802.11a/g id */ -#define BCM4328_D11G_ID 0x4315 /* 4328 802.11g 2.4Ghz band id */ -#define BCM4328_D11A_ID 0x4316 /* 4328 802.11a 5Ghz band id */ -#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */ -#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */ -#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */ -#define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */ -#define BCM4325_D11G_ID 0x431c /* 4325 802.11g 2.4Ghz band id */ -#define BCM4325_D11A_ID 0x431d /* 4325 802.11a 5Ghz band id */ -#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ -#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ -#define BCM4306_UART_ID 0x4322 /* 4306 uart */ -#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ -#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ -#define BCM4306_D11G_ID2 0x4325 -#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */ -#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */ -#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */ -#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ -#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ -#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */ -#define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */ -#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */ -#define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */ -#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */ -#define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */ -#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */ -#define BCM4402_ENET_ID 0x4402 /* 4402 enet */ -#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ -#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ -#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ -#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ -#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ -#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ -#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ -#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */ -#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ -#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ -#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ -#define BCM47XX_USB_ID 0x4715 /* 47xx usb */ -#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ -#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ -#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ -#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ -#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ -#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ -#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */ -#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */ -#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */ -#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ -#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */ -#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */ -#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ -#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ -#define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */ -#define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */ -#define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */ -#define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */ - -/* Chip IDs */ -#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */ -#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */ -#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */ -#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */ -#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */ -#define BCM4312_CHIP_ID 0x4312 /* 4312 chip common chipid */ -#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */ -#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */ -#define BCM4328_CHIP_ID 0x4328 /* 4328 chip common chipid */ -#define BCM4325_CHIP_ID 0x4325 /* 4325 chip common chipid */ -#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */ -#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */ -#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */ -#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */ -#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */ -#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */ -#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */ - -/* Package IDs */ -#define BCM4303_PKG_ID 2 /* 4303 package id */ -#define BCM4309_PKG_ID 1 /* 4309 package id */ -#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ -#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ -#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ -#define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */ -#define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */ -#define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */ -#define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */ -#define BCM5354E_PKG_ID 1 /* 5354E package id */ -#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */ -#define HDLSIM_PKG_ID 14 /* HDL simulator package id */ -#define HWSIM_PKG_ID 15 /* Hardware simulator package id */ - -#define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */ -#define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */ -/* boardflags */ -#define BFL_BTCOEXIST 0x00000001 /* This board implements Bluetooth coexistance */ -#define BFL_PACTRL 0x00000002 /* This board has gpio 9 controlling the PA */ -#define BFL_AIRLINEMODE 0x00000004 /* This board implements gpio13 radio disable indication */ -#define BFL_ADCDIV 0x00000008 /* This board has the rssi ADC divider */ -#define BFL_ENETROBO 0x00000010 /* This board has robo switch or core */ -#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ -#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ -#define BFL_ENETADM 0x00000080 /* This board has ADMtek switch */ -#define BFL_ENETVLAN 0x00000100 /* This board has vlan capability */ -#define BFL_AFTERBURNER 0x00000200 /* This board supports Afterburner mode */ -#define BFL_NOPCI 0x00000400 /* This board leaves PCI floating */ -#define BFL_FEM 0x00000800 /* This board supports the Front End Module */ -#define BFL_EXTLNA 0x00001000 /* This board has an external LNA */ -#define BFL_HGPA 0x00002000 /* This board has a high gain PA */ -#define BFL_BTCMOD 0x00004000 /* This board' BTCOEXIST is in the alternate gpios */ -#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ -#define BFL_NOPA 0x00010000 /* This board has no PA */ -#define BFL_RSSIINV 0x00020000 /* This board's RSSI uses positive slope */ -#define BFL_PAREF 0x00040000 /* This board uses the PARef LDO */ -#define BFL_3TSWITCH 0x00080000 /* This board uses a triple throw switch shared with BT */ -#define BFL_PHASESHIFTER 0x00100000 /* This board can support phase shifter */ -#define BFL_BUCKBOOST 0x00200000 /* This board has buck/booster */ -/* boardflags2 */ -#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */ -#define BFL2_DEPRECIATED_STUB 0x00000002 /* This board flag is depreciated */ -#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits enabling TX Power Control */ -#define BFL2_2X4_DIV 0x00000008 /* This board supports the 2X4 diversity switch */ -#define BFL2_5G_PWRGAIN 0x00000010 /* This board supports 5G band power gain */ -#define BFL2_PCIEWAR_OVR 0x00000020 /* This board overrides ASPM and Clkreq settings */ -#define BFL2_CAESERS_BRD 0x00000040 /* This board is Dell Caeser's brd (unused by sw) */ - -/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ -#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */ -#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */ -#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */ -#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */ -#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ -#define BOARD_GPIO_ANT0_SEL 0x100 /* With BFL2_2X4_DIV */ -#define BOARD_GPIO_ANT1_SEL 0x200 /* With BFL2_2X4_DIV */ - -#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ -#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ -#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ -#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ - -/* power control defines */ -#define PLL_DELAY 150 /* us pll on delay */ -#define FREF_DELAY 200 /* us fref change delay */ -#define MIN_SLOW_CLK 32 /* us Slow clock period */ -#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ - -/* Reference Board Types */ -#define BU4710_BOARD 0x0400 -#define VSIM4710_BOARD 0x0401 -#define QT4710_BOARD 0x0402 - -#define BU4309_BOARD 0x040a -#define BCM94309CB_BOARD 0x040b -#define BCM94309MP_BOARD 0x040c -#define BCM4309AP_BOARD 0x040d - -#define BCM94302MP_BOARD 0x040e - -#define BU4306_BOARD 0x0416 -#define BCM94306CB_BOARD 0x0417 -#define BCM94306MP_BOARD 0x0418 - -#define BCM94710D_BOARD 0x041a -#define BCM94710R1_BOARD 0x041b -#define BCM94710R4_BOARD 0x041c -#define BCM94710AP_BOARD 0x041d - -#define BU2050_BOARD 0x041f - - -#define BCM94309G_BOARD 0x0421 - -#define BU4704_BOARD 0x0423 -#define BU4702_BOARD 0x0424 - -#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */ - - -#define BCM94702MN_BOARD 0x0428 - -/* BCM4702 1U CompactPCI Board */ -#define BCM94702CPCI_BOARD 0x0429 - -/* BCM4702 with BCM95380 VLAN Router */ -#define BCM95380RR_BOARD 0x042a - -/* cb4306 with SiGe PA */ -#define BCM94306CBSG_BOARD 0x042b - -/* cb4306 with SiGe PA */ -#define PCSG94306_BOARD 0x042d - -/* bu4704 with sdram */ -#define BU4704SD_BOARD 0x042e - -/* Dual 11a/11g Router */ -#define BCM94704AGR_BOARD 0x042f - -/* 11a-only minipci */ -#define BCM94308MP_BOARD 0x0430 - - - -#define BU4712_BOARD 0x0444 -#define BU4712SD_BOARD 0x045d -#define BU4712L_BOARD 0x045f - -/* BCM4712 boards */ -#define BCM94712AP_BOARD 0x0445 -#define BCM94712P_BOARD 0x0446 - -/* BCM4318 boards */ -#define BU4318_BOARD 0x0447 -#define CB4318_BOARD 0x0448 -#define MPG4318_BOARD 0x0449 -#define MP4318_BOARD 0x044a -#define SD4318_BOARD 0x044b - -/* BCM63XX boards */ -#define BCM96338_BOARD 0x6338 -#define BCM96348_BOARD 0x6348 -#define BCM96358_BOARD 0x6358 - -/* Another mp4306 with SiGe */ -#define BCM94306P_BOARD 0x044c - -/* mp4303 */ -#define BCM94303MP_BOARD 0x044e - -/* mpsgh4306 */ -#define BCM94306MPSGH_BOARD 0x044f - -/* BRCM 4306 w/ Front End Modules */ -#define BCM94306MPM 0x0450 -#define BCM94306MPL 0x0453 - -/* 4712agr */ -#define BCM94712AGR_BOARD 0x0451 - -/* pcmcia 4303 */ -#define PC4303_BOARD 0x0454 - -/* 5350K */ -#define BCM95350K_BOARD 0x0455 - -/* 5350R */ -#define BCM95350R_BOARD 0x0456 - -/* 4306mplna */ -#define BCM94306MPLNA_BOARD 0x0457 - -/* 4320 boards */ -#define BU4320_BOARD 0x0458 -#define BU4320S_BOARD 0x0459 -#define BCM94320PH_BOARD 0x045a - -/* 4306mph */ -#define BCM94306MPH_BOARD 0x045b - -/* 4306pciv */ -#define BCM94306PCIV_BOARD 0x045c - -#define BU4712SD_BOARD 0x045d - -#define BCM94320PFLSH_BOARD 0x045e - -#define BU4712L_BOARD 0x045f -#define BCM94712LGR_BOARD 0x0460 -#define BCM94320R_BOARD 0x0461 - -#define BU5352_BOARD 0x0462 - -#define BCM94318MPGH_BOARD 0x0463 - -#define BU4311_BOARD 0x0464 -#define BCM94311MC_BOARD 0x0465 -#define BCM94311MCAG_BOARD 0x0466 - -#define BCM95352GR_BOARD 0x0467 - -/* bcm95351agr */ -#define BCM95351AGR_BOARD 0x0470 - -/* bcm94704mpcb */ -#define BCM94704MPCB_BOARD 0x0472 - -/* 4785 boards */ -#define BU4785_BOARD 0x0478 - -/* 4321 boards */ -#define BU4321_BOARD 0x046b -#define BU4321E_BOARD 0x047c -#define MP4321_BOARD 0x046c -#define CB2_4321_BOARD 0x046d -#define MC4321_BOARD 0x046e - -/* 4328 boards */ -#define BU4328_BOARD 0x0481 -#define BCM4328SDG_BOARD 0x0482 -#define BCM4328SDAG_BOARD 0x0483 -#define BCM4328UG_BOARD 0x0484 -#define BCM4328UAG_BOARD 0x0485 -#define BCM4328PC_BOARD 0x0486 -#define BCM4328CF_BOARD 0x0487 - -/* 4325 boards */ -#define BU4325_BOARD 0x0490 - -/* # of GPIO pins */ -#define GPIO_NUMPINS 16 - -/* radio ID codes */ -#define NORADIO_ID 0xe4f5 -#define NORADIO_IDCODE 0x4e4f5246 - -#define BCM2050_ID 0x2050 -#define BCM2050_IDCODE 0x02050000 -#define BCM2050A0_IDCODE 0x1205017f -#define BCM2050A1_IDCODE 0x2205017f -#define BCM2050R8_IDCODE 0x8205017f - -#define BCM2055_ID 0x2055 -#define BCM2055_IDCODE 0x02055000 -#define BCM2055A0_IDCODE 0x1205517f - -#define BCM2060_ID 0x2060 -#define BCM2060_IDCODE 0x02060000 -#define BCM2060WW_IDCODE 0x1206017f - -#define BCM2062_ID 0x2062 -#define BCM2062_IDCODE 0x02062000 -#define BCM2062A0_IDCODE 0x0206217f - -#define BCM2063_ID 0x2063 -#define BCM2063_IDCODE 0x02063000 -#define BCM2063A0_IDCODE 0x0206317f - -/* parts of an idcode: */ -#define IDCODE_MFG_MASK 0x00000fff -#define IDCODE_MFG_SHIFT 0 -#define IDCODE_ID_MASK 0x0ffff000 -#define IDCODE_ID_SHIFT 12 -#define IDCODE_REV_MASK 0xf0000000 -#define IDCODE_REV_SHIFT 28 - -#endif /* _BCMDEVS_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs1.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs1.h deleted file mode 100644 index b7792221de..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmdevs1.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Broadcom device-specific manifest constants. - * - * Copyright 2005, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _BCMDEVS_H -#define _BCMDEVS_H - - -/* Known PCI vendor Id's */ -#define VENDOR_EPIGRAM 0xfeda -#define VENDOR_BROADCOM 0x14e4 -#define VENDOR_3COM 0x10b7 -#define VENDOR_NETGEAR 0x1385 -#define VENDOR_DIAMOND 0x1092 -#define VENDOR_DELL 0x1028 -#define VENDOR_HP 0x0e11 -#define VENDOR_APPLE 0x106b - -/* PCI Device Id's */ -#define BCM4210_DEVICE_ID 0x1072 /* never used */ -#define BCM4211_DEVICE_ID 0x4211 -#define BCM4230_DEVICE_ID 0x1086 /* never used */ -#define BCM4231_DEVICE_ID 0x4231 - -#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ -#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ -#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ -#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ - -#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ -#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ - -#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ -#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ - -#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */ -#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ -#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ -#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ -#define BCM47XX_USB_ID 0x4715 /* 47xx usb */ -#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ -#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ -#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ -#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ -#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ -#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ - -#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ - -#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */ -#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */ -#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */ -#define BCM4610_ENET_ID 0x4613 /* 4610 enet */ -#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */ -#define BCM4610_USB_ID 0x4615 /* 4610 usb */ - -#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */ -#define BCM4402_ENET_ID 0x4402 /* 4402 enet */ -#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ -#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ - -#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */ -#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */ - -#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */ -#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */ -#define BCM4307_ENET_ID 0x4306 /* 4307 enet */ -#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */ - -#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */ -#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ -#define BCM4306_D11G_ID2 0x4325 -#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ -#define BCM4306_UART_ID 0x4322 /* 4306 uart */ -#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ -#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ - -#define BCM4309_PKG_ID 1 /* 4309 package id */ - -#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ -#define BCM4303_PKG_ID 2 /* 4303 package id */ - -#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */ -#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */ -#define BCM4310_UART_ID 0x4312 /* 4310 uart */ -#define BCM4310_ENET_ID 0x4313 /* 4310 enet */ -#define BCM4310_USB_ID 0x4315 /* 4310 usb */ - -#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ -#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ - - -#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */ -#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ - -#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */ - -#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */ -#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */ -#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */ -#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */ - -#define FPGA_JTAGM_ID 0x4330 /* ??? */ - -/* Address map */ -#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */ -#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */ -#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */ -#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */ -#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */ - -/* Core register space */ -#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */ -#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */ -#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */ -#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */ -#define BCM4710_REG_USB 0x18004000 /* USB core registers */ -#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */ -#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */ -#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */ -#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */ - -#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */ -#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */ -#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */ -#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */ -#define BCM4710_PROG 0x1f800000 /* Programable interface */ -#define BCM4710_FLASH 0x1fc00000 /* Flash */ - -#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ - -#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300) - -#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000) -#define BCM4710_LED (BCM4710_EXTIF + 0x00900000) - -#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */ -#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ -#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ -#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ -#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ - -#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */ - -#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */ -#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */ -#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */ - -#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */ - -/* PCMCIA vendor Id's */ - -#define VENDOR_BROADCOM_PCMCIA 0x02d0 - -/* SDIO vendor Id's */ -#define VENDOR_BROADCOM_SDIO 0x00BF - - -/* boardflags */ -#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */ -#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */ -#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */ -#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */ -#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */ -#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */ -#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */ -#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */ -#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */ -#define BFL_FEM 0x0800 /* This board supports the Front End Module */ -#define BFL_EXTLNA 0x1000 /* This board has an external LNA */ -#define BFL_HGPA 0x2000 /* This board has a high gain PA */ -#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */ -#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */ - -/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ -#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */ -#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */ -#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */ -#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */ -#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */ -#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ -#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ -#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ -#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ -#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ - -/* Bus types */ -#define SB_BUS 0 /* Silicon Backplane */ -#define PCI_BUS 1 /* PCI target */ -#define PCMCIA_BUS 2 /* PCMCIA target */ -#define SDIO_BUS 3 /* SDIO target */ -#define JTAG_BUS 4 /* JTAG */ - -/* Allows optimization for single-bus support */ -#ifdef BCMBUSTYPE -#define BUSTYPE(bus) (BCMBUSTYPE) -#else -#define BUSTYPE(bus) (bus) -#endif - -/* power control defines */ -#define PLL_DELAY 150 /* us pll on delay */ -#define FREF_DELAY 200 /* us fref change delay */ -#define MIN_SLOW_CLK 32 /* us Slow clock period */ -#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ - -/* Reference Board Types */ - -#define BU4710_BOARD 0x0400 -#define VSIM4710_BOARD 0x0401 -#define QT4710_BOARD 0x0402 - -#define BU4610_BOARD 0x0403 -#define VSIM4610_BOARD 0x0404 - -#define BU4307_BOARD 0x0405 -#define BCM94301CB_BOARD 0x0406 -#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */ -#define BCM94301MP_BOARD 0x0407 -#define BCM94307MP_BOARD 0x0408 -#define BCMAP4307_BOARD 0x0409 - -#define BU4309_BOARD 0x040a -#define BCM94309CB_BOARD 0x040b -#define BCM94309MP_BOARD 0x040c -#define BCM4309AP_BOARD 0x040d - -#define BCM94302MP_BOARD 0x040e - -#define VSIM4310_BOARD 0x040f -#define BU4711_BOARD 0x0410 -#define BCM94310U_BOARD 0x0411 -#define BCM94310AP_BOARD 0x0412 -#define BCM94310MP_BOARD 0x0414 - -#define BU4306_BOARD 0x0416 -#define BCM94306CB_BOARD 0x0417 -#define BCM94306MP_BOARD 0x0418 - -#define BCM94710D_BOARD 0x041a -#define BCM94710R1_BOARD 0x041b -#define BCM94710R4_BOARD 0x041c -#define BCM94710AP_BOARD 0x041d - - -#define BU2050_BOARD 0x041f - - -#define BCM94309G_BOARD 0x0421 - -#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */ - -#define BU4704_BOARD 0x0423 -#define BU4702_BOARD 0x0424 - -#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */ - -#define BU4317_BOARD 0x0426 - - -#define BCM94702MN_BOARD 0x0428 - -/* BCM4702 1U CompactPCI Board */ -#define BCM94702CPCI_BOARD 0x0429 - -/* BCM4702 with BCM95380 VLAN Router */ -#define BCM95380RR_BOARD 0x042a - -/* cb4306 with SiGe PA */ -#define BCM94306CBSG_BOARD 0x042b - -/* mp4301 with 2050 radio */ -#define BCM94301MPL_BOARD 0x042c - -/* cb4306 with SiGe PA */ -#define PCSG94306_BOARD 0x042d - -/* bu4704 with sdram */ -#define BU4704SD_BOARD 0x042e - -/* Dual 11a/11g Router */ -#define BCM94704AGR_BOARD 0x042f - -/* 11a-only minipci */ -#define BCM94308MP_BOARD 0x0430 - - - -/* BCM94317 boards */ -#define BCM94317CB_BOARD 0x0440 -#define BCM94317MP_BOARD 0x0441 -#define BCM94317PCMCIA_BOARD 0x0442 -#define BCM94317SDIO_BOARD 0x0443 - -#define BU4712_BOARD 0x0444 -#define BU4712SD_BOARD 0x045d -#define BU4712L_BOARD 0x045f - -/* BCM4712 boards */ -#define BCM94712AP_BOARD 0x0445 -#define BCM94712P_BOARD 0x0446 - -/* BCM4318 boards */ -#define BU4318_BOARD 0x0447 -#define CB4318_BOARD 0x0448 -#define MPG4318_BOARD 0x0449 -#define MP4318_BOARD 0x044a -#define SD4318_BOARD 0x044b - -/* BCM63XX boards */ -#define BCM96338_BOARD 0x6338 -#define BCM96345_BOARD 0x6345 -#define BCM96348_BOARD 0x6348 - -/* Another mp4306 with SiGe */ -#define BCM94306P_BOARD 0x044c - -/* CF-like 4317 modules */ -#define BCM94317CF_BOARD 0x044d - -/* mp4303 */ -#define BCM94303MP_BOARD 0x044e - -/* mpsgh4306 */ -#define BCM94306MPSGH_BOARD 0x044f - -/* BRCM 4306 w/ Front End Modules */ -#define BCM94306MPM 0x0450 -#define BCM94306MPL 0x0453 - -/* 4712agr */ -#define BCM94712AGR_BOARD 0x0451 - -/* The real CF 4317 board */ -#define CFI4317_BOARD 0x0452 - -/* pcmcia 4303 */ -#define PC4303_BOARD 0x0454 - -/* 5350K */ -#define BCM95350K_BOARD 0x0455 - -/* 5350R */ -#define BCM95350R_BOARD 0x0456 - -/* 4306mplna */ -#define BCM94306MPLNA_BOARD 0x0457 - -/* 4320 boards */ -#define BU4320_BOARD 0x0458 -#define BU4320S_BOARD 0x0459 -#define BCM94320PH_BOARD 0x045a - -/* 4306mph */ -#define BCM94306MPH_BOARD 0x045b - -/* 4306pciv */ -#define BCM94306PCIV_BOARD 0x045c - -#define BU4712SD_BOARD 0x045d - -#define BCM94320PFLSH_BOARD 0x045e - -#define BU4712L_BOARD 0x045f -#define BCM94712LGR_BOARD 0x0460 -#define BCM94320R_BOARD 0x0461 - -#define BU5352_BOARD 0x0462 - -#define BCM94318MPGH_BOARD 0x0463 - - -#define BCM95352GR_BOARD 0x0467 - -/* bcm95351agr */ -#define BCM95351AGR_BOARD 0x0470 - -/* # of GPIO pins */ -#define GPIO_NUMPINS 16 - -#endif /* _BCMDEVS_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h deleted file mode 100644 index 042f6036fd..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmendian.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * local version of endian.h - byte order defines - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * -*/ - -#ifndef _BCMENDIAN_H_ -#define _BCMENDIAN_H_ - -#include <typedefs.h> - -/* Byte swap a 16 bit value */ -#define BCMSWAP16(val) \ - ((uint16)(\ - (((uint16)(val) & (uint16)0x00ffU) << 8) | \ - (((uint16)(val) & (uint16)0xff00U) >> 8))) - -/* Byte swap a 32 bit value */ -#define BCMSWAP32(val) \ - ((uint32)(\ - (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \ - (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \ - (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \ - (((uint32)(val) & (uint32)0xff000000UL) >> 24))) - -/* 2 Byte swap a 32 bit value */ -#define BCMSWAP32BY16(val) \ - ((uint32)(\ - (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \ - (((uint32)(val) & (uint32)0xffff0000UL) >> 16))) - - -static INLINE uint16 -bcmswap16(uint16 val) -{ - return BCMSWAP16(val); -} - -static INLINE uint32 -bcmswap32(uint32 val) -{ - return BCMSWAP32(val); -} - -static INLINE uint32 -bcmswap32by16(uint32 val) -{ - return BCMSWAP32BY16(val); -} - -/* buf - start of buffer of shorts to swap */ -/* len - byte length of buffer */ -static INLINE void -bcmswap16_buf(uint16 *buf, uint len) -{ - len = len/2; - - while (len--) { - *buf = bcmswap16(*buf); - buf++; - } -} - -#ifndef hton16 -#ifndef IL_BIGENDIAN -#define HTON16(i) BCMSWAP16(i) -#define hton16(i) bcmswap16(i) -#define hton32(i) bcmswap32(i) -#define ntoh16(i) bcmswap16(i) -#define ntoh32(i) bcmswap32(i) -#define ltoh16(i) (i) -#define ltoh32(i) (i) -#define htol16(i) (i) -#define htol32(i) (i) -#else -#define HTON16(i) (i) -#define hton16(i) (i) -#define hton32(i) (i) -#define ntoh16(i) (i) -#define ntoh32(i) (i) -#define ltoh16(i) bcmswap16(i) -#define ltoh32(i) bcmswap32(i) -#define htol16(i) bcmswap16(i) -#define htol32(i) bcmswap32(i) -#endif /* IL_BIGENDIAN */ -#endif /* hton16 */ - -#ifndef IL_BIGENDIAN -#define ltoh16_buf(buf, i) -#define htol16_buf(buf, i) -#else -#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i) -#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i) -#endif /* IL_BIGENDIAN */ - -/* -* store 16-bit value to unaligned little endian byte array. -*/ -static INLINE void -htol16_ua_store(uint16 val, uint8 *bytes) -{ - bytes[0] = val&0xff; - bytes[1] = val>>8; -} - -/* -* store 32-bit value to unaligned little endian byte array. -*/ -static INLINE void -htol32_ua_store(uint32 val, uint8 *bytes) -{ - bytes[0] = val&0xff; - bytes[1] = (val>>8)&0xff; - bytes[2] = (val>>16)&0xff; - bytes[3] = val>>24; -} - -/* -* store 16-bit value to unaligned network(big) endian byte array. -*/ -static INLINE void -hton16_ua_store(uint16 val, uint8 *bytes) -{ - bytes[1] = val&0xff; - bytes[0] = val>>8; -} - -/* -* store 32-bit value to unaligned network(big) endian byte array. -*/ -static INLINE void -hton32_ua_store(uint32 val, uint8 *bytes) -{ - bytes[3] = val&0xff; - bytes[2] = (val>>8)&0xff; - bytes[1] = (val>>16)&0xff; - bytes[0] = val>>24; -} - -/* -* load 16-bit value from unaligned little endian byte array. -*/ -static INLINE uint16 -ltoh16_ua(void *bytes) -{ - return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0]; -} - -/* -* load 32-bit value from unaligned little endian byte array. -*/ -static INLINE uint32 -ltoh32_ua(void *bytes) -{ - return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+ - (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0]; -} - -/* -* load 16-bit value from unaligned big(network) endian byte array. -*/ -static INLINE uint16 -ntoh16_ua(void *bytes) -{ - return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1]; -} - -/* -* load 32-bit value from unaligned big(network) endian byte array. -*/ -static INLINE uint32 -ntoh32_ua(void *bytes) -{ - return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+ - (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3]; -} - -#define ltoh_ua(ptr) (\ - sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \ - sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \ - (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \ -) - -#define ntoh_ua(ptr) (\ - sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \ - sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \ - (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \ -) - -#endif /* _BCMENDIAN_H_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h deleted file mode 100644 index 9dd6d8576a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmnvram.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * NVRAM variable manipulation - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _bcmnvram_h_ -#define _bcmnvram_h_ - -#ifndef _LANGUAGE_ASSEMBLY - -#include <typedefs.h> -#include <bcmdefs.h> - -struct nvram_header { - uint32 magic; - uint32 len; - uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ - uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ - uint32 config_ncdl; /* ncdl values for memc */ -}; - -struct nvram_tuple { - char *name; - char *value; - struct nvram_tuple *next; -}; - -/* - * Get default value for an NVRAM variable - */ -extern char *nvram_default_get(const char *name); - -/* - * Append a chunk of nvram variables to the global list - */ -extern int nvram_append(void *sb, char *vars, uint varsz); - -/* - * Check for reset button press for restoring factory defaults. - */ -extern bool nvram_reset(void *sbh); - -/* - * Disable NVRAM access. May be unnecessary or undefined on certain - * platforms. - */ -extern void nvram_exit(void *sbh); - -/* - * Get the value of an NVRAM variable. The pointer returned may be - * invalid after a set. - * @param name name of variable to get - * @return value of variable or NULL if undefined - */ -extern char * nvram_get(const char *name); - -/* - * Read the reset GPIO value from the nvram and set the GPIO - * as input - */ -extern int BCMINITFN(nvram_resetgpio_init)(void *sbh); - -/* - * Get the value of an NVRAM variable. - * @param name name of variable to get - * @return value of variable or NUL if undefined - */ -#define nvram_safe_get(name) (nvram_get(name) ? : "") - -/* - * Match an NVRAM variable. - * @param name name of variable to match - * @param match value to compare against value of variable - * @return TRUE if variable is defined and its value is string equal - * to match or FALSE otherwise - */ -static INLINE int -nvram_match(char *name, char *match) { - const char *value = nvram_get(name); - return (value && !strcmp(value, match)); -} - -/* - * Inversely match an NVRAM variable. - * @param name name of variable to match - * @param match value to compare against value of variable - * @return TRUE if variable is defined and its value is not string - * equal to invmatch or FALSE otherwise - */ -static INLINE int -nvram_invmatch(char *name, char *invmatch) { - const char *value = nvram_get(name); - return (value && strcmp(value, invmatch)); -} - -/* - * Set the value of an NVRAM variable. The name and value strings are - * copied into private storage. Pointers to previously set values - * may become invalid. The new value may be immediately - * retrieved but will not be permanently stored until a commit. - * @param name name of variable to set - * @param value value of variable - * @return 0 on success and errno on failure - */ -extern int nvram_set(const char *name, const char *value); - -/* - * Unset an NVRAM variable. Pointers to previously set values - * remain valid until a set. - * @param name name of variable to unset - * @return 0 on success and errno on failure - * NOTE: use nvram_commit to commit this change to flash. - */ -extern int nvram_unset(const char *name); - -/* - * Commit NVRAM variables to permanent storage. All pointers to values - * may be invalid after a commit. - * NVRAM values are undefined after a commit. - * @return 0 on success and errno on failure - */ -extern int nvram_commit(void); - -/* - * Get all NVRAM variables (format name=value\0 ... \0\0). - * @param buf buffer to store variables - * @param count size of buffer in bytes - * @return 0 on success and errno on failure - */ -extern int nvram_getall(char *nvram_buf, int count); - -/* - * returns the crc value of the nvram - * @param nvh nvram header pointer - */ -extern uint8 nvram_calc_crc(struct nvram_header * nvh); - -extern char* getvar(char *vars, const char *name); -extern int getintvar(char *vars, const char *name); - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* The NVRAM version number stored as an NVRAM variable */ -#define NVRAM_SOFTWARE_VERSION "1" - -#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */ -#define NVRAM_CLEAR_MAGIC 0x0 -#define NVRAM_INVALID_MAGIC 0xFFFFFFFF -#define NVRAM_VERSION 1 -#define NVRAM_HEADER_SIZE 20 -#define NVRAM_SPACE 0x8000 - -#define NVRAM_MAX_VALUE_LEN 255 -#define NVRAM_MAX_PARAM_LEN 64 - -#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */ -#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */ - -#endif /* _bcmnvram_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h deleted file mode 100644 index 518590082a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Misc useful routines to access NIC local SROM/OTP . - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _bcmsrom_h_ -#define _bcmsrom_h_ - -/* Maximum srom: 4 Kilobits == 512 bytes */ -#define SROM_MAX 512 - - -#define SROM_WORDS 64 - -#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ - -#define SROM_SSID 2 - -#define SROM_WL1LHMAXP 29 - -#define SROM_WL1LPAB0 30 -#define SROM_WL1LPAB1 31 -#define SROM_WL1LPAB2 32 - -#define SROM_WL1HPAB0 33 -#define SROM_WL1HPAB1 34 -#define SROM_WL1HPAB2 35 - -#define SROM_MACHI_IL0 36 -#define SROM_MACMID_IL0 37 -#define SROM_MACLO_IL0 38 -#define SROM_MACHI_ET0 39 -#define SROM_MACMID_ET0 40 -#define SROM_MACLO_ET0 41 -#define SROM_MACHI_ET1 42 -#define SROM_MACMID_ET1 43 -#define SROM_MACLO_ET1 44 -#define SROM3_MACHI 37 -#define SROM3_MACMID 38 -#define SROM3_MACLO 39 - -#define SROM_BXARSSI2G 40 -#define SROM_BXARSSI5G 41 - -#define SROM_TRI52G 42 -#define SROM_TRI5GHL 43 - -#define SROM_RXPO52G 45 - -#define SROM2_ENETPHY 45 - -#define SROM_AABREV 46 -/* Fields in AABREV */ -#define SROM_BR_MASK 0x00ff -#define SROM_CC_MASK 0x0f00 -#define SROM_CC_SHIFT 8 -#define SROM_AA0_MASK 0x3000 -#define SROM_AA0_SHIFT 12 -#define SROM_AA1_MASK 0xc000 -#define SROM_AA1_SHIFT 14 - -#define SROM_WL0PAB0 47 -#define SROM_WL0PAB1 48 -#define SROM_WL0PAB2 49 - -#define SROM_LEDBH10 50 -#define SROM_LEDBH32 51 - -#define SROM_WL10MAXP 52 - -#define SROM_WL1PAB0 53 -#define SROM_WL1PAB1 54 -#define SROM_WL1PAB2 55 - -#define SROM_ITT 56 - -#define SROM_BFL 57 -#define SROM_BFL2 28 -#define SROM3_BFL2 61 - -#define SROM_AG10 58 - -#define SROM_CCODE 59 - -#define SROM_OPO 60 - -#define SROM3_LEDDC 62 - -#define SROM_CRCREV 63 - -/* SROM Rev 4: Reallocate the software part of the srom to accomodate - * MIMO features. It assumes up to two PCIE functions and 440 bytes - * of useable srom i.e. the useable storage in chips with OTP that - * implements hardware redundancy. - */ - -#define SROM4_WORDS 220 - -#define SROM4_SIGN 32 -#define SROM4_SIGNATURE 0x5372 - -#define SROM4_BREV 33 - -#define SROM4_BFL0 34 -#define SROM4_BFL1 35 -#define SROM4_BFL2 36 -#define SROM4_BFL3 37 -#define SROM5_BFL0 37 -#define SROM5_BFL1 38 -#define SROM5_BFL2 39 -#define SROM5_BFL3 40 - -#define SROM4_MACHI 38 -#define SROM4_MACMID 39 -#define SROM4_MACLO 40 -#define SROM5_MACHI 41 -#define SROM5_MACMID 42 -#define SROM5_MACLO 43 - -#define SROM4_CCODE 41 -#define SROM4_REGREV 42 -#define SROM5_CCODE 34 -#define SROM5_REGREV 35 - -#define SROM4_LEDBH10 43 -#define SROM4_LEDBH32 44 -#define SROM5_LEDBH10 59 -#define SROM5_LEDBH32 60 - -#define SROM4_LEDDC 45 -#define SROM5_LEDDC 45 - -#define SROM4_AA 46 -#define SROM4_AA2G_MASK 0x00ff -#define SROM4_AA2G_SHIFT 0 -#define SROM4_AA5G_MASK 0xff00 -#define SROM4_AA5G_SHIFT 8 - -#define SROM4_AG10 47 -#define SROM4_AG32 48 - -#define SROM4_TXPID2G 49 -#define SROM4_TXPID5G 51 -#define SROM4_TXPID5GL 53 -#define SROM4_TXPID5GH 55 - -#define SROM4_TXRXC 61 -#define SROM4_TXCHAIN_MASK 0x000f -#define SROM4_TXCHAIN_SHIFT 0 -#define SROM4_RXCHAIN_MASK 0x00f0 -#define SROM4_RXCHAIN_SHIFT 4 -#define SROM4_SWITCH_MASK 0xff00 -#define SROM4_SWITCH_SHIFT 8 - -/* Per-path fields */ -#define MAX_PATH 4 -#define SROM4_PATH0 64 -#define SROM4_PATH1 87 -#define SROM4_PATH2 110 -#define SROM4_PATH3 133 - -#define SROM4_2G_ITT_MAXP 0 -#define SROM4_2G_PA 1 -#define SROM4_5G_ITT_MAXP 5 -#define SROM4_5GLH_MAXP 6 -#define SROM4_5G_PA 7 -#define SROM4_5GL_PA 11 -#define SROM4_5GH_PA 15 - -/* Fields in the ITT_MAXP and 5GLH_MAXP words */ -#define B2G_MAXP_MASK 0xff -#define B2G_ITT_SHIFT 8 -#define B5G_MAXP_MASK 0xff -#define B5G_ITT_SHIFT 8 -#define B5GH_MAXP_MASK 0xff -#define B5GL_MAXP_SHIFT 8 - -/* All the miriad power offsets */ -#define SROM4_2G_CCKPO 156 -#define SROM4_2G_OFDMPO 157 -#define SROM4_5G_OFDMPO 159 -#define SROM4_5GL_OFDMPO 161 -#define SROM4_5GH_OFDMPO 163 -#define SROM4_2G_MCSPO 165 -#define SROM4_5G_MCSPO 173 -#define SROM4_5GL_MCSPO 181 -#define SROM4_5GH_MCSPO 189 -#define SROM4_CDDPO 197 -#define SROM4_STBCPO 198 -#define SROM4_BW40PO 199 -#define SROM4_BWDUPPO 200 - -#define SROM4_CRCREV 219 - - -/*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. - * This is acombined srom for both MIMO and SISO boards, usable in - * the .130 4Kilobit OTP with hardware redundancy. - */ - -#define SROM8_SIGN 64 - -#define SROM8_BREV 65 - -#define SROM8_BFL0 66 -#define SROM8_BFL1 67 -#define SROM8_BFL2 68 -#define SROM8_BFL3 69 - -#define SROM8_MACHI 70 -#define SROM8_MACMID 71 -#define SROM8_MACLO 72 - -#define SROM8_CCODE 73 -#define SROM8_REGREV 74 - -#define SROM8_LEDBH10 75 -#define SROM8_LEDBH32 76 - -#define SROM8_LEDDC 77 - -#define SROM8_AA 78 - -#define SROM8_AG10 79 -#define SROM8_AG32 80 - -#define SROM8_TXRXC 81 - -#define SROM8_BXARSSI2G 82 -#define SROM8_BXARSSI5G 83 -#define SROM8_TRI52G 84 -#define SROM8_TRI5GHL 85 -#define SROM8_RXPO52G 86 - -/* Per-path offsets & fields */ -#define SROM8_PATH0 96 -#define SROM8_PATH1 112 -#define SROM8_PATH2 128 -#define SROM8_PATH3 144 - -#define SROM8_2G_ITT_MAXP 0 -#define SROM8_2G_PA 1 -#define SROM8_5G_ITT_MAXP 4 -#define SROM8_5GLH_MAXP 5 -#define SROM8_5G_PA 6 -#define SROM8_5GL_PA 9 -#define SROM8_5GH_PA 12 - -/* All the miriad power offsets */ -#define SROM8_2G_CCKPO 160 - -#define SROM8_2G_OFDMPO 161 -#define SROM8_5G_OFDMPO 163 -#define SROM8_5GL_OFDMPO 165 -#define SROM8_5GH_OFDMPO 167 - -#define SROM8_2G_MCSPO 169 -#define SROM8_5G_MCSPO 177 -#define SROM8_5GL_MCSPO 185 -#define SROM8_5GH_MCSPO 193 - -#define SROM8_CDDPO 201 -#define SROM8_STBCPO 202 -#define SROM8_BW40PO 203 -#define SROM8_BWDUPPO 204 - -/* SISO PA parameters are in the path0 spaces */ -#define SROM8_SISO 96 - -/* Legacy names for SISO PA paramters */ -#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) -#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) -#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) -#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) -#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) -#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) -#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) -#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) -#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) -#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) -#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) -#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) -#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) -#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) -#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) - -#define SROM8_CRCREV 219 - -/* Prototypes */ -extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh, - char **vars, uint *count); - -extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh, - uint byteoff, uint nbytes, uint16 *buf); -extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh, - uint byteoff, uint nbytes, uint16 *buf); - -extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, - char **vars, uint *count); - -#endif /* _bcmsrom_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h deleted file mode 100644 index 4c4986ce6c..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmutils.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * Misc useful os-independent macros and functions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * $Id$ - */ - -#ifndef _bcmutils_h_ -#define _bcmutils_h_ - -/* ctype replacement */ -#define _BCM_U 0x01 /* upper */ -#define _BCM_L 0x02 /* lower */ -#define _BCM_D 0x04 /* digit */ -#define _BCM_C 0x08 /* cntrl */ -#define _BCM_P 0x10 /* punct */ -#define _BCM_S 0x20 /* white space (space/lf/tab) */ -#define _BCM_X 0x40 /* hex digit */ -#define _BCM_SP 0x80 /* hard space (0x20) */ - -extern const unsigned char bcm_ctype[]; -#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)]) - -#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0) -#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0) -#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0) -#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0) -#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0) -#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0) -#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0) -#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0) -#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0) -#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0) -#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0) -#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c)) -#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c)) - -/* Buffer structure for collecting string-formatted data -* using bcm_bprintf() API. -* Use bcm_binit() to initialize before use -*/ - -struct bcmstrbuf { - char *buf; /* pointer to current position in origbuf */ - unsigned int size; /* current (residual) size in bytes */ - char *origbuf; /* unmodified pointer to orignal buffer */ - unsigned int origsize; /* unmodified orignal buffer size in bytes */ -}; - -/* ** driver-only section ** */ -#ifdef BCMDRIVER -#include <osl.h> - -#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */ - -/* - * Spin at most 'us' microseconds while 'exp' is true. - * Caller should explicitly test 'exp' when this completes - * and take appropriate error action if 'exp' is still true. - */ -#define SPINWAIT(exp, us) { \ - uint countdown = (us) + 9; \ - while ((exp) && (countdown >= 10)) {\ - OSL_DELAY(10); \ - countdown -= 10; \ - } \ -} - - -/* osl multi-precedence packet queue */ -#ifndef PKTQ_LEN_DEFAULT -#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */ -#endif -#ifndef PKTQ_MAX_PREC -#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */ -#endif - -typedef struct pktq_prec { - void *head; /* first packet to dequeue */ - void *tail; /* last packet to dequeue */ - uint16 len; /* number of queued packets */ - uint16 max; /* maximum number of queued packets */ -} pktq_prec_t; - - -/* multi-priority pkt queue */ -struct pktq { - uint16 num_prec; /* number of precedences in use */ - uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ - uint16 max; /* total max packets */ - uint16 len; /* total number of packets */ - /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ - struct pktq_prec q[PKTQ_MAX_PREC]; -}; - -/* simple, non-priority pkt queue */ -struct spktq { - uint16 num_prec; /* number of precedences in use (always 1) */ - uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ - uint16 max; /* total max packets */ - uint16 len; /* total number of packets */ - /* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */ - struct pktq_prec q[1]; -}; - -#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--) - -/* forward definition of ether_addr structure used by some function prototypes */ - -struct ether_addr; - -/* operations on a specific precedence in packet queue */ - -#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max)) -#define pktq_plen(pq, prec) ((pq)->q[prec].len) -#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len) -#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max) -#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0) - -#define pktq_ppeek(pq, prec) ((pq)->q[prec].head) -#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail) - -extern void *pktq_penq(struct pktq *pq, int prec, void *p); -extern void *pktq_penq_head(struct pktq *pq, int prec, void *p); -extern void *pktq_pdeq(struct pktq *pq, int prec); -extern void *pktq_pdeq_tail(struct pktq *pq, int prec); -/* Empty the queue at particular precedence level */ -extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir); -/* Remove a specified packet from its queue */ -extern bool pktq_pdel(struct pktq *pq, void *p, int prec); - -/* operations on a set of precedences in packet queue */ - -extern int pktq_mlen(struct pktq *pq, uint prec_bmp); -extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out); - -/* operations on packet queue as a whole */ - -#define pktq_len(pq) ((int)(pq)->len) -#define pktq_max(pq) ((int)(pq)->max) -#define pktq_avail(pq) ((int)((pq)->max - (pq)->len)) -#define pktq_full(pq) ((pq)->len >= (pq)->max) -#define pktq_empty(pq) ((pq)->len == 0) - -/* operations for single precedence queues */ -#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p)) -#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p)) -#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0) -#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0) -#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len) - -extern void pktq_init(struct pktq *pq, int num_prec, int max_len); -/* prec_out may be NULL if caller is not interested in return value */ -extern void *pktq_deq(struct pktq *pq, int *prec_out); -extern void *pktq_deq_tail(struct pktq *pq, int *prec_out); -extern void *pktq_peek(struct pktq *pq, int *prec_out); -extern void *pktq_peek_tail(struct pktq *pq, int *prec_out); -extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir); /* Empty the entire queue */ -extern int pktq_setmax(struct pktq *pq, int max_len); - -/* externs */ -/* packet */ -extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf); -extern uint pkttotlen(osl_t *osh, void *p); -extern void *pktlast(osl_t *osh, void *p); - -/* Get priority from a packet and pass it back in scb (or equiv) */ -extern uint pktsetprio(void *pkt, bool update_vtag); -#define PKTPRIO_VDSCP 0x100 /* DSCP prio found after VLAN tag */ -#define PKTPRIO_VLAN 0x200 /* VLAN prio found */ -#define PKTPRIO_UPD 0x400 /* DSCP used to update VLAN prio */ -#define PKTPRIO_DSCP 0x800 /* DSCP prio found */ - -/* string */ -extern int BCMROMFN(bcm_atoi)(char *s); -extern ulong BCMROMFN(bcm_strtoul)(char *cp, char **endp, uint base); -extern char *BCMROMFN(bcmstrstr)(char *haystack, char *needle); -extern char *BCMROMFN(bcmstrcat)(char *dest, const char *src); -extern char *BCMROMFN(bcmstrncat)(char *dest, const char *src, uint size); -extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen); -/* ethernet address */ -extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf); -extern int BCMROMFN(bcm_ether_atoe)(char *p, struct ether_addr *ea); - -/* ip address */ -struct ipv4_addr; -extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf); - -/* delay */ -extern void bcm_mdelay(uint ms); -/* variable access */ -extern char *getvar(char *vars, const char *name); -extern int getintvar(char *vars, const char *name); -extern uint getgpiopin(char *vars, char *pin_name, uint def_pin); -#ifdef BCMPERFSTATS -extern void bcm_perf_enable(void); -extern void bcmstats(char *fmt); -extern void bcmlog(char *fmt, uint a1, uint a2); -extern void bcmdumplog(char *buf, int size); -extern int bcmdumplogent(char *buf, uint idx); -#else -#define bcm_perf_enable() -#define bcmstats(fmt) -#define bcmlog(fmt, a1, a2) -#define bcmdumplog(buf, size) *buf = '\0' -#define bcmdumplogent(buf, idx) -1 -#endif /* BCMPERFSTATS */ -extern char *bcm_nvram_vars(uint *length); -extern int bcm_nvram_cache(void *sbh); - -/* Support for sharing code across in-driver iovar implementations. - * The intent is that a driver use this structure to map iovar names - * to its (private) iovar identifiers, and the lookup function to - * find the entry. Macros are provided to map ids and get/set actions - * into a single number space for a switch statement. - */ - -/* iovar structure */ -typedef struct bcm_iovar { - const char *name; /* name for lookup and display */ - uint16 varid; /* id for switch */ - uint16 flags; /* driver-specific flag bits */ - uint16 type; /* base type of argument */ - uint16 minlen; /* min length for buffer vars */ -} bcm_iovar_t; - -/* varid definitions are per-driver, may use these get/set bits */ - -/* IOVar action bits for id mapping */ -#define IOV_GET 0 /* Get an iovar */ -#define IOV_SET 1 /* Set an iovar */ - -/* Varid to actionid mapping */ -#define IOV_GVAL(id) ((id)*2) -#define IOV_SVAL(id) (((id)*2)+IOV_SET) -#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET) - -/* flags are per-driver based on driver attributes */ - -extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name); -extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set); - -#endif /* BCMDRIVER */ - -/* Base type definitions */ -#define IOVT_VOID 0 /* no value (implictly set only) */ -#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */ -#define IOVT_INT8 2 /* integer values are range-checked */ -#define IOVT_UINT8 3 /* unsigned int 8 bits */ -#define IOVT_INT16 4 /* int 16 bits */ -#define IOVT_UINT16 5 /* unsigned int 16 bits */ -#define IOVT_INT32 6 /* int 32 bits */ -#define IOVT_UINT32 7 /* unsigned int 32 bits */ -#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */ -#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER) - -/* Initializer for IOV type strings */ -#define BCM_IOV_TYPE_INIT { \ - "void", \ - "bool", \ - "int8", \ - "uint8", \ - "int16", \ - "uint16", \ - "int32", \ - "uint32", \ - "buffer", \ - "" } - -#define BCM_IOVT_IS_INT(type) (\ - (type == IOVT_BOOL) || \ - (type == IOVT_INT8) || \ - (type == IOVT_UINT8) || \ - (type == IOVT_INT16) || \ - (type == IOVT_UINT16) || \ - (type == IOVT_INT32) || \ - (type == IOVT_UINT32)) - -/* ** driver/apps-shared section ** */ - -#define BCME_STRLEN 64 /* Max string length for BCM errors */ -#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST)) - - -/* - * error codes could be added but the defined ones shouldn't be changed/deleted - * these error codes are exposed to the user code - * when ever a new error code is added to this list - * please update errorstring table with the related error string and - * update osl files with os specific errorcode map -*/ - -#define BCME_OK 0 /* Success */ -#define BCME_ERROR -1 /* Error generic */ -#define BCME_BADARG -2 /* Bad Argument */ -#define BCME_BADOPTION -3 /* Bad option */ -#define BCME_NOTUP -4 /* Not up */ -#define BCME_NOTDOWN -5 /* Not down */ -#define BCME_NOTAP -6 /* Not AP */ -#define BCME_NOTSTA -7 /* Not STA */ -#define BCME_BADKEYIDX -8 /* BAD Key Index */ -#define BCME_RADIOOFF -9 /* Radio Off */ -#define BCME_NOTBANDLOCKED -10 /* Not band locked */ -#define BCME_NOCLK -11 /* No Clock */ -#define BCME_BADRATESET -12 /* BAD Rate valueset */ -#define BCME_BADBAND -13 /* BAD Band */ -#define BCME_BUFTOOSHORT -14 /* Buffer too short */ -#define BCME_BUFTOOLONG -15 /* Buffer too long */ -#define BCME_BUSY -16 /* Busy */ -#define BCME_NOTASSOCIATED -17 /* Not Associated */ -#define BCME_BADSSIDLEN -18 /* Bad SSID len */ -#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */ -#define BCME_BADCHAN -20 /* Bad Channel */ -#define BCME_BADADDR -21 /* Bad Address */ -#define BCME_NORESOURCE -22 /* Not Enough Resources */ -#define BCME_UNSUPPORTED -23 /* Unsupported */ -#define BCME_BADLEN -24 /* Bad length */ -#define BCME_NOTREADY -25 /* Not Ready */ -#define BCME_EPERM -26 /* Not Permitted */ -#define BCME_NOMEM -27 /* No Memory */ -#define BCME_ASSOCIATED -28 /* Associated */ -#define BCME_RANGE -29 /* Not In Range */ -#define BCME_NOTFOUND -30 /* Not Found */ -#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */ -#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */ -#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */ -#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */ -#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */ -#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */ -#define BCME_VERSION -37 /* Incorrect version */ -#define BCME_LAST BCME_VERSION - -/* These are collection of BCME Error strings */ -#define BCMERRSTRINGTABLE { \ - "OK", \ - "Undefined error", \ - "Bad Argument", \ - "Bad Option", \ - "Not up", \ - "Not down", \ - "Not AP", \ - "Not STA", \ - "Bad Key Index", \ - "Radio Off", \ - "Not band locked", \ - "No clock", \ - "Bad Rate valueset", \ - "Bad Band", \ - "Buffer too short", \ - "Buffer too long", \ - "Busy", \ - "Not Associated", \ - "Bad SSID len", \ - "Out of Range Channel", \ - "Bad Channel", \ - "Bad Address", \ - "Not Enough Resources", \ - "Unsupported", \ - "Bad length", \ - "Not Ready", \ - "Not Permitted", \ - "No Memory", \ - "Associated", \ - "Not In Range", \ - "Not Found", \ - "WME Not Enabled", \ - "TSPEC Not Found", \ - "ACM Not Supported", \ - "Not WME Association", \ - "SDIO Bus Error", \ - "Dongle Not Accessible", \ - "Incorrect version" \ -} - -#ifndef ABS -#define ABS(a) (((a) < 0)?-(a):(a)) -#endif /* ABS */ - -#ifndef MIN -#define MIN(a, b) (((a) < (b))?(a):(b)) -#endif /* MIN */ - -#ifndef MAX -#define MAX(a, b) (((a) > (b))?(a):(b)) -#endif /* MAX */ - -#define CEIL(x, y) (((x) + ((y)-1)) / (y)) -#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) -#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0) -#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0) -#define VALID_MASK(mask) !((mask) & ((mask) + 1)) -#ifndef OFFSETOF -#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member) -#endif /* OFFSETOF */ -#ifndef ARRAYSIZE -#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0])) -#endif - -/* bit map related macros */ -#ifndef setbit -#ifndef NBBY /* the BSD family defines NBBY */ -#define NBBY 8 /* 8 bits per byte */ -#endif /* #ifndef NBBY */ -#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY)) -#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) -#define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) -#define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0) -#endif /* setbit */ - -#define NBITS(type) (sizeof(type) * 8) -#define NBITVAL(nbits) (1 << (nbits)) -#define MAXBITVAL(nbits) ((1 << (nbits)) - 1) -#define NBITMASK(nbits) MAXBITVAL(nbits) -#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8) - -/* basic mux operation - can be optimized on several architectures */ -#define MUX(pred, true, false) ((pred) ? (true) : (false)) - -/* modulo inc/dec - assumes x E [0, bound - 1] */ -#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1) -#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1) - -/* modulo inc/dec, bound = 2^k */ -#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1)) -#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1)) - -/* modulo add/sub - assumes x, y E [0, bound - 1] */ -#define MODADD(x, y, bound) \ - MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y)) -#define MODSUB(x, y, bound) \ - MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y)) - -/* module add/sub, bound = 2^k */ -#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1)) -#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1)) - -/* crc defines */ -#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */ -#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */ -#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */ -#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */ -#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */ -#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */ - -/* bcm_format_flags() bit description structure */ -typedef struct bcm_bit_desc { - uint32 bit; - const char* name; -} bcm_bit_desc_t; - -/* tag_ID/length/value_buffer tuple */ -typedef struct bcm_tlv { - uint8 id; - uint8 len; - uint8 data[1]; -} bcm_tlv_t; - -/* Check that bcm_tlv_t fits into the given buflen */ -#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len)) - -/* buffer length for ethernet address from bcm_ether_ntoa() */ -#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */ - -/* unaligned load and store macros */ -#ifdef IL_BIGENDIAN -static INLINE uint32 -load32_ua(uint8 *a) -{ - return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]); -} - -static INLINE void -store32_ua(uint8 *a, uint32 v) -{ - a[0] = (v >> 24) & 0xff; - a[1] = (v >> 16) & 0xff; - a[2] = (v >> 8) & 0xff; - a[3] = v & 0xff; -} - -static INLINE uint16 -load16_ua(uint8 *a) -{ - return ((a[0] << 8) | a[1]); -} - -static INLINE void -store16_ua(uint8 *a, uint16 v) -{ - a[0] = (v >> 8) & 0xff; - a[1] = v & 0xff; -} - -#else /* IL_BIGENDIAN */ - -static INLINE uint32 -load32_ua(uint8 *a) -{ - return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]); -} - -static INLINE void -store32_ua(uint8 *a, uint32 v) -{ - a[3] = (v >> 24) & 0xff; - a[2] = (v >> 16) & 0xff; - a[1] = (v >> 8) & 0xff; - a[0] = v & 0xff; -} - -static INLINE uint16 -load16_ua(uint8 *a) -{ - return ((a[1] << 8) | a[0]); -} - -static INLINE void -store16_ua(uint8 *a, uint16 v) -{ - a[1] = (v >> 8) & 0xff; - a[0] = v & 0xff; -} - -#endif /* IL_BIGENDIAN */ - -/* externs */ -/* crc */ -extern uint8 BCMROMFN(hndcrc8)(uint8 *p, uint nbytes, uint8 crc); -extern uint16 BCMROMFN(hndcrc16)(uint8 *p, uint nbytes, uint16 crc); -extern uint32 BCMROMFN(hndcrc32)(uint8 *p, uint nbytes, uint32 crc); -/* format/print */ -extern char *bcm_brev_str(uint16 brev, char *buf); -extern void printfbig(char *buf); - -/* IE parsing */ -extern bcm_tlv_t *BCMROMFN(bcm_next_tlv)(bcm_tlv_t *elt, int *buflen); -extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs)(void *buf, int buflen, uint key); -extern bcm_tlv_t *BCMROMFN(bcm_parse_ordered_tlvs)(void *buf, int buflen, uint key); - -/* bcmerror */ -extern const char *bcmerrorstr(int bcmerror); - -/* multi-bool data type: set of bools, mbool is true if any is set */ -typedef uint32 mbool; -#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */ -#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */ -#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */ -#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val))) - -/* power conversion */ -extern uint16 BCMROMFN(bcm_qdbm_to_mw)(uint8 qdbm); -extern uint8 BCMROMFN(bcm_mw_to_qdbm)(uint16 mw); - -/* generic datastruct to help dump routines */ -struct fielddesc { - const char *nameandfmt; - uint32 offset; - uint32 len; -}; - -extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size); -extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...); - -typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset); -extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, - char *buf, uint32 bufsize); - -extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len); -extern uint BCMROMFN(bcm_bitcount)(uint8 *bitmap, uint bytelength); - -#ifdef BCMDBG_PKT /* pkt logging for debugging */ -#define PKTLIST_SIZE 1000 -typedef struct { - void *list[PKTLIST_SIZE]; /* List of pointers to packets */ - uint count; /* Total count of the packets */ -} pktlist_info_t; - -extern void pktlist_add(pktlist_info_t *pktlist, void *p); -extern void pktlist_remove(pktlist_info_t *pktlist, void *p); -extern char* pktlist_dump(pktlist_info_t *pktlist, char *buf); -#endif /* BCMDBG_PKT */ - -#endif /* _bcmutils_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h deleted file mode 100644 index aba28bd9de..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndchipc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * HND SiliconBackplane chipcommon support. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndchipc_h_ -#define _hndchipc_h_ - -typedef void (*sb_serial_init_fn)(void *regs, uint irq, uint baud_base, uint reg_shift); - -extern void sb_serial_init(sb_t *sbh, sb_serial_init_fn add); - -extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap); -extern void sb_jtagm_disable(osl_t *osh, void *h); -extern uint32 jtag_rwreg(osl_t *osh, void *h, uint32 ir, uint32 dr); - -typedef void (*cc_isr_fn)(void* cbdata, uint32 ccintst); - -extern bool sb_cc_register_isr(sb_t *sbh, cc_isr_fn isr, uint32 ccintmask, void *cbdata); -extern void sb_cc_isr(sb_t *sbh, chipcregs_t *regs); - -#endif /* _hndchipc_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h deleted file mode 100644 index 5cfee709bc..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndcpu.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * HND SiliconBackplane MIPS/ARM cores software interface. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndcpu_h_ -#define _hndcpu_h_ - -#if defined(mips) -#include <hndmips.h> -#elif defined(__arm__) || defined(__thumb__) || defined(__thumb2__) -#include <hndarm.h> -#endif - -extern uint sb_irq(sb_t *sbh); -extern uint32 sb_cpu_clock(sb_t *sbh); -extern void hnd_cpu_wait(sb_t *sbh); -extern void hnd_cpu_jumpto(void *addr); -extern void hnd_cpu_reset(sb_t *sbh); - -#endif /* _hndcpu_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h deleted file mode 100644 index c6051ec17b..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * HND SiliconBackplane MIPS core software interface. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndmips_h_ -#define _hndmips_h_ - -extern void sb_mips_init(sb_t *sbh, uint shirq_map_base); -extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock); -extern void enable_pfc(uint32 mode); -extern uint32 sb_memc_get_ncdl(sb_t *sbh); - -#if defined(BCMPERFSTATS) -/* enable counting - exclusive version. Only one set of counters allowed at a time */ -extern void hndmips_perf_cyclecount_enable(void); -extern void hndmips_perf_instrcount_enable(void); -extern void hndmips_perf_icachecount_enable(void); -extern void hndmips_perf_dcachecount_enable(void); -/* start and stop counting */ -#define hndmips_perf_start01() \ - MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000) -#define hndmips_perf_stop01() \ - MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000) -/* retrieve coutners - counters *decrement* */ -#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0)) -#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1)) -#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2)) -/* enable counting - modular version. Each counters can be enabled separately. */ -extern void hndmips_perf_icache_hit_enable(void); -extern void hndmips_perf_icache_miss_enable(void); -extern uint32 hndmips_perf_read_instrcount(void); -extern uint32 hndmips_perf_read_cache_miss(void); -extern uint32 hndmips_perf_read_cache_hit(void); -#endif - -#endif /* _hndmips_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h deleted file mode 100644 index 9a3bc4a091..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpci.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * HND SiliconBackplane PCI core software interface. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _hndpci_h_ -#define _hndpci_h_ - -extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len); -extern void sbpci_ban(uint16 core); -extern int sbpci_init(sb_t *sbh); -extern int sbpci_init_pci(sb_t *sbh); -extern void sbpci_init_cores(sb_t *sbh); -extern void sbpci_arb_park(sb_t *sbh, uint parkid); - -#define PCI_PARK_NVRAM 0xff - -#endif /* _hndpci_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h deleted file mode 100644 index bef3758fc4..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndpmu.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * HND SiliconBackplane PMU support. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _hndpmu_h_ -#define _hndpmu_h_ - -#define SET_LDO_VOLTAGE_LDO1 1 -#define SET_LDO_VOLTAGE_LDO2 2 -#define SET_LDO_VOLTAGE_LDO3 3 -#define SET_LDO_VOLTAGE_PAREF 4 - -extern void sb_pmu_init(sb_t *sbh, osl_t *osh); -extern void sb_pmu_pll_init(sb_t *sbh, osl_t *osh, uint32 xtalfreq); -extern void sb_pmu_res_init(sb_t *sbh, osl_t *osh); -extern uint32 sb_pmu_force_ilp(sb_t *sbh, osl_t *osh, bool force); -extern uint32 sb_pmu_cpu_clock(sb_t *sbh, osl_t *osh); -extern uint32 sb_pmu_alp_clock(sb_t *sbh, osl_t *osh); - -extern void sb_pmu_set_switcher_voltage(sb_t *sbh, osl_t *osh, uint8 bb_voltage, uint8 rf_voltage); -extern void sb_pmu_set_ldo_voltage(sb_t *sbh, osl_t *osh, uint8 ldo, uint8 voltage); -extern void sb_pmu_paref_ldo_enable(sb_t *sbh, osl_t *osh, bool enable); -extern uint16 sb_pmu_fast_pwrup_delay(sb_t *sbh, osl_t *osh); -extern void sb_pmu_otp_power(sb_t *sbh, osl_t *osh, bool on); -extern void sb_pmu_rcal(sb_t *sbh, osl_t *osh); - -#endif /* _hndpmu_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h deleted file mode 100644 index c98beb6373..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linux_gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Linux Broadcom BCM47xx GPIO char driver - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _linux_gpio_h_ -#define _linux_gpio_h_ - -struct gpio_ioctl { - uint32 mask; - uint32 val; -}; - -#define GPIO_IOC_MAGIC 'G' - -/* reserve/release a gpio to the caller */ -#define GPIO_IOC_RESERVE _IOWR(GPIO_IOC_MAGIC, 1, struct gpio_ioctl) -#define GPIO_IOC_RELEASE _IOWR(GPIO_IOC_MAGIC, 2, struct gpio_ioctl) -/* ioctls to read/write the gpio registers */ -#define GPIO_IOC_OUT _IOWR(GPIO_IOC_MAGIC, 3, struct gpio_ioctl) -#define GPIO_IOC_IN _IOWR(GPIO_IOC_MAGIC, 4, struct gpio_ioctl) -#define GPIO_IOC_OUTEN _IOWR(GPIO_IOC_MAGIC, 5, struct gpio_ioctl) - -#endif /* _linux_gpio_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h deleted file mode 100644 index 3f16345f74..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/linuxver.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Linux-specific abstractions to gain some independence from linux kernel versions. - * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _linuxver_h_ -#define _linuxver_h_ - -#include <linux/version.h> -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) -#include <linux/config.h> -#else -#include <linux/autoconf.h> -#endif -#include <linux/module.h> - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0)) -/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */ -#ifdef __UNDEF_NO_VERSION__ -#undef __NO_VERSION__ -#else -#define __NO_VERSION__ -#endif -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0) -#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i") -#define module_param_string(_name_, _string_, _size_, _perm_) \ - MODULE_PARM(_string_, "c" __MODULE_STRING(_size_)) -#endif - -/* linux/malloc.h is deprecated, use linux/slab.h instead. */ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9)) -#include <linux/malloc.h> -#else -#include <linux/slab.h> -#endif - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/string.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/netdevice.h> -#include <asm/io.h> - -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41)) -#include <linux/workqueue.h> -#else -#include <linux/tqueue.h> -#ifndef work_struct -#define work_struct tq_struct -#endif -#ifndef INIT_WORK -#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data)) -#endif -#ifndef schedule_work -#define schedule_work(_work) schedule_task((_work)) -#endif -#ifndef flush_scheduled_work -#define flush_scheduled_work() flush_scheduled_tasks() -#endif -#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */ - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20) -#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func) -#else -#define MY_INIT_WORK(_work, _func, _data) INIT_WORK(_work, _func, _data) -typedef void (*work_func_t)(void *work); -#endif /* < 2.6.20 */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) -/* Some distributions have their own 2.6.x compatibility layers */ -#ifndef IRQ_NONE -typedef void irqreturn_t; -#define IRQ_NONE -#define IRQ_HANDLED -#define IRQ_RETVAL(x) -#endif -#else -typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs); -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */ - -#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE) - -#include <pcmcia/version.h> -#include <pcmcia/cs_types.h> -#include <pcmcia/cs.h> -#include <pcmcia/cistpl.h> -#include <pcmcia/cisreg.h> -#include <pcmcia/ds.h> - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69)) -/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which - * does this, but it's not in 2.4 so we do our own for now. - */ -static inline void -cs_error(client_handle_t handle, int func, int ret) -{ - error_info_t err = { func, ret }; - CardServices(ReportError, handle, &err); -} -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15)) - -typedef struct pcmcia_device dev_link_t; - -#endif - -#endif /* CONFIG_PCMCIA */ - -#ifndef __exit -#define __exit -#endif -#ifndef __devexit -#define __devexit -#endif -#ifndef __devinit -#define __devinit __init -#endif -#ifndef __devinitdata -#define __devinitdata -#endif -#ifndef __devexit_p -#define __devexit_p(x) x -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)) - -#define pci_get_drvdata(dev) (dev)->sysdata -#define pci_set_drvdata(dev, value) (dev)->sysdata = (value) - -/* - * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration - */ - -struct pci_device_id { - unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ - unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ - unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ - unsigned long driver_data; /* Data private to the driver */ -}; - -struct pci_driver { - struct list_head node; - char *name; - const struct pci_device_id *id_table; /* NULL if wants all devices */ - int (*probe)(struct pci_dev *dev, - const struct pci_device_id *id); /* New device inserted */ - void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug - * capable driver) - */ - void (*suspend)(struct pci_dev *dev); /* Device suspended */ - void (*resume)(struct pci_dev *dev); /* Device woken up */ -}; - -#define MODULE_DEVICE_TABLE(type, name) -#define PCI_ANY_ID (~0) - -/* compatpci.c */ -#define pci_module_init pci_register_driver -extern int pci_register_driver(struct pci_driver *drv); -extern void pci_unregister_driver(struct pci_driver *drv); - -#endif /* PCI registration */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18)) -#ifdef MODULE -#define module_init(x) int init_module(void) { return x(); } -#define module_exit(x) void cleanup_module(void) { x(); } -#else -#define module_init(x) __initcall(x); -#define module_exit(x) __exitcall(x); -#endif -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48)) -#define list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13)) -#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)]) -#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44)) -#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23)) -#define pci_enable_device(dev) do { } while (0) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14)) -#define net_device device -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42)) - -/* - * DMA mapping - * - * See linux/Documentation/DMA-mapping.txt - */ - -#ifndef PCI_DMA_TODEVICE -#define PCI_DMA_TODEVICE 1 -#define PCI_DMA_FROMDEVICE 2 -#endif - -typedef u32 dma_addr_t; - -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, - dma_addr_t *dma_handle) -{ - void *ret; - int gfp = GFP_ATOMIC | GFP_DMA; - - ret = (void *)__get_free_pages(gfp, get_order(size)); - - if (ret != NULL) { - memset(ret, 0, size); - *dma_handle = virt_to_bus(ret); - } - return ret; -} -static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle) -{ - free_pages((unsigned long)vaddr, get_order(size)); -} -#ifdef ILSIM -extern uint pci_map_single(void *dev, void *va, uint size, int direction); -extern void pci_unmap_single(void *dev, uint pa, uint size, int direction); -#else -#define pci_map_single(cookie, address, size, dir) virt_to_bus(address) -#define pci_unmap_single(cookie, address, size, dir) -#endif - -#endif /* DMA mapping */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43)) - -#define dev_kfree_skb_any(a) dev_kfree_skb(a) -#define netif_down(dev) do { (dev)->start = 0; } while (0) - -/* pcmcia-cs provides its own netdevice compatibility layer */ -#ifndef _COMPAT_NETDEVICE_H - -/* - * SoftNet - * - * For pre-softnet kernels we need to tell the upper layer not to - * re-enter start_xmit() while we are in there. However softnet - * guarantees not to enter while we are in there so there is no need - * to do the netif_stop_queue() dance unless the transmit queue really - * gets stuck. This should also improve performance according to tests - * done by Aman Singla. - */ - -#define dev_kfree_skb_irq(a) dev_kfree_skb(a) -#define netif_wake_queue(dev) \ - do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0) -#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy) - -static inline void netif_start_queue(struct net_device *dev) -{ - dev->tbusy = 0; - dev->interrupt = 0; - dev->start = 1; -} - -#define netif_queue_stopped(dev) (dev)->tbusy -#define netif_running(dev) (dev)->start - -#endif /* _COMPAT_NETDEVICE_H */ - -#define netif_device_attach(dev) netif_start_queue(dev) -#define netif_device_detach(dev) netif_stop_queue(dev) - -/* 2.4.x renamed bottom halves to tasklets */ -#define tasklet_struct tq_struct -static inline void tasklet_schedule(struct tasklet_struct *tasklet) -{ - queue_task(tasklet, &tq_immediate); - mark_bh(IMMEDIATE_BH); -} - -static inline void tasklet_init(struct tasklet_struct *tasklet, - void (*func)(unsigned long), - unsigned long data) -{ - tasklet->next = NULL; - tasklet->sync = 0; - tasklet->routine = (void (*)(void *))func; - tasklet->data = (void *)data; -} -#define tasklet_kill(tasklet) { do{} while (0); } - -/* 2.4.x introduced del_timer_sync() */ -#define del_timer_sync(timer) del_timer(timer) - -#else - -#define netif_down(dev) - -#endif /* SoftNet */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3)) - -/* - * Emit code to initialise a tq_struct's routine and data pointers - */ -#define PREPARE_TQUEUE(_tq, _routine, _data) \ - do { \ - (_tq)->routine = _routine; \ - (_tq)->data = _data; \ - } while (0) - -/* - * Emit code to initialise all of a tq_struct - */ -#define INIT_TQUEUE(_tq, _routine, _data) \ - do { \ - INIT_LIST_HEAD(&(_tq)->list); \ - (_tq)->sync = 0; \ - PREPARE_TQUEUE((_tq), (_routine), (_data)); \ - } while (0) - -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */ - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6)) - -/* Power management related routines */ - -static inline int -pci_save_state(struct pci_dev *dev, u32 *buffer) -{ - int i; - if (buffer) { - for (i = 0; i < 16; i++) - pci_read_config_dword(dev, i * 4, &buffer[i]); - } - return 0; -} - -static inline int -pci_restore_state(struct pci_dev *dev, u32 *buffer) -{ - int i; - - if (buffer) { - for (i = 0; i < 16; i++) - pci_write_config_dword(dev, i * 4, buffer[i]); - } - /* - * otherwise, write the context information we know from bootup. - * This works around a problem where warm-booting from Windows - * combined with a D3(hot)->D0 transition causes PCI config - * header data to be forgotten. - */ - else { - for (i = 0; i < 6; i ++) - pci_write_config_dword(dev, - PCI_BASE_ADDRESS_0 + (i * 4), - pci_resource_start(dev, i)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } - return 0; -} - -#endif /* PCI power management */ - -/* Old cp0 access macros deprecated in 2.4.19 */ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19)) -#define read_c0_count() read_32bit_cp0_register(CP0_COUNT) -#endif - -/* Module refcount handled internally in 2.6.x */ -#ifndef SET_MODULE_OWNER -#define SET_MODULE_OWNER(dev) do {} while (0) -#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT -#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT -#else -#define OLD_MOD_INC_USE_COUNT do {} while (0) -#define OLD_MOD_DEC_USE_COUNT do {} while (0) -#endif - -#ifndef SET_NETDEV_DEV -#define SET_NETDEV_DEV(net, pdev) do {} while (0) -#endif - -#ifndef HAVE_FREE_NETDEV -#define free_netdev(dev) kfree(dev) -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) -/* struct packet_type redefined in 2.6.x */ -#define af_packet_priv data -#endif - -/* suspend args */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11) -#define DRV_SUSPEND_STATE_TYPE pm_message_t -#else -#define DRV_SUSPEND_STATE_TYPE uint32 -#endif - -#endif /* _linuxver_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h deleted file mode 100644 index 7e44f1b890..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h +++ /dev/null @@ -1,542 +0,0 @@ -/* - * HND Run Time Environment for standalone MIPS programs. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _MISPINC_H -#define _MISPINC_H - - -/* MIPS defines */ - -#ifdef _LANGUAGE_ASSEMBLY - -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - - -/* CP0 Registers */ - -#define C0_INX $0 -#define C0_RAND $1 -#define C0_TLBLO0 $2 -#define C0_TLBLO C0_TLBLO0 -#define C0_TLBLO1 $3 -#define C0_CTEXT $4 -#define C0_PGMASK $5 -#define C0_WIRED $6 -#define C0_INFO $7 -#define C0_BADVADDR $8 -#define C0_COUNT $9 -#define C0_TLBHI $10 -#define C0_COMPARE $11 -#define C0_SR $12 -#define C0_STATUS C0_SR -#define C0_CAUSE $13 -#define C0_EPC $14 -#define C0_PRID $15 -#define C0_CONFIG $16 -#define C0_LLADDR $17 -#define C0_WATCHLO $18 -#define C0_WATCHHI $19 -#define C0_XCTEXT $20 -#define C0_DIAGNOSTIC $22 -#define C0_BROADCOM C0_DIAGNOSTIC -#define C0_PERFORMANCE $25 -#define C0_ECC $26 -#define C0_CACHEERR $27 -#define C0_TAGLO $28 -#define C0_TAGHI $29 -#define C0_ERREPC $30 -#define C0_DESAVE $31 - -/* - * LEAF - declare leaf routine - */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, 0, ra - -/* - * END - mark end of function - */ -#define END(function) \ - .end function; \ - .size function, . - function - -#define _ULCAST_ - -#define MFC0_SEL(dst, src, sel) \ - .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel)) - - -#define MTC0_SEL(dst, src, sel) \ - .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel)) - -#else - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -#define _ULCAST_ (unsigned long) - - -/* CP0 Registers */ - -#define C0_INX 0 /* CP0: TLB Index */ -#define C0_RAND 1 /* CP0: TLB Random */ -#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */ -#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */ -#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */ -#define C0_CTEXT 4 /* CP0: Context */ -#define C0_PGMASK 5 /* CP0: TLB PageMask */ -#define C0_WIRED 6 /* CP0: TLB Wired */ -#define C0_INFO 7 /* CP0: Info */ -#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */ -#define C0_COUNT 9 /* CP0: Count */ -#define C0_TLBHI 10 /* CP0: TLB EntryHi */ -#define C0_COMPARE 11 /* CP0: Compare */ -#define C0_SR 12 /* CP0: Processor Status */ -#define C0_STATUS C0_SR /* CP0: Processor Status */ -#define C0_CAUSE 13 /* CP0: Exception Cause */ -#define C0_EPC 14 /* CP0: Exception PC */ -#define C0_PRID 15 /* CP0: Processor Revision Indentifier */ -#define C0_CONFIG 16 /* CP0: Config */ -#define C0_LLADDR 17 /* CP0: LLAddr */ -#define C0_WATCHLO 18 /* CP0: WatchpointLo */ -#define C0_WATCHHI 19 /* CP0: WatchpointHi */ -#define C0_XCTEXT 20 /* CP0: XContext */ -#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */ -#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */ -#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */ -#define C0_ECC 26 /* CP0: ECC */ -#define C0_CACHEERR 27 /* CP0: CacheErr */ -#define C0_TAGLO 28 /* CP0: TagLo */ -#define C0_TAGHI 29 /* CP0: TagHi */ -#define C0_ERREPC 30 /* CP0: ErrorEPC */ -#define C0_DESAVE 31 /* CP0: DebugSave */ - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * Memory segments (32bit kernel mode addresses) - */ -#undef KUSEG -#undef KSEG0 -#undef KSEG1 -#undef KSEG2 -#undef KSEG3 -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 -#define PHYSADDR_MASK 0x1fffffff - -/* - * Map an address to a certain kernel segment - */ -#undef PHYSADDR -#undef KSEG0ADDR -#undef KSEG1ADDR -#undef KSEG2ADDR -#undef KSEG3ADDR - -#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK) -#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0) -#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1) -#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2) -#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3) - - -#ifndef Index_Invalidate_I -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill_I 0x14 -#define Hit_Writeback_Inv_D 0x15 - /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define R5K_Page_Invalidate_S 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b - /* 0x1c is unused */ - /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f -#endif /* !Index_Invalidate_I */ - - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -#ifndef ST0_UM -/* - * Bitfields in the mips32 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_UM 0x00000010 -#define ST0_SWINT0 0x00000100 -#define ST0_SWINT1 0x00000200 -#define ST0_HWINT0 0x00000400 -#define ST0_HWINT1 0x00000800 -#define ST0_HWINT2 0x00001000 -#define ST0_HWINT3 0x00002000 -#define ST0_HWINT4 0x00004000 -#define ST0_HWINT5 0x00008000 -#define ST0_IM 0x0000ff00 -#define ST0_NMI 0x00080000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_RP 0x08000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#endif /* !ST0_UM */ - - -/* - * Bitfields in the mips32 cp0 cause register - */ -#define C_EXC 0x0000007c -#define C_EXC_SHIFT 2 -#define C_INT 0x0000ff00 -#define C_INT_SHIFT 8 -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) -#define C_WP 0x00400000 -#define C_IV 0x00800000 -#define C_CE 0x30000000 -#define C_CE_SHIFT 28 -#define C_BD 0x80000000 - -/* Values in C_EXC */ -#define EXC_INT 0 -#define EXC_TLBM 1 -#define EXC_TLBL 2 -#define EXC_TLBS 3 -#define EXC_AEL 4 -#define EXC_AES 5 -#define EXC_IBE 6 -#define EXC_DBE 7 -#define EXC_SYS 8 -#define EXC_BPT 9 -#define EXC_RI 10 -#define EXC_CU 11 -#define EXC_OV 12 -#define EXC_TR 13 -#define EXC_WATCH 23 -#define EXC_MCHK 24 - - -/* - * Bits in the cp0 config register. - */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_SE (_ULCAST_(1) << 12) -#ifndef CONF_BE /* duplicate in mipsregs.h */ -#define CONF_BE (_ULCAST_(1) << 15) -#endif -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_AC (_ULCAST_(1) << 23) -#define CONF_HALT (_ULCAST_(1) << 25) -#ifndef CONF_M /* duplicate in mipsregs.h */ -#define CONF_M (_ULCAST_(1) << 31) -#endif - - -/* - * Bits in the cp0 config register select 1. - */ -#define CONF1_FP 0x00000001 /* FPU present */ -#define CONF1_EP 0x00000002 /* EJTAG present */ -#define CONF1_CA 0x00000004 /* mips16 implemented */ -#define CONF1_WR 0x00000008 /* Watch registers present */ -#define CONF1_PC 0x00000010 /* Performance counters present */ -#define CONF1_DA_SHIFT 7 /* D$ associativity */ -#define CONF1_DA_MASK 0x00000380 -#define CONF1_DA_BASE 1 -#define CONF1_DL_SHIFT 10 /* D$ line size */ -#define CONF1_DL_MASK 0x00001c00 -#define CONF1_DL_BASE 2 -#define CONF1_DS_SHIFT 13 /* D$ sets/way */ -#define CONF1_DS_MASK 0x0000e000 -#define CONF1_DS_BASE 64 -#define CONF1_IA_SHIFT 16 /* I$ associativity */ -#define CONF1_IA_MASK 0x00070000 -#define CONF1_IA_BASE 1 -#define CONF1_IL_SHIFT 19 /* I$ line size */ -#define CONF1_IL_MASK 0x00380000 -#define CONF1_IL_BASE 2 -#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ -#define CONF1_IS_MASK 0x01c00000 -#define CONF1_IS_BASE 64 -#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */ -#define CONF1_MS_SHIFT 25 - -/* PRID register */ -#define PRID_COPT_MASK 0xff000000 -#define PRID_COMP_MASK 0x00ff0000 -#define PRID_IMP_MASK 0x0000ff00 -#define PRID_REV_MASK 0x000000ff - -#define PRID_COMP_LEGACY 0x000000 -#define PRID_COMP_MIPS 0x010000 -#define PRID_COMP_BROADCOM 0x020000 -#define PRID_COMP_ALCHEMY 0x030000 -#define PRID_COMP_SIBYTE 0x040000 -#define PRID_IMP_BCM4710 0x4000 -#define PRID_IMP_BCM3302 0x9000 -#define PRID_IMP_BCM3303 0x9100 - -#define PRID_IMP_UNKNOWN 0xff00 - -#define BCM330X(id) \ - (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \ - (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \ - ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \ - (PRID_COMP_BROADCOM | PRID_IMP_BCM3303))) - -/* Bits in C0_BROADCOM */ -#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */ -#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */ -#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */ -#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */ -#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */ - -/* PreFetch Cache aka Read Ahead Cache */ - -#define PFC_CR0 0xff400000 /* control reg 0 */ -#define PFC_CR1 0xff400004 /* control reg 1 */ - -/* PFC operations */ -#define PFC_I 0x00000001 /* Enable PFC use for instructions */ -#define PFC_D 0x00000002 /* Enable PFC use for data */ -#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */ -#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */ -#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */ -#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */ -#define PFC_DPF 0x00000040 /* Enable directional prefetching */ -#define PFC_FLUSH 0x00000100 /* Flush the PFC */ -#define PFC_BRR 0x40000000 /* Bus error indication */ -#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */ - -/* Handy defaults */ -#define PFC_DISABLED 0 -#define PFC_AUTO 0xffffffff /* auto select the default mode */ -#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV) -#define PFC_INST_NOPF (PFC_I | PFC_CINV) -#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV) -#define PFC_DATA_NOPF (PFC_D | PFC_CINV) -#define PFC_I_AND_D (PFC_INST | PFC_DATA) -#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF) - -#ifndef _LANGUAGE_ASSEMBLY - -/* - * Macros to access the system control coprocessor - */ - -#define MFC0(source, sel) \ -({ \ - int __res; \ - __asm__ __volatile__(" \ - .set\tnoreorder; \ - .set\tnoat; \ - .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \ - move\t%0, $1; \ - .set\tat; \ - .set\treorder" \ - :"=r" (__res) \ - : \ - :"$1"); \ - __res; \ -}) - -#define MTC0(source, sel, value) \ -do { \ - __asm__ __volatile__(" \ - .set\tnoreorder; \ - .set\tnoat; \ - move\t$1, %z0; \ - .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \ - .set\tat; \ - .set\treorder" \ - : \ - :"jr" (value) \ - :"$1"); \ -} while (0) - -#define get_c0_count() \ -({ \ - int __res; \ - __asm__ __volatile__(" \ - .set\tnoreorder; \ - .set\tnoat; \ - mfc0\t%0, $9; \ - .set\tat; \ - .set\treorder" \ - :"=r" (__res)); \ - __res; \ -}) - -static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize) -{ - uint lsz, sets, ways; - - /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */ - if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT))) - lsz = CONF1_IL_BASE << lsz; - sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT); - ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT); - *size = lsz * sets * ways; - *lsize = lsz; -} - -static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize) -{ - uint lsz, sets, ways; - - /* Data Cache Size = Associativity * Line Size * Sets Per Way */ - if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT))) - lsz = CONF1_DL_BASE << lsz; - sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT); - ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT); - *size = lsz * sets * ways; - *lsize = lsz; -} - -#define cache_op(base, op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -#define cache_unroll4(base, delta, op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0(%0); \ - cache %1, delta(%0); \ - cache %1, (2 * delta)(%0); \ - cache %1, (3 * delta)(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -#endif /* !_LANGUAGE_ASSEMBLY */ - -#endif /* _MISPINC_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h deleted file mode 100644 index fddd1983e8..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/osl.h +++ /dev/null @@ -1,221 +0,0 @@ -#ifndef __osl_h -#define __osl_h - -#include <linux/delay.h> -#include <typedefs.h> -#include <linuxver.h> -#include <pcicfg.h> - -#define ASSERT(n) - -#ifndef ABS -#define ABS(a) (((a) < 0)?-(a):(a)) -#endif /* ABS */ - -#ifndef MIN -#define MIN(a, b) (((a) < (b))?(a):(b)) -#endif /* MIN */ - -#ifndef MAX -#define MAX(a, b) (((a) > (b))?(a):(b)) -#endif /* MAX */ - -#define CEIL(x, y) (((x) + ((y)-1)) / (y)) -#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) -#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0) -#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0) -#define VALID_MASK(mask) !((mask) & ((mask) + 1)) -#ifndef OFFSETOF -#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member) -#endif /* OFFSETOF */ -#ifndef ARRAYSIZE -#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0])) -#endif - -/* - * Spin at most 'us' microseconds while 'exp' is true. - * Caller should explicitly test 'exp' when this completes - * and take appropriate error action if 'exp' is still true. - */ -#define SPINWAIT(exp, us) { \ - uint countdown = (us) + 9; \ - while ((exp) && (countdown >= 10)) {\ - OSL_DELAY(10); \ - countdown -= 10; \ - } \ -} - - -typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status); -/* Pkttag flag should be part of public information */ -typedef struct { - bool pkttag; - uint pktalloced; /* Number of allocated packet buffers */ - bool mmbus; /* Bus supports memory-mapped register accesses */ - pktfree_cb_fn_t tx_fn; /* Callback function for PKTFREE */ - void *tx_ctx; /* Context to the callback function */ -} osl_pubinfo_t; - -struct osl_info { - osl_pubinfo_t pub; - uint magic; - void *pdev; - uint malloced; - uint failed; - uint bustype; - void *dbgmem_list; -}; - -typedef struct osl_info osl_t; - -#define PCI_CFG_RETRY 10 - -/* map/unmap direction */ -#define DMA_TX 1 /* TX direction for DMA */ -#define DMA_RX 2 /* RX direction for DMA */ - -#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v)) -#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v)) -#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val))) - -/* bcopy, bcmp, and bzero */ -#define bcopy(src, dst, len) memcpy((dst), (src), (len)) -#define bcmp(b1, b2, len) memcmp((b1), (b2), (len)) -#define bzero(b, len) memset((b), '\0', (len)) - -/* uncached virtual address */ -#ifdef mips -#define OSL_UNCACHED(va) KSEG1ADDR((va)) -#include <asm/addrspace.h> -#else -#define OSL_UNCACHED(va) (va) -#endif /* mips */ - - -#ifndef IL_BIGENDIAN -#define R_REG(osh, r) (\ - sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \ - sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \ - readl((volatile uint32*)(r)) \ -) -#define W_REG(osh, r, v) do { \ - switch (sizeof(*(r))) { \ - case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \ - case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \ - case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \ - } \ -} while (0) -#else /* IL_BIGENDIAN */ -#define R_REG(osh, r) ({ \ - __typeof(*(r)) __osl_v; \ - switch (sizeof(*(r))) { \ - case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \ - case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \ - case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \ - } \ - __osl_v; \ -}) -#define W_REG(osh, r, v) do { \ - switch (sizeof(*(r))) { \ - case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \ - case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \ - case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \ - } \ -} while (0) -#endif /* IL_BIGENDIAN */ - -/* dereference an address that may cause a bus exception */ -#define BUSPROBE(val, addr) get_dbe((val), (addr)) -#include <asm/paccess.h> - -/* map/unmap physical to virtual I/O */ -#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size)) -#define REG_UNMAP(va) iounmap((void *)(va)) - -/* shared (dma-able) memory access macros */ -#define R_SM(r) *(r) -#define W_SM(r, v) (*(r) = (v)) -#define BZERO_SM(r, len) memset((r), '\0', (len)) - -#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC) -#define MFREE(osh, addr, size) kfree((addr)) -#define MALLOCED(osh) (0) - -#define OSL_DELAY _osl_delay -static inline void _osl_delay(uint usec) -{ - uint d; - - while (usec > 0) { - d = MIN(usec, 1000); - udelay(d); - usec -= d; - } -} - -static inline void -bcm_mdelay(uint ms) -{ - uint i; - - for (i = 0; i < ms; i++) { - OSL_DELAY(1000); - } -} - - -#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) -#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) - -#define OSL_PCI_READ_CONFIG(osh, offset, size) \ - _osl_pci_read_config((osh), (offset), (size)) - -static inline uint32 -_osl_pci_read_config(osl_t *osh, uint offset, uint size) -{ - uint val; - uint retry = PCI_CFG_RETRY; - - do { - pci_read_config_dword(osh->pdev, offset, &val); - if (val != 0xffffffff) - break; - } while (retry--); - - return (val); -} - -#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \ - _osl_pci_write_config((osh), (offset), (size), (val)) -static inline void -_osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val) -{ - uint retry = PCI_CFG_RETRY; - - do { - pci_write_config_dword(osh->pdev, offset, val); - if (offset != PCI_BAR0_WIN) - break; - if (_osl_pci_read_config(osh, offset, size) == val) - break; - } while (retry--); -} - - -/* return bus # for the pci device pointed by osh->pdev */ -#define OSL_PCI_BUS(osh) _osl_pci_bus(osh) -static inline uint -_osl_pci_bus(osl_t *osh) -{ - return ((struct pci_dev *)osh->pdev)->bus->number; -} - -/* return slot # for the pci device pointed by osh->pdev */ -#define OSL_PCI_SLOT(osh) _osl_pci_slot(osh) -static inline uint -_osl_pci_slot(osl_t *osh) -{ - return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn); -} - -#endif diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h deleted file mode 100644 index 25140e622c..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h +++ /dev/null @@ -1,507 +0,0 @@ -/* - * pcicfg.h: PCI configuration constants and structures. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _h_pcicfg_ -#define _h_pcicfg_ - -/* The following inside ifndef's so we don't collide with NTDDK.H */ -#ifndef PCI_MAX_BUS -#define PCI_MAX_BUS 0x100 -#endif -#ifndef PCI_MAX_DEVICES -#define PCI_MAX_DEVICES 0x20 -#endif -#ifndef PCI_MAX_FUNCTION -#define PCI_MAX_FUNCTION 0x8 -#endif - -#ifndef PCI_INVALID_VENDORID -#define PCI_INVALID_VENDORID 0xffff -#endif -#ifndef PCI_INVALID_DEVICEID -#define PCI_INVALID_DEVICEID 0xffff -#endif - - -/* Convert between bus-slot-function-register and config addresses */ - -#define PCICFG_BUS_SHIFT 16 /* Bus shift */ -#define PCICFG_SLOT_SHIFT 11 /* Slot shift */ -#define PCICFG_FUN_SHIFT 8 /* Function shift */ -#define PCICFG_OFF_SHIFT 0 /* Register shift */ - -#define PCICFG_BUS_MASK 0xff /* Bus mask */ -#define PCICFG_SLOT_MASK 0x1f /* Slot mask */ -#define PCICFG_FUN_MASK 7 /* Function mask */ -#define PCICFG_OFF_MASK 0xff /* Bus mask */ - -#define PCI_CONFIG_ADDR(b, s, f, o) \ - ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \ - | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \ - | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \ - | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT)) - -#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK) -#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK) -#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK) -#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK) - -/* PCIE Config space accessing MACROS */ - -#define PCIECFG_BUS_SHIFT 24 /* Bus shift */ -#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */ -#define PCIECFG_FUN_SHIFT 16 /* Function shift */ -#define PCIECFG_OFF_SHIFT 0 /* Register shift */ - -#define PCIECFG_BUS_MASK 0xff /* Bus mask */ -#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */ -#define PCIECFG_FUN_MASK 7 /* Function mask */ -#define PCIECFG_OFF_MASK 0x3ff /* Register mask */ - -#define PCIE_CONFIG_ADDR(b, s, f, o) \ - ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \ - | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \ - | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \ - | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT)) - -#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK) -#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK) -#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK) -#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK) - -/* The actual config space */ - -#define PCI_BAR_MAX 6 - -#define PCI_ROM_BAR 8 - -#define PCR_RSVDA_MAX 2 - -/* Bits in PCI bars' flags */ - -#define PCIBAR_FLAGS 0xf -#define PCIBAR_IO 0x1 -#define PCIBAR_MEM1M 0x2 -#define PCIBAR_MEM64 0x4 -#define PCIBAR_PREFETCH 0x8 -#define PCIBAR_MEM32_MASK 0xFFFFFF80 - -/* pci config status reg has a bit to indicate that capability ptr is present */ - -#define PCI_CAPPTR_PRESENT 0x0010 - -typedef struct _pci_config_regs { - unsigned short vendor; - unsigned short device; - unsigned short command; - unsigned short status; - unsigned char rev_id; - unsigned char prog_if; - unsigned char sub_class; - unsigned char base_class; - unsigned char cache_line_size; - unsigned char latency_timer; - unsigned char header_type; - unsigned char bist; - unsigned long base[PCI_BAR_MAX]; - unsigned long cardbus_cis; - unsigned short subsys_vendor; - unsigned short subsys_id; - unsigned long baserom; - unsigned long rsvd_a[PCR_RSVDA_MAX]; - unsigned char int_line; - unsigned char int_pin; - unsigned char min_gnt; - unsigned char max_lat; - unsigned char dev_dep[192]; -} pci_config_regs; - -#define SZPCR (sizeof (pci_config_regs)) -#define MINSZPCR 64 /* offsetof (dev_dep[0] */ - -/* A structure for the config registers is nice, but in most - * systems the config space is not memory mapped, so we need - * filed offsetts. :-( - */ -#define PCI_CFG_VID 0 -#define PCI_CFG_DID 2 -#define PCI_CFG_CMD 4 -#define PCI_CFG_STAT 6 -#define PCI_CFG_REV 8 -#define PCI_CFG_PROGIF 9 -#define PCI_CFG_SUBCL 0xa -#define PCI_CFG_BASECL 0xb -#define PCI_CFG_CLSZ 0xc -#define PCI_CFG_LATTIM 0xd -#define PCI_CFG_HDR 0xe -#define PCI_CFG_BIST 0xf -#define PCI_CFG_BAR0 0x10 -#define PCI_CFG_BAR1 0x14 -#define PCI_CFG_BAR2 0x18 -#define PCI_CFG_BAR3 0x1c -#define PCI_CFG_BAR4 0x20 -#define PCI_CFG_BAR5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SVID 0x2c -#define PCI_CFG_SSID 0x2e -#define PCI_CFG_ROMBAR 0x30 -#define PCI_CFG_CAPPTR 0x34 -#define PCI_CFG_INT 0x3c -#define PCI_CFG_PIN 0x3d -#define PCI_CFG_MINGNT 0x3e -#define PCI_CFG_MAXLAT 0x3f - -#ifdef __NetBSD__ -#undef PCI_CLASS_DISPLAY -#undef PCI_CLASS_MEMORY -#undef PCI_CLASS_BRIDGE -#undef PCI_CLASS_INPUT -#undef PCI_CLASS_DOCK -#endif /* __NetBSD__ */ - -#ifdef EFI -#undef PCI_CLASS_BRIDGE -#undef PCI_CLASS_OLD -#undef PCI_CLASS_DISPLAY -#undef PCI_CLASS_SERIAL -#undef PCI_CLASS_SATELLITE -#endif /* EFI */ - -/* Classes and subclasses */ - -typedef enum { - PCI_CLASS_OLD = 0, - PCI_CLASS_DASDI, - PCI_CLASS_NET, - PCI_CLASS_DISPLAY, - PCI_CLASS_MMEDIA, - PCI_CLASS_MEMORY, - PCI_CLASS_BRIDGE, - PCI_CLASS_COMM, - PCI_CLASS_BASE, - PCI_CLASS_INPUT, - PCI_CLASS_DOCK, - PCI_CLASS_CPU, - PCI_CLASS_SERIAL, - PCI_CLASS_INTELLIGENT = 0xe, - PCI_CLASS_SATELLITE, - PCI_CLASS_CRYPT, - PCI_CLASS_DSP, - PCI_CLASS_XOR = 0xfe -} pci_classes; - -typedef enum { - PCI_DASDI_SCSI, - PCI_DASDI_IDE, - PCI_DASDI_FLOPPY, - PCI_DASDI_IPI, - PCI_DASDI_RAID, - PCI_DASDI_OTHER = 0x80 -} pci_dasdi_subclasses; - -typedef enum { - PCI_NET_ETHER, - PCI_NET_TOKEN, - PCI_NET_FDDI, - PCI_NET_ATM, - PCI_NET_OTHER = 0x80 -} pci_net_subclasses; - -typedef enum { - PCI_DISPLAY_VGA, - PCI_DISPLAY_XGA, - PCI_DISPLAY_3D, - PCI_DISPLAY_OTHER = 0x80 -} pci_display_subclasses; - -typedef enum { - PCI_MMEDIA_VIDEO, - PCI_MMEDIA_AUDIO, - PCI_MMEDIA_PHONE, - PCI_MEDIA_OTHER = 0x80 -} pci_mmedia_subclasses; - -typedef enum { - PCI_MEMORY_RAM, - PCI_MEMORY_FLASH, - PCI_MEMORY_OTHER = 0x80 -} pci_memory_subclasses; - -typedef enum { - PCI_BRIDGE_HOST, - PCI_BRIDGE_ISA, - PCI_BRIDGE_EISA, - PCI_BRIDGE_MC, - PCI_BRIDGE_PCI, - PCI_BRIDGE_PCMCIA, - PCI_BRIDGE_NUBUS, - PCI_BRIDGE_CARDBUS, - PCI_BRIDGE_RACEWAY, - PCI_BRIDGE_OTHER = 0x80 -} pci_bridge_subclasses; - -typedef enum { - PCI_COMM_UART, - PCI_COMM_PARALLEL, - PCI_COMM_MULTIUART, - PCI_COMM_MODEM, - PCI_COMM_OTHER = 0x80 -} pci_comm_subclasses; - -typedef enum { - PCI_BASE_PIC, - PCI_BASE_DMA, - PCI_BASE_TIMER, - PCI_BASE_RTC, - PCI_BASE_PCI_HOTPLUG, - PCI_BASE_OTHER = 0x80 -} pci_base_subclasses; - -typedef enum { - PCI_INPUT_KBD, - PCI_INPUT_PEN, - PCI_INPUT_MOUSE, - PCI_INPUT_SCANNER, - PCI_INPUT_GAMEPORT, - PCI_INPUT_OTHER = 0x80 -} pci_input_subclasses; - -typedef enum { - PCI_DOCK_GENERIC, - PCI_DOCK_OTHER = 0x80 -} pci_dock_subclasses; - -typedef enum { - PCI_CPU_386, - PCI_CPU_486, - PCI_CPU_PENTIUM, - PCI_CPU_ALPHA = 0x10, - PCI_CPU_POWERPC = 0x20, - PCI_CPU_MIPS = 0x30, - PCI_CPU_COPROC = 0x40, - PCI_CPU_OTHER = 0x80 -} pci_cpu_subclasses; - -typedef enum { - PCI_SERIAL_IEEE1394, - PCI_SERIAL_ACCESS, - PCI_SERIAL_SSA, - PCI_SERIAL_USB, - PCI_SERIAL_FIBER, - PCI_SERIAL_SMBUS, - PCI_SERIAL_OTHER = 0x80 -} pci_serial_subclasses; - -typedef enum { - PCI_INTELLIGENT_I2O -} pci_intelligent_subclasses; - -typedef enum { - PCI_SATELLITE_TV, - PCI_SATELLITE_AUDIO, - PCI_SATELLITE_VOICE, - PCI_SATELLITE_DATA, - PCI_SATELLITE_OTHER = 0x80 -} pci_satellite_subclasses; - -typedef enum { - PCI_CRYPT_NETWORK, - PCI_CRYPT_ENTERTAINMENT, - PCI_CRYPT_OTHER = 0x80 -} pci_crypt_subclasses; - -typedef enum { - PCI_DSP_DPIO, - PCI_DSP_OTHER = 0x80 -} pci_dsp_subclasses; - -typedef enum { - PCI_XOR_QDMA, - PCI_XOR_OTHER = 0x80 -} pci_xor_subclasses; - -/* Header types */ -typedef enum { - PCI_HEADER_NORMAL, - PCI_HEADER_BRIDGE, - PCI_HEADER_CARDBUS -} pci_header_types; - - -/* Overlay for a PCI-to-PCI bridge */ - -#define PPB_RSVDA_MAX 2 -#define PPB_RSVDD_MAX 8 - -typedef struct _ppb_config_regs { - unsigned short vendor; - unsigned short device; - unsigned short command; - unsigned short status; - unsigned char rev_id; - unsigned char prog_if; - unsigned char sub_class; - unsigned char base_class; - unsigned char cache_line_size; - unsigned char latency_timer; - unsigned char header_type; - unsigned char bist; - unsigned long rsvd_a[PPB_RSVDA_MAX]; - unsigned char prim_bus; - unsigned char sec_bus; - unsigned char sub_bus; - unsigned char sec_lat; - unsigned char io_base; - unsigned char io_lim; - unsigned short sec_status; - unsigned short mem_base; - unsigned short mem_lim; - unsigned short pf_mem_base; - unsigned short pf_mem_lim; - unsigned long pf_mem_base_hi; - unsigned long pf_mem_lim_hi; - unsigned short io_base_hi; - unsigned short io_lim_hi; - unsigned short subsys_vendor; - unsigned short subsys_id; - unsigned long rsvd_b; - unsigned char rsvd_c; - unsigned char int_pin; - unsigned short bridge_ctrl; - unsigned char chip_ctrl; - unsigned char diag_ctrl; - unsigned short arb_ctrl; - unsigned long rsvd_d[PPB_RSVDD_MAX]; - unsigned char dev_dep[192]; -} ppb_config_regs; - - -/* PCI CAPABILITY DEFINES */ -#define PCI_CAP_POWERMGMTCAP_ID 0x01 -#define PCI_CAP_MSICAP_ID 0x05 -#define PCI_CAP_PCIECAP_ID 0x10 - -/* Data structure to define the Message Signalled Interrupt facility - * Valid for PCI and PCIE configurations - */ -typedef struct _pciconfig_cap_msi { - unsigned char capID; - unsigned char nextptr; - unsigned short msgctrl; - unsigned int msgaddr; -} pciconfig_cap_msi; - -/* Data structure to define the Power managment facility - * Valid for PCI and PCIE configurations - */ -typedef struct _pciconfig_cap_pwrmgmt { - unsigned char capID; - unsigned char nextptr; - unsigned short pme_cap; - unsigned short pme_sts_ctrl; - unsigned char pme_bridge_ext; - unsigned char data; -} pciconfig_cap_pwrmgmt; - -#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ -#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ -#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ -#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ - -/* Data structure to define the PCIE capability */ -typedef struct _pciconfig_cap_pcie { - unsigned char capID; - unsigned char nextptr; - unsigned short pcie_cap; - unsigned int dev_cap; - unsigned short dev_ctrl; - unsigned short dev_status; - unsigned int link_cap; - unsigned short link_ctrl; - unsigned short link_status; -} pciconfig_cap_pcie; - -/* PCIE Enhanced CAPABILITY DEFINES */ -#define PCIE_EXTCFG_OFFSET 0x100 -#define PCIE_ADVERRREP_CAPID 0x0001 -#define PCIE_VC_CAPID 0x0002 -#define PCIE_DEVSNUM_CAPID 0x0003 -#define PCIE_PWRBUDGET_CAPID 0x0004 - -/* Header to define the PCIE specific capabilities in the extended config space */ -typedef struct _pcie_enhanced_caphdr { - unsigned short capID; - unsigned short cap_ver : 4; - unsigned short next_ptr : 12; -} pcie_enhanced_caphdr; - - -/* Everything below is BRCM HND proprietary */ - - -/* Brcm PCI configuration registers */ -#define cap_list rsvd_a[0] -#define bar0_window dev_dep[0x80 - 0x40] -#define bar1_window dev_dep[0x84 - 0x40] -#define sprom_control dev_dep[0x88 - 0x40] - -#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ -#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ -#define PCI_SPROM_CONTROL 0x88 /* sprom property control */ -#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ -#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ -#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ -#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ -#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */ -#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */ -#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ -#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ -#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ - -#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ -#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ -#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ -#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the - * 8KB window, so their address is the "regular" - * address plus 4K - */ -#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ - -/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ -#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ -#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ -#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ - -/* PCI_INT_STATUS */ -#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ - -/* PCI_INT_MASK */ -#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ -#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ -#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ - -/* PCI_SPROM_CONTROL */ -#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ -#define SPROM_LOCKED 0x08 /* SPROM Locked */ -#define SPROM_BLANK 0x04 /* indicating a blank SPROM */ -#define SPROM_WRITEEN 0x10 /* SPROM write enable */ -#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ -#define SPROM_OTPIN_USE 0x80 /* device OTP In use */ - -#define SPROM_SIZE 256 /* sprom size in 16-bit */ -#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */ - -/* PCI_CFG_CMD_STAT */ -#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */ - -#endif /* _h_pcicfg_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h deleted file mode 100644 index 1be060870e..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbchipc.h +++ /dev/null @@ -1,856 +0,0 @@ -/* - * SiliconBackplane Chipcommon core hardware definitions. - * - * The chipcommon core provides chip identification, SB control, - * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, - * gpio interface, extbus, and support for serial and parallel flashes. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBCHIPC_H -#define _SBCHIPC_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - - -typedef volatile struct { - uint32 chipid; /* 0x0 */ - uint32 capabilities; - uint32 corecontrol; /* corerev >= 1 */ - uint32 bist; - - /* OTP */ - uint32 otpstatus; /* 0x10, corerev >= 10 */ - uint32 otpcontrol; - uint32 otpprog; - uint32 PAD; - - /* Interrupt control */ - uint32 intstatus; /* 0x20 */ - uint32 intmask; - uint32 chipcontrol; /* 0x28, rev >= 11 */ - uint32 chipstatus; /* 0x2c, rev >= 11 */ - - /* Jtag Master */ - uint32 jtagcmd; /* 0x30, rev >= 10 */ - uint32 jtagir; - uint32 jtagdr; - uint32 jtagctrl; - - /* serial flash interface registers */ - uint32 flashcontrol; /* 0x40 */ - uint32 flashaddress; - uint32 flashdata; - uint32 PAD[1]; - - /* Silicon backplane configuration broadcast control */ - uint32 broadcastaddress; /* 0x50 */ - uint32 broadcastdata; - - /* gpio - cleared only by power-on-reset */ - uint32 gpiopullup; /* 0x58, corerev >= 20 */ - uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ - uint32 gpioin; /* 0x60 */ - uint32 gpioout; - uint32 gpioouten; - uint32 gpiocontrol; - uint32 gpiointpolarity; - uint32 gpiointmask; - - /* GPIO events corerev >= 11 */ - uint32 gpioevent; - uint32 gpioeventintmask; - - /* Watchdog timer */ - uint32 watchdog; /* 0x80 */ - - /* GPIO events corerev >= 11 */ - uint32 gpioeventintpolarity; - - /* GPIO based LED powersave registers corerev >= 16 */ - uint32 gpiotimerval; /* 0x88 */ - uint32 gpiotimeroutmask; - - /* clock control */ - uint32 clockcontrol_n; /* 0x90 */ - uint32 clockcontrol_sb; /* aka m0 */ - uint32 clockcontrol_pci; /* aka m1 */ - uint32 clockcontrol_m2; /* mii/uart/mipsref */ - uint32 clockcontrol_m3; /* cpu */ - uint32 clkdiv; /* corerev >= 3 */ - uint32 PAD[2]; - - /* pll delay registers (corerev >= 4) */ - uint32 pll_on_delay; /* 0xb0 */ - uint32 fref_sel_delay; - uint32 slow_clk_ctl; /* 5 < corerev < 10 */ - uint32 PAD[1]; - - /* Instaclock registers (corerev >= 10) */ - uint32 system_clk_ctl; /* 0xc0 */ - uint32 clkstatestretch; - uint32 PAD[14]; - - /* ExtBus control registers (corerev >= 3) */ - uint32 pcmcia_config; /* 0x100 */ - uint32 pcmcia_memwait; - uint32 pcmcia_attrwait; - uint32 pcmcia_iowait; - uint32 ide_config; - uint32 ide_memwait; - uint32 ide_attrwait; - uint32 ide_iowait; - uint32 prog_config; - uint32 prog_waitcount; - uint32 flash_config; - uint32 flash_waitcount; - uint32 PAD[4]; - - /* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */ - uint32 eci_output; /* 0x140 */ - uint32 eci_control; - uint32 eci_inputlo; - uint32 eci_inputmi; - uint32 eci_inputhi; - uint32 eci_inputintpolaritylo; - uint32 eci_inputintpolaritymi; - uint32 eci_inputintpolarityhi; - uint32 eci_intmasklo; - uint32 eci_intmaskmi; - uint32 eci_intmaskhi; - uint32 eci_eventlo; - uint32 eci_eventmi; - uint32 eci_eventhi; - uint32 eci_eventmasklo; - uint32 eci_eventmaskmi; - uint32 eci_eventmaskhi; - uint32 PAD[23]; - - - /* Clock control and hardware workarounds (corerev >= 20) */ - uint32 clk_ctl_st; /* 0x1e0 */ - uint32 hw_war; - uint32 PAD[70]; - - /* uarts */ - uint8 uart0data; /* 0x300 */ - uint8 uart0imr; - uint8 uart0fcr; - uint8 uart0lcr; - uint8 uart0mcr; - uint8 uart0lsr; - uint8 uart0msr; - uint8 uart0scratch; - uint8 PAD[248]; /* corerev >= 1 */ - - uint8 uart1data; /* 0x400 */ - uint8 uart1imr; - uint8 uart1fcr; - uint8 uart1lcr; - uint8 uart1mcr; - uint8 uart1lsr; - uint8 uart1msr; - uint8 uart1scratch; - uint32 PAD[126]; - - /* PMU registers (corerev >= 20) */ - uint32 pmucontrol; /* 0x600 */ - uint32 pmucapabilities; - uint32 pmustatus; - uint32 res_state; - uint32 res_pending; - uint32 pmutimer; - uint32 min_res_mask; - uint32 max_res_mask; - uint32 res_table_sel; - uint32 res_dep_mask; - uint32 res_updn_timer; - uint32 res_timer; - uint32 clkstretch; - uint32 pmuwatchdog; - uint32 PAD[2]; - uint32 res_req_timer_sel; - uint32 res_req_timer; - uint32 res_req_mask; - uint32 PAD; - uint32 chipcontrol_addr; - uint32 chipcontrol_data; - uint32 regcontrol_addr; - uint32 regcontrol_data; - uint32 pllcontrol_addr; - uint32 pllcontrol_data; - uint32 PAD[102]; - uint16 otp[512]; -} chipcregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* corecontrol */ -#define CC_UE (1 << 0) /* uart enable */ - -#define CC_CHIPID 0 -#define CC_CAPABILITIES 4 -#define CC_OTPST 0x10 -#define CC_CHIPST 0x2c -#define CC_JTAGCMD 0x30 -#define CC_JTAGIR 0x34 -#define CC_JTAGDR 0x38 -#define CC_JTAGCTRL 0x3c -#define CC_WATCHDOG 0x80 -#define CC_CLKC_N 0x90 -#define CC_CLKC_M0 0x94 -#define CC_CLKC_M1 0x98 -#define CC_CLKC_M2 0x9c -#define CC_CLKC_M3 0xa0 -#define CC_CLKDIV 0xa4 -#define CC_SYS_CLK_CTL 0xc0 -#define CC_CLK_CTL_ST SB_CLK_CTL_ST -#define PMU_CTL 0x600 -#define PMU_CAP 0x604 -#define PMU_ST 0x608 -#define PMU_TIMER 0x614 -#define PMU_MIN_RES_MASK 0x618 -#define PMU_MAX_RES_MASK 0x61c -#define PMU_REG_CONTROL_ADDR 0x658 -#define PMU_REG_CONTROL_DATA 0x65C -#define PMU_PLL_CONTROL_ADDR 0x660 -#define PMU_PLL_CONTROL_DATA 0x664 -#define CC_OTP 0x800 /* OTP address space */ - -/* chipid */ -#define CID_ID_MASK 0x0000ffff /* Chip Id mask */ -#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */ -#define CID_REV_SHIFT 16 /* Chip Revision shift */ -#define CID_PKG_MASK 0x00f00000 /* Package Option mask */ -#define CID_PKG_SHIFT 20 /* Package Option shift */ -#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */ -#define CID_CC_SHIFT 24 - -/* capabilities */ -#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */ -#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ -#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ -#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */ -#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */ -#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ -#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ -#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ -#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ -#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ -#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ -#define CC_CAP_PWR_CTL 0x00040000 /* Power control */ -#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */ -#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */ -#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */ -#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ -#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */ -#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ -#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ -#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */ - -/* PLL type */ -#define PLL_NONE 0x00000000 -#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */ -#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */ -#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */ -#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */ -#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */ -#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ -#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */ - -/* ALP clock on pre-PMU chips */ -#define ALP_CLOCK 20000000 - -/* HT clock */ -#define HT_CLOCK 80000000 - -/* watchdog clock */ -#define WATCHDOG_CLOCK_5354 32000 /* Hz */ - -/* corecontrol */ -#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ -#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ -#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ - -/* chipcontrol */ -#define CHIPCTRL_4321A0_DEFAULT 0x3a4 -#define CHIPCTRL_4321A1_DEFAULT 0x0a4 - -/* Fields in the otpstatus register in rev >= 21 */ -#define OTPS_OL_MASK 0x000000ff -#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */ -#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ -#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ -#define OTPS_OL_GU 0x00000008 /* general use region is locked */ -#define OTPS_GUP_MASK 0x00000f00 -#define OTPS_GUP_SHIFT 8 -#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ -#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ -#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ -#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ -#define OTPS_READY 0x00001000 -#define OTPS_RV(x) (1 << (16 + (x))) - -/* Fields in the otpcontrol register in rev >= 21 */ -#define OTPC_PROGSEL 0x00000001 -#define OTPC_PCOUNT_MASK 0x0000000e -#define OTPC_PCOUNT_SHIFT 1 -#define OTPC_VSEL_MASK 0x000000f0 -#define OTPC_VSEL_SHIFT 4 -#define OTPC_TMM_MASK 0x00000700 -#define OTPC_TMM_SHIFT 8 -#define OTPC_ODM 0x00000800 -#define OTPC_PROGEN 0x80000000 - -/* Fields in otpprog in rev >= 21 */ -#define OTPP_COL_MASK 0x000000ff -#define OTPP_COL_SHIFT 0 -#define OTPP_ROW_MASK 0x0000ff00 -#define OTPP_ROW_SHIFT 8 -#define OTPP_OC_MASK 0x0f000000 -#define OTPP_OC_SHIFT 24 -#define OTPP_READERR 0x10000000 -#define OTPP_VALUE_MASK 0x20000000 -#define OTPP_VALUE_SHIFT 29 -#define OTPP_START_BUSY 0x80000000 - -/* Opcodes for OTPP_OC field */ -#define OTPPOC_READ 0 -#define OTPPOC_BIT_PROG 1 -#define OTPPOC_VERIFY 3 -#define OTPPOC_INIT 4 -#define OTPPOC_SET 5 -#define OTPPOC_RESET 6 -#define OTPPOC_OCST 7 -#define OTPPOC_ROW_LOCK 8 -#define OTPPOC_PRESCN_TEST 9 - -/* jtagcmd */ -#define JCMD_START 0x80000000 -#define JCMD_BUSY 0x80000000 -#define JCMD_PAUSE 0x40000000 -#define JCMD0_ACC_MASK 0x0000f000 -#define JCMD0_ACC_IRDR 0x00000000 -#define JCMD0_ACC_DR 0x00001000 -#define JCMD0_ACC_IR 0x00002000 -#define JCMD0_ACC_RESET 0x00003000 -#define JCMD0_ACC_IRPDR 0x00004000 -#define JCMD0_ACC_PDR 0x00005000 -#define JCMD0_IRW_MASK 0x00000f00 -#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ -#define JCMD_ACC_IRDR 0x00000000 -#define JCMD_ACC_DR 0x00010000 -#define JCMD_ACC_IR 0x00020000 -#define JCMD_ACC_RESET 0x00030000 -#define JCMD_ACC_IRPDR 0x00040000 -#define JCMD_ACC_PDR 0x00050000 -#define JCMD_IRW_MASK 0x00001f00 -#define JCMD_IRW_SHIFT 8 -#define JCMD_DRW_MASK 0x0000003f - -/* jtagctrl */ -#define JCTRL_FORCE_CLK 4 /* Force clock */ -#define JCTRL_EXT_EN 2 /* Enable external targets */ -#define JCTRL_EN 1 /* Enable Jtag master */ - -/* Fields in clkdiv */ -#define CLKD_SFLASH 0x0f000000 -#define CLKD_SFLASH_SHIFT 24 -#define CLKD_OTP 0x000f0000 -#define CLKD_OTP_SHIFT 16 -#define CLKD_JTAG 0x00000f00 -#define CLKD_JTAG_SHIFT 8 -#define CLKD_UART 0x000000ff - -/* intstatus/intmask */ -#define CI_GPIO 0x00000001 /* gpio intr */ -#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */ -#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ -#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ -#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */ -#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ -#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */ -#define CI_WDRESET 0x80000000 /* watchdog reset occurred */ - -/* slow_clk_ctl */ -#define SCC_SS_MASK 0x00000007 /* slow clock source mask */ -#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ -#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ -#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ -#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ -#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, - * 0: LPO is enabled - */ -#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, - * 0: power logic control - */ -#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors - * PLL clock disable requests from core - */ -#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't - * disable crystal when appropriate - */ -#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ -#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ -#define SCC_CD_SHIFT 16 - -/* system_clk_ctl */ -#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ -#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ -#define SYCC_FP 0x00000004 /* ForcePLLOn */ -#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ -#define SYCC_HR 0x00000010 /* Force HT */ -#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ -#define SYCC_CD_SHIFT 16 - -/* pcmcia_iowait */ -#define PI_W0_MASK 0x0000003f /* waitcount0 */ -#define PI_W1_MASK 0x00001f00 /* waitcount1 */ -#define PI_W1_SHIFT 8 -#define PI_W2_MASK 0x001f0000 /* waitcount2 */ -#define PI_W2_SHIFT 16 -#define PI_W3_MASK 0x1f000000 /* waitcount3 */ -#define PI_W3_SHIFT 24 - -/* prog_waitcount */ -#define PW_W0_MASK 0x0000001f /* waitcount0 */ -#define PW_W1_MASK 0x00001f00 /* waitcount1 */ -#define PW_W1_SHIFT 8 -#define PW_W2_MASK 0x001f0000 /* waitcount2 */ -#define PW_W2_SHIFT 16 -#define PW_W3_MASK 0x1f000000 /* waitcount3 */ -#define PW_W3_SHIFT 24 - -#define PW_W0 0x0000000c -#define PW_W1 0x00000a00 -#define PW_W2 0x00020000 -#define PW_W3 0x01000000 - -/* watchdog */ -#define WATCHDOG_CLOCK 48000000 /* Hz */ - -/* Fields in pmucontrol */ -#define PCTL_ILP_DIV_MASK 0xffff0000 -#define PCTL_ILP_DIV_SHIFT 16 -#define PCTL_NOILP_ON_WAIT 0x00000200 -#define PCTL_HT_REQ_EN 0x00000100 -#define PCTL_ALP_REQ_EN 0x00000080 -#define PCTL_XTALFREQ_MASK 0x0000007c -#define PCTL_XTALFREQ_SHIFT 2 -#define PCTL_ILP_DIV_EN 0x00000002 -#define PCTL_LPO_SEL 0x00000001 - -/* gpiotimerval */ -#define GPIO_ONTIME_SHIFT 16 - -/* clockcontrol_n */ -#define CN_N1_MASK 0x3f /* n1 control */ -#define CN_N2_MASK 0x3f00 /* n2 control */ -#define CN_N2_SHIFT 8 -#define CN_PLLC_MASK 0xf0000 /* pll control */ -#define CN_PLLC_SHIFT 16 - -/* clockcontrol_sb/pci/uart */ -#define CC_M1_MASK 0x3f /* m1 control */ -#define CC_M2_MASK 0x3f00 /* m2 control */ -#define CC_M2_SHIFT 8 -#define CC_M3_MASK 0x3f0000 /* m3 control */ -#define CC_M3_SHIFT 16 -#define CC_MC_MASK 0x1f000000 /* mux control */ -#define CC_MC_SHIFT 24 - -/* N3M Clock control magic field values */ -#define CC_F6_2 0x02 /* A factor of 2 in */ -#define CC_F6_3 0x03 /* 6-bit fields like */ -#define CC_F6_4 0x05 /* N1, M1 or M3 */ -#define CC_F6_5 0x09 -#define CC_F6_6 0x11 -#define CC_F6_7 0x21 - -#define CC_F5_BIAS 5 /* 5-bit fields get this added */ - -#define CC_MC_BYPASS 0x08 -#define CC_MC_M1 0x04 -#define CC_MC_M1M2 0x02 -#define CC_MC_M1M2M3 0x01 -#define CC_MC_M1M3 0x11 - -/* Type 2 Clock control magic field values */ -#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ -#define CC_T2M2_BIAS 3 /* m2 bias */ - -#define CC_T2MC_M1BYP 1 -#define CC_T2MC_M2BYP 2 -#define CC_T2MC_M3BYP 4 - -/* Type 6 Clock control magic field values */ -#define CC_T6_MMASK 1 /* bits of interest in m */ -#define CC_T6_M0 120000000 /* sb clock for m = 0 */ -#define CC_T6_M1 100000000 /* sb clock for m = 1 */ -#define SB2MIPS_T6(sb) (2 * (sb)) - -/* Common clock base */ -#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */ -#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */ - -/* Clock control values for 200Mhz in 5350 */ -#define CLKC_5350_N 0x0311 -#define CLKC_5350_M 0x04020009 - -/* Flash types in the chipcommon capabilities register */ -#define FLASH_NONE 0x000 /* No flash */ -#define SFLASH_ST 0x100 /* ST serial flash */ -#define SFLASH_AT 0x200 /* Atmel serial flash */ -#define PFLASH 0x700 /* Parallel flash */ - -/* Bits in the ExtBus config registers */ -#define CC_CFG_EN 0x0001 /* Enable */ -#define CC_CFG_EM_MASK 0x000e /* Extif Mode */ -#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ -#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */ -#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ -#define CC_CFG_EM_IDE 0x0006 /* IDE */ -#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ -#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ -#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ -#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ -#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ - -/* ExtBus address space */ -#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ -#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ -#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ -#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ -#define CC_EB_IDE 0x1a800000 /* IDE memory base */ -#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ -#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ -#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ -#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ - - -/* Start/busy bit in flashcontrol */ -#define SFLASH_OPCODE 0x000000ff -#define SFLASH_ACTION 0x00000700 -#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ -#define SFLASH_START 0x80000000 -#define SFLASH_BUSY SFLASH_START - -/* flashcontrol action codes */ -#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ -#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ -#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */ -#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */ -#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */ -#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */ -#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */ - -/* flashcontrol action+opcodes for ST flashes */ -#define SFLASH_ST_WREN 0x0006 /* Write Enable */ -#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */ -#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */ -#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */ -#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */ -#define SFLASH_ST_PP 0x0302 /* Page Program */ -#define SFLASH_ST_SE 0x02d8 /* Sector Erase */ -#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */ -#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */ -#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ -#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ - -/* Status register bits for ST flashes */ -#define SFLASH_ST_WIP 0x01 /* Write In Progress */ -#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */ -#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */ -#define SFLASH_ST_BP_SHIFT 2 -#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ - -/* flashcontrol action+opcodes for Atmel flashes */ -#define SFLASH_AT_READ 0x07e8 -#define SFLASH_AT_PAGE_READ 0x07d2 -#define SFLASH_AT_BUF1_READ -#define SFLASH_AT_BUF2_READ -#define SFLASH_AT_STATUS 0x01d7 -#define SFLASH_AT_BUF1_WRITE 0x0384 -#define SFLASH_AT_BUF2_WRITE 0x0387 -#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 -#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 -#define SFLASH_AT_BUF1_PROGRAM 0x0288 -#define SFLASH_AT_BUF2_PROGRAM 0x0289 -#define SFLASH_AT_PAGE_ERASE 0x0281 -#define SFLASH_AT_BLOCK_ERASE 0x0250 -#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 -#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 -#define SFLASH_AT_BUF1_LOAD 0x0253 -#define SFLASH_AT_BUF2_LOAD 0x0255 -#define SFLASH_AT_BUF1_COMPARE 0x0260 -#define SFLASH_AT_BUF2_COMPARE 0x0261 -#define SFLASH_AT_BUF1_REPROGRAM 0x0258 -#define SFLASH_AT_BUF2_REPROGRAM 0x0259 - -/* Status register bits for Atmel flashes */ -#define SFLASH_AT_READY 0x80 -#define SFLASH_AT_MISMATCH 0x40 -#define SFLASH_AT_ID_MASK 0x38 -#define SFLASH_AT_ID_SHIFT 3 - -/* - * These are the UART port assignments, expressed as offsets from the base - * register. These assignments should hold for any serial port based on - * a 8250, 16450, or 16550(A). - */ - -#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ -#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ -#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ -#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ -#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ -#define UART_IIR 2 /* In: Interrupt Identity Register */ -#define UART_FCR 2 /* Out: FIFO Control Register */ -#define UART_LCR 3 /* Out: Line Control Register */ -#define UART_MCR 4 /* Out: Modem Control Register */ -#define UART_LSR 5 /* In: Line Status Register */ -#define UART_MSR 6 /* In: Modem Status Register */ -#define UART_SCR 7 /* I/O: Scratch Register */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ -#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_RXRDY 0x01 /* Receiver ready */ -#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ - -/* Interrupt Identity Register (IIR) bits */ -#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ -#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ -#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */ -#define UART_IIR_NOINT 0x1 /* No interrupt pending */ -#define UART_IIR_THRE 0x2 /* THR empty */ -#define UART_IIR_RCVD_DATA 0x4 /* Received data available */ -#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ -#define UART_IIR_CHAR_TIME 0xc /* Character time */ - -/* Interrupt Enable Register (IER) bits */ -#define UART_IER_EDSSI 8 /* enable modem status interrupt */ -#define UART_IER_ELSI 4 /* enable receiver line status interrupt */ -#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ -#define UART_IER_ERBFI 1 /* enable data available interrupt */ - -/* pmustatus */ -#define PST_INTPEND 0x0040 -#define PST_SBCLKST 0x0030 -#define PST_ALPAVAIL 0x0008 -#define PST_HTAVAIL 0x0004 -#define PST_RESINIT 0x0003 - -/* pmucapabilities */ -#define PCAP_REV_MASK 0x000000ff - -/* PMU Resource Request Timer registers */ -/* This is based on PmuRev0 */ -#define PRRT_TIME_MASK 0x03ff -#define PRRT_INTEN 0x0400 -#define PRRT_REQ_ACTIVE 0x0800 -#define PRRT_ALP_REQ 0x1000 -#define PRRT_HT_REQ 0x2000 - -/* PMU resource bit position */ -#define PMURES_BIT(bit) (1 << (bit)) - -/* PMU corerev and chip specific PLL controls. - * PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number - * to differentiate different PLLs controlled by the same PMU rev. - */ -/* pllcontrol registers */ -/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ -#define PMU0_PLL0_PLLCTL0 0 -#define PMU0_PLL0_PC0_PDIV_MASK 1 -#define PMU0_PLL0_PC0_PDIV_FREQ 25000 -#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 -#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 -#define PMU0_PLL0_PC0_DIV_ARM_BASE 8 - -/* PC0_DIV_ARM for PLLOUT_ARM */ -#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 -#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 -#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 -#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ -#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 -#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 -#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 -#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 - -/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ -#define PMU0_PLL0_PLLCTL1 1 -#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 -#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 -#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 -#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 -#define PMU0_PLL0_PC1_STOP_MOD 0x00000040 - -/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ -#define PMU0_PLL0_PLLCTL2 2 -#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf -#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 - -/* Chip specific PMU resources. */ -#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ -#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ -#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ -#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ -#define RES4328_ILP_REQUEST 4 /* 0x00010 */ -#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ -#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ -#define RES4328_ROM_SWITCH 7 /* 0x00080 */ -#define RES4328_PA_REF_LDO 8 /* 0x00100 */ -#define RES4328_RADIO_LDO 9 /* 0x00200 */ -#define RES4328_AFE_LDO 10 /* 0x00400 */ -#define RES4328_PLL_LDO 11 /* 0x00800 */ -#define RES4328_BG_FILTBYP 12 /* 0x01000 */ -#define RES4328_TX_FILTBYP 13 /* 0x02000 */ -#define RES4328_RX_FILTBYP 14 /* 0x04000 */ -#define RES4328_XTAL_PU 15 /* 0x08000 */ -#define RES4328_XTAL_EN 16 /* 0x10000 */ -#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ -#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ -#define RES4328_BB_PLL_PU 19 /* 0x80000 */ - -#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ -#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ -#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ -#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ -#define RES5354_ILP_REQUEST 4 /* 0x00010 */ -#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ -#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ -#define RES5354_ROM_SWITCH 7 /* 0x00080 */ -#define RES5354_PA_REF_LDO 8 /* 0x00100 */ -#define RES5354_RADIO_LDO 9 /* 0x00200 */ -#define RES5354_AFE_LDO 10 /* 0x00400 */ -#define RES5354_PLL_LDO 11 /* 0x00800 */ -#define RES5354_BG_FILTBYP 12 /* 0x01000 */ -#define RES5354_TX_FILTBYP 13 /* 0x02000 */ -#define RES5354_RX_FILTBYP 14 /* 0x04000 */ -#define RES5354_XTAL_PU 15 /* 0x08000 */ -#define RES5354_XTAL_EN 16 /* 0x10000 */ -#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ -#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ -#define RES5354_BB_PLL_PU 19 /* 0x80000 */ - -/* pllcontrol registers */ -/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */ -#define PMU1_PLL0_PLLCTL0 0 -#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 -#define PMU1_PLL0_PC0_P1DIV_SHIFT 20 -#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 -#define PMU1_PLL0_PC0_P2DIV_SHIFT 24 - -/* m<x>div */ -#define PMU1_PLL0_PLLCTL1 1 -#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff -#define PMU1_PLL0_PC1_M1DIV_SHIFT 0 -#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 -#define PMU1_PLL0_PC1_M2DIV_SHIFT 8 -#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 -#define PMU1_PLL0_PC1_M3DIV_SHIFT 16 -#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 -#define PMU1_PLL0_PC1_M4DIV_SHIFT 24 - -/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ -#define PMU1_PLL0_PLLCTL2 2 -#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff -#define PMU1_PLL0_PC2_M5DIV_SHIFT 0 -#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 -#define PMU1_PLL0_PC2_M6DIV_SHIFT 8 -#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 -#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 -#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 -#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 - -/* ndiv_frac */ -#define PMU1_PLL0_PLLCTL3 3 -#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff -#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 - -/* pll_ctrl */ -#define PMU1_PLL0_PLLCTL4 4 - -/* pll_ctrl, vco_rng, clkdrive_ch<x> */ -#define PMU1_PLL0_PLLCTL5 5 -#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 -#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 - -#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ -#define RES4325_CBUCK_BURST 1 /* 0x00000002 */ -#define RES4325_CBUCK_PWM 2 /* 0x00000004 */ -#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ -#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ -#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ -#define RES4325_ILP_REQUEST 6 /* 0x00000040 */ -#define RES4325_ABUCK_BURST 7 /* 0x00000080 */ -#define RES4325_ABUCK_PWM 8 /* 0x00000100 */ -#define RES4325_LNLDO1_PU 9 /* 0x00000200 */ -#define RES4325_LNLDO2_PU 10 /* 0x00000400 */ -#define RES4325_LNLDO3_PU 11 /* 0x00000800 */ -#define RES4325_LNLDO4_PU 12 /* 0x00001000 */ -#define RES4325_XTAL_PU 13 /* 0x00002000 */ -#define RES4325_ALP_AVAIL 14 /* 0x00004000 */ -#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ -#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ -#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ -#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ -#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ -#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ -#define RES4325_HT_AVAIL 21 /* 0x00200000 */ - -/* Chip specific ChipStatus register bits */ -#define CST4325_SPROM_OTP_SEL_MASK 0x00000003 -#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ -#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ -#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ -#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ -#define CST4325_SDIO_USB_MODE_MASK 0x00000004 -#define CST4325_SDIO_USB_MODE_SHIFT 2 -#define CST4325_RCAL_VALID_MASK 0x00000008 -#define CST4325_RCAL_VALID_SHIFT 3 -#define CST4325_RCAL_VALUE_MASK 0x000001f0 -#define CST4325_RCAL_VALUE_SHIFT 4 -#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ -#define CST4325_PMUTOP_2B_SHIFT 9 - -#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */ -#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */ -#define RES4312_PA_REF_LDO 2 /* 0x00000004 */ -#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ -#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ -#define RES4312_RADIO_LDO 5 /* 0x00000020 */ -#define RES4312_ILP_REQUEST 6 /* 0x00000040 */ -#define RES4312_BG_FILTBYP 7 /* 0x00000080 */ -#define RES4312_TX_FILTBYP 8 /* 0x00000100 */ -#define RES4312_RX_FILTBYP 9 /* 0x00000200 */ -#define RES4312_XTAL_PU 10 /* 0x00000400 */ -#define RES4312_ALP_AVAIL 11 /* 0x00000800 */ -#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ -#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ -#define RES4312_HT_AVAIL 14 /* 0x00004000 */ - -/* -* Maximum delay for the PMU state transition. -* This is an upper bound intended for spinwaits etc. -*/ -#define PMU_MAX_TRANSITION_DLY 15000 - -#endif /* _SBCHIPC_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h deleted file mode 100644 index e9a5f183dd..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Broadcom SiliconBackplane hardware register definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBCONFIG_H -#define _SBCONFIG_H -#include "linuxver.h" - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* - * SiliconBackplane Address Map. - * All regions may not exist on all chips. - */ -#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */ -#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ -#define SB_PCI_MEM_SZ (64 * 1024 * 1024) -#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ -#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ -#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */ -#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */ - -#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ -#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ -#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */ -#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ -#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ -#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ -#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ -#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ -#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ -#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ -#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ - -#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ -#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ -#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 - * (2 ZettaBytes), low 32 bits - */ -#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 - * (2 ZettaBytes), high 32 bits - */ -#define SB_EUART (SB_EXTIF_BASE + 0x00800000) -#define SB_LED (SB_EXTIF_BASE + 0x00900000) - - -/* enumeration space related defs */ -#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ -#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE) -#define SB_MAXFUNCS 4 /* max. # functions per core */ -#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */ -#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */ - -/* mips address */ -#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ - -/* - * Sonics Configuration Space Registers. - */ -#define SBIPSFLAG 0x08 -#define SBTPSFLAG 0x18 -#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */ -#define SBTMERRLOG 0x50 /* sonics >= 2.3 */ -#define SBADMATCH3 0x60 -#define SBADMATCH2 0x68 -#define SBADMATCH1 0x70 -#define SBIMSTATE 0x90 -#define SBINTVEC 0x94 -#define SBTMSTATELOW 0x98 -#define SBTMSTATEHIGH 0x9c -#define SBBWA0 0xa0 -#define SBIMCONFIGLOW 0xa8 -#define SBIMCONFIGHIGH 0xac -#define SBADMATCH0 0xb0 -#define SBTMCONFIGLOW 0xb8 -#define SBTMCONFIGHIGH 0xbc -#define SBBCONFIG 0xc0 -#define SBBSTATE 0xc8 -#define SBACTCNFG 0xd8 -#define SBFLAGST 0xe8 -#define SBIDLOW 0xf8 -#define SBIDHIGH 0xfc - -/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have - * a few registers *below* that line. I think it would be very confusing to try - * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here, - */ - -#define SBIMERRLOGA 0xea8 -#define SBIMERRLOG 0xeb0 -#define SBTMPORTCONNID0 0xed8 -#define SBTMPORTLOCK0 0xef8 - -#ifndef _LANGUAGE_ASSEMBLY - -typedef volatile struct _sbconfig { - uint32 PAD[2]; - uint32 sbipsflag; /* initiator port ocp slave flag */ - uint32 PAD[3]; - uint32 sbtpsflag; /* target port ocp slave flag */ - uint32 PAD[11]; - uint32 sbtmerrloga; /* (sonics >= 2.3) */ - uint32 PAD; - uint32 sbtmerrlog; /* (sonics >= 2.3) */ - uint32 PAD[3]; - uint32 sbadmatch3; /* address match3 */ - uint32 PAD; - uint32 sbadmatch2; /* address match2 */ - uint32 PAD; - uint32 sbadmatch1; /* address match1 */ - uint32 PAD[7]; - uint32 sbimstate; /* initiator agent state */ - uint32 sbintvec; /* interrupt mask */ - uint32 sbtmstatelow; /* target state */ - uint32 sbtmstatehigh; /* target state */ - uint32 sbbwa0; /* bandwidth allocation table0 */ - uint32 PAD; - uint32 sbimconfiglow; /* initiator configuration */ - uint32 sbimconfighigh; /* initiator configuration */ - uint32 sbadmatch0; /* address match0 */ - uint32 PAD; - uint32 sbtmconfiglow; /* target configuration */ - uint32 sbtmconfighigh; /* target configuration */ - uint32 sbbconfig; /* broadcast configuration */ - uint32 PAD; - uint32 sbbstate; /* broadcast state */ - uint32 PAD[3]; - uint32 sbactcnfg; /* activate configuration */ - uint32 PAD[3]; - uint32 sbflagst; /* current sbflags */ - uint32 PAD[3]; - uint32 sbidlow; /* identification */ - uint32 sbidhigh; /* identification */ -} sbconfig_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* sbipsflag */ -#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ -#define SBIPS_INT1_SHIFT 0 -#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ -#define SBIPS_INT2_SHIFT 8 -#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ -#define SBIPS_INT3_SHIFT 16 -#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ -#define SBIPS_INT4_SHIFT 24 - -/* sbtpsflag */ -#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ -#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ - -/* sbtmerrlog */ -#define SBTMEL_CM 0x00000007 /* command */ -#define SBTMEL_CI 0x0000ff00 /* connection id */ -#define SBTMEL_EC 0x0f000000 /* error code */ -#define SBTMEL_ME 0x80000000 /* multiple error */ - -/* sbimstate */ -#define SBIM_PC 0xf /* pipecount */ -#define SBIM_AP_MASK 0x30 /* arbitration policy */ -#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */ -#define SBIM_AP_TS 0x10 /* use timesliaces only */ -#define SBIM_AP_TK 0x20 /* use token only */ -#define SBIM_AP_RSV 0x30 /* reserved */ -#define SBIM_IBE 0x20000 /* inbanderror */ -#define SBIM_TO 0x40000 /* timeout */ -#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ -#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ - -/* sbtmstatelow */ -#define SBTML_RESET 0x1 /* reset */ -#define SBTML_REJ_MASK 0x6 /* reject */ -#define SBTML_REJ_SHIFT 1 -#define SBTML_CLK 0x10000 /* clock enable */ -#define SBTML_FGC 0x20000 /* force gated clocks on */ -#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */ -#define SBTML_PE 0x40000000 /* pme enable */ -#define SBTML_BE 0x80000000 /* bist enable */ - -/* sbtmstatehigh */ -#define SBTMH_SERR 0x1 /* serror */ -#define SBTMH_INT 0x2 /* interrupt */ -#define SBTMH_BUSY 0x4 /* busy */ -#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */ -#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */ -#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */ -#define SBTMH_GCR 0x20000000 /* gated clock request */ -#define SBTMH_BISTF 0x40000000 /* bist failed */ -#define SBTMH_BISTD 0x80000000 /* bist done */ - - -/* sbbwa0 */ -#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */ -#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */ -#define SBBWA_TAB1_SHIFT 16 - -/* sbimconfiglow */ -#define SBIMCL_STO_MASK 0x7 /* service timeout */ -#define SBIMCL_RTO_MASK 0x70 /* request timeout */ -#define SBIMCL_RTO_SHIFT 4 -#define SBIMCL_CID_MASK 0xff0000 /* connection id */ -#define SBIMCL_CID_SHIFT 16 - -/* sbimconfighigh */ -#define SBIMCH_IEM_MASK 0xc /* inband error mode */ -#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */ -#define SBIMCH_TEM_SHIFT 4 -#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */ -#define SBIMCH_BEM_SHIFT 6 - -/* sbadmatch0 */ -#define SBAM_TYPE_MASK 0x3 /* address type */ -#define SBAM_AD64 0x4 /* reserved */ -#define SBAM_ADINT0_MASK 0xf8 /* type0 size */ -#define SBAM_ADINT0_SHIFT 3 -#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */ -#define SBAM_ADINT1_SHIFT 3 -#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */ -#define SBAM_ADINT2_SHIFT 3 -#define SBAM_ADEN 0x400 /* enable */ -#define SBAM_ADNEG 0x800 /* negative decode */ -#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */ -#define SBAM_BASE0_SHIFT 8 -#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ -#define SBAM_BASE1_SHIFT 12 -#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ -#define SBAM_BASE2_SHIFT 16 - -/* sbtmconfiglow */ -#define SBTMCL_CD_MASK 0xff /* clock divide */ -#define SBTMCL_CO_MASK 0xf800 /* clock offset */ -#define SBTMCL_CO_SHIFT 11 -#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */ -#define SBTMCL_IF_SHIFT 18 -#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */ -#define SBTMCL_IM_SHIFT 24 - -/* sbtmconfighigh */ -#define SBTMCH_BM_MASK 0x3 /* busy mode */ -#define SBTMCH_RM_MASK 0x3 /* retry mode */ -#define SBTMCH_RM_SHIFT 2 -#define SBTMCH_SM_MASK 0x30 /* stop mode */ -#define SBTMCH_SM_SHIFT 4 -#define SBTMCH_EM_MASK 0x300 /* sb error mode */ -#define SBTMCH_EM_SHIFT 8 -#define SBTMCH_IM_MASK 0xc00 /* int mode */ -#define SBTMCH_IM_SHIFT 10 - -/* sbbconfig */ -#define SBBC_LAT_MASK 0x3 /* sb latency */ -#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */ -#define SBBC_MAX0_SHIFT 16 -#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */ -#define SBBC_MAX1_SHIFT 20 - -/* sbbstate */ -#define SBBS_SRD 0x1 /* st reg disable */ -#define SBBS_HRD 0x2 /* hold reg disable */ - -/* sbidlow */ -#define SBIDL_CS_MASK 0x3 /* config space */ -#define SBIDL_AR_MASK 0x38 /* # address ranges supported */ -#define SBIDL_AR_SHIFT 3 -#define SBIDL_SYNCH 0x40 /* sync */ -#define SBIDL_INIT 0x80 /* initiator */ -#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ -#define SBIDL_MINLAT_SHIFT 8 -#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */ -#define SBIDL_MAXLAT_SHIFT 12 -#define SBIDL_FIRST 0x10000 /* this initiator is first */ -#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */ -#define SBIDL_CW_SHIFT 18 -#define SBIDL_TP_MASK 0xf00000 /* target ports */ -#define SBIDL_TP_SHIFT 20 -#define SBIDL_IP_MASK 0xf000000 /* initiator ports */ -#define SBIDL_IP_SHIFT 24 -#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */ -#define SBIDL_RV_SHIFT 28 -#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */ -#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */ - -/* sbidhigh */ -#define SBIDH_RC_MASK 0x000f /* revision code */ -#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ -#define SBIDH_RCE_SHIFT 8 -#define SBCOREREV(sbidh) \ - ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) -#define SBIDH_CC_MASK 0x8ff0 /* core code */ -#define SBIDH_CC_SHIFT 4 -#define SBIDH_VC_MASK 0xffff0000 /* vendor code */ -#define SBIDH_VC_SHIFT 16 - -#define SB_COMMIT 0xfd8 /* update buffered registers value */ - -/* vendor codes */ -#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */ - -/* core codes */ -#define SB_NODEV 0x700 /* Invalid coreid */ -#define SB_CC 0x800 /* chipcommon core */ -#define SB_ILINE20 0x801 /* iline20 core */ -#define SB_SDRAM 0x803 /* sdram core */ -#define SB_PCI 0x804 /* pci core */ -#define SB_MIPS 0x805 /* mips core */ -#define SB_ENET 0x806 /* enet mac core */ -#define SB_CODEC 0x807 /* v90 codec core */ -#define SB_USB 0x808 /* usb 1.1 host/device core */ -#define SB_ADSL 0x809 /* ADSL core */ -#define SB_ILINE100 0x80a /* iline100 core */ -#define SB_IPSEC 0x80b /* ipsec core */ -#define SB_PCMCIA 0x80d /* pcmcia core */ -#define SB_SOCRAM 0x80e /* internal memory core */ -#define SB_MEMC 0x80f /* memc sdram core */ -#define SB_EXTIF 0x811 /* external interface core */ -#define SB_D11 0x812 /* 802.11 MAC core */ -#define SB_MIPS33 0x816 /* mips3302 core */ -#define SB_USB11H 0x817 /* usb 1.1 host core */ -#define SB_USB11D 0x818 /* usb 1.1 device core */ -#define SB_USB20H 0x819 /* usb 2.0 host core */ -#define SB_USB20D 0x81a /* usb 2.0 device core */ -#define SB_SDIOH 0x81b /* sdio host core */ -#define SB_ROBO 0x81c /* roboswitch core */ -#define SB_ATA100 0x81d /* parallel ATA core */ -#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */ -#define SB_GIGETH 0x81f /* gigabit ethernet core */ -#define SB_PCIE 0x820 /* pci express core */ -#define SB_MIMO 0x821 /* MIMO phy core */ -#define SB_SRAMC 0x822 /* SRAM controller core */ -#define SB_MINIMAC 0x823 /* MINI MAC/phy core */ -#define SB_ARM7S 0x825 /* ARM7tdmi-s core */ -#define SB_SDIOD 0x829 /* SDIO device core */ -#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */ -#define SB_OCP 0x830 /* OCP2OCP bridge core */ -#define SB_SC 0x831 /* shared common core */ -#define SB_AHB 0x832 /* OCP2AHB bridge core */ - -#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */ - -/* Not an enumeration space register, but common to all cores to - * communicate w/PMU regarding Silicon Backplane clocking. - */ -#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */ - -/* clk_ctl_st register */ -#define CCS_FORCEALP 0x00000001 /* force ALP request */ -#define CCS_FORCEHT 0x00000002 /* force HT request */ -#define CCS_FORCEILP 0x00000004 /* force ILP request */ -#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ -#define CCS_HTAREQ 0x00000010 /* HT Avail Request */ -#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ -#define CCS_ALPAVAIL 0x00010000 /* ALP is available */ -#define CCS_HTAVAIL 0x00020000 /* HT is available */ -#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ -#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ - -/* Not really related to Silicon Backplane, but a couple of software - * conventions for the use the flash space: - */ - -/* Minumum amount of flash we support */ -#define FLASH_MIN 0x00020000 /* Minimum flash size */ - -/* A boot/binary may have an embedded block that describes its size */ -#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ -#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ -#define BISZ_MAGIC_IDX 0 /* Word 0: magic */ -#define BISZ_TXTST_IDX 1 /* 1: text start */ -#define BISZ_TXTEND_IDX 2 /* 2: text end */ -#define BISZ_DATAST_IDX 3 /* 3: data start */ -#define BISZ_DATAEND_IDX 4 /* 4: data end */ -#define BISZ_BSSST_IDX 5 /* 5: bss start */ -#define BISZ_BSSEND_IDX 6 /* 6: bss end */ -#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */ - -#endif /* _SBCONFIG_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h deleted file mode 100644 index 948118d402..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbextif.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Hardware-specific External Interface I/O core definitions - * for the BCM47xx family of SiliconBackplane-based chips. - * - * The External Interface core supports a total of three external chip selects - * supporting external interfaces. One of the external chip selects is - * used for Flash, one is used for PCMCIA, and the other may be - * programmed to support either a synchronous interface or an - * asynchronous interface. The asynchronous interface can be used to - * support external devices such as UARTs and the BCM2019 Bluetooth - * baseband processor. - * The external interface core also contains 2 on-chip 16550 UARTs, clock - * frequency control, a watchdog interrupt timer, and a GPIO interface. - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBEXTIF_H -#define _SBEXTIF_H - -/* external interface address space */ -#define EXTIF_PCMCIA_MEMBASE(x) (x) -#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000) -#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000) -#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000) -#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000) - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -/* - * The multiple instances of output and output enable registers - * are present to allow driver software for multiple cores to control - * gpio outputs without needing to share a single register pair. - */ -struct gpiouser { - uint32 out; - uint32 outen; -}; -#define NGPIOUSER 5 - -typedef volatile struct { - uint32 corecontrol; - uint32 extstatus; - uint32 PAD[2]; - - /* pcmcia control registers */ - uint32 pcmcia_config; - uint32 pcmcia_memwait; - uint32 pcmcia_attrwait; - uint32 pcmcia_iowait; - - /* programmable interface control registers */ - uint32 prog_config; - uint32 prog_waitcount; - - /* flash control registers */ - uint32 flash_config; - uint32 flash_waitcount; - uint32 PAD[4]; - - uint32 watchdog; - - /* clock control */ - uint32 clockcontrol_n; - uint32 clockcontrol_sb; - uint32 clockcontrol_pci; - uint32 clockcontrol_mii; - uint32 PAD[3]; - - /* gpio */ - uint32 gpioin; - struct gpiouser gpio[NGPIOUSER]; - uint32 PAD; - uint32 ejtagouten; - uint32 gpiointpolarity; - uint32 gpiointmask; - uint32 PAD[153]; - - uint8 uartdata; - uint8 PAD[3]; - uint8 uartimer; - uint8 PAD[3]; - uint8 uartfcr; - uint8 PAD[3]; - uint8 uartlcr; - uint8 PAD[3]; - uint8 uartmcr; - uint8 PAD[3]; - uint8 uartlsr; - uint8 PAD[3]; - uint8 uartmsr; - uint8 PAD[3]; - uint8 uartscratch; - uint8 PAD[3]; -} extifregs_t; - -/* corecontrol */ -#define CC_UE (1 << 0) /* uart enable */ - -/* extstatus */ -#define ES_EM (1 << 0) /* endian mode (ro) */ -#define ES_EI (1 << 1) /* external interrupt pin (ro) */ -#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */ - -/* gpio bit mask */ -#define GPIO_BIT0 (1 << 0) -#define GPIO_BIT1 (1 << 1) -#define GPIO_BIT2 (1 << 2) -#define GPIO_BIT3 (1 << 3) -#define GPIO_BIT4 (1 << 4) -#define GPIO_BIT5 (1 << 5) -#define GPIO_BIT6 (1 << 6) -#define GPIO_BIT7 (1 << 7) - - -/* pcmcia/prog/flash_config */ -#define CF_EN (1 << 0) /* enable */ -#define CF_EM_MASK 0xe /* mode */ -#define CF_EM_SHIFT 1 -#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */ -#define CF_EM_SYNC 0x2 /* synchronous mode */ -#define CF_EM_PCMCIA 0x4 /* pcmcia mode */ -#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */ -#define CF_BS (1 << 5) /* byteswap */ -#define CF_CD_MASK 0xc0 /* clock divider */ -#define CF_CD_SHIFT 6 -#define CF_CD_DIV2 0x0 /* backplane/2 */ -#define CF_CD_DIV3 0x40 /* backplane/3 */ -#define CF_CD_DIV4 0x80 /* backplane/4 */ -#define CF_CE (1 << 8) /* clock enable */ -#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */ - -/* pcmcia_memwait */ -#define PM_W0_MASK 0x3f /* waitcount0 */ -#define PM_W1_MASK 0x1f00 /* waitcount1 */ -#define PM_W1_SHIFT 8 -#define PM_W2_MASK 0x1f0000 /* waitcount2 */ -#define PM_W2_SHIFT 16 -#define PM_W3_MASK 0x1f000000 /* waitcount3 */ -#define PM_W3_SHIFT 24 - -/* pcmcia_attrwait */ -#define PA_W0_MASK 0x3f /* waitcount0 */ -#define PA_W1_MASK 0x1f00 /* waitcount1 */ -#define PA_W1_SHIFT 8 -#define PA_W2_MASK 0x1f0000 /* waitcount2 */ -#define PA_W2_SHIFT 16 -#define PA_W3_MASK 0x1f000000 /* waitcount3 */ -#define PA_W3_SHIFT 24 - -/* prog_waitcount */ -#define PW_W0_MASK 0x0000001f /* waitcount0 */ -#define PW_W1_MASK 0x00001f00 /* waitcount1 */ -#define PW_W1_SHIFT 8 -#define PW_W2_MASK 0x001f0000 /* waitcount2 */ -#define PW_W2_SHIFT 16 -#define PW_W3_MASK 0x1f000000 /* waitcount3 */ -#define PW_W3_SHIFT 24 - -#define PW_W0 0x0000000c -#define PW_W1 0x00000a00 -#define PW_W2 0x00020000 -#define PW_W3 0x01000000 - -/* flash_waitcount */ -#define FW_W0_MASK 0x1f /* waitcount0 */ -#define FW_W1_MASK 0x1f00 /* waitcount1 */ -#define FW_W1_SHIFT 8 -#define FW_W2_MASK 0x1f0000 /* waitcount2 */ -#define FW_W2_SHIFT 16 -#define FW_W3_MASK 0x1f000000 /* waitcount3 */ -#define FW_W3_SHIFT 24 - -/* watchdog */ -#define WATCHDOG_CLOCK 48000000 /* Hz */ - -/* clockcontrol_n */ -#define CN_N1_MASK 0x3f /* n1 control */ -#define CN_N2_MASK 0x3f00 /* n2 control */ -#define CN_N2_SHIFT 8 - -/* clockcontrol_sb/pci/mii */ -#define CC_M1_MASK 0x3f /* m1 control */ -#define CC_M2_MASK 0x3f00 /* m2 control */ -#define CC_M2_SHIFT 8 -#define CC_M3_MASK 0x3f0000 /* m3 control */ -#define CC_M3_SHIFT 16 -#define CC_MC_MASK 0x1f000000 /* mux control */ -#define CC_MC_SHIFT 24 - -/* Clock control default values */ -#define CC_DEF_N 0x0009 /* Default values for bcm4710 */ -#define CC_DEF_100 0x04020011 -#define CC_DEF_33 0x11030011 -#define CC_DEF_25 0x11050011 - -/* Clock control values for 125Mhz */ -#define CC_125_N 0x0802 -#define CC_125_M 0x04020009 -#define CC_125_M25 0x11090009 -#define CC_125_M33 0x11090005 - -/* Clock control magic field values */ -#define CC_F6_2 0x02 /* A factor of 2 in */ -#define CC_F6_3 0x03 /* 6-bit fields like */ -#define CC_F6_4 0x05 /* N1, M1 or M3 */ -#define CC_F6_5 0x09 -#define CC_F6_6 0x11 -#define CC_F6_7 0x21 - -#define CC_F5_BIAS 5 /* 5-bit fields get this added */ - -#define CC_MC_BYPASS 0x08 -#define CC_MC_M1 0x04 -#define CC_MC_M1M2 0x02 -#define CC_MC_M1M2M3 0x01 -#define CC_MC_M1M3 0x11 - -#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */ - -#endif /* _SBEXTIF_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h deleted file mode 100644 index 8479d3033a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbhndmips.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Broadcom SiliconBackplane MIPS definitions - * - * SB MIPS cores are custom MIPS32 processors with SiliconBackplane - * OCP interfaces. The CP0 processor ID is 0x00024000, where bits - * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP - * interface. The core revision is stored in the SB ID register in SB - * configuration space. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sbhndmips_h_ -#define _sbhndmips_h_ - -#include <mipsinc.h> - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -typedef volatile struct { - uint32 corecontrol; - uint32 PAD[2]; - uint32 biststatus; - uint32 PAD[4]; - uint32 intstatus; - uint32 intmask; - uint32 timer; -} mipsregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* _sbhndmips_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h deleted file mode 100644 index 649d41d210..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbmemc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBMEMC_H -#define _SBMEMC_H - -#ifdef _LANGUAGE_ASSEMBLY - -#define MEMC_CONTROL 0x00 -#define MEMC_CONFIG 0x04 -#define MEMC_REFRESH 0x08 -#define MEMC_BISTSTAT 0x0c -#define MEMC_MODEBUF 0x10 -#define MEMC_BKCLS 0x14 -#define MEMC_PRIORINV 0x18 -#define MEMC_DRAMTIM 0x1c -#define MEMC_INTSTAT 0x20 -#define MEMC_INTMASK 0x24 -#define MEMC_INTINFO 0x28 -#define MEMC_NCDLCTL 0x30 -#define MEMC_RDNCDLCOR 0x34 -#define MEMC_WRNCDLCOR 0x38 -#define MEMC_MISCDLYCTL 0x3c -#define MEMC_DQSGATENCDL 0x40 -#define MEMC_SPARE 0x44 -#define MEMC_TPADDR 0x48 -#define MEMC_TPDATA 0x4c -#define MEMC_BARRIER 0x50 -#define MEMC_CORE 0x54 - -#else /* !_LANGUAGE_ASSEMBLY */ - -/* Sonics side: MEMC core registers */ -typedef volatile struct sbmemcregs { - uint32 control; - uint32 config; - uint32 refresh; - uint32 biststat; - uint32 modebuf; - uint32 bkcls; - uint32 priorinv; - uint32 dramtim; - uint32 intstat; - uint32 intmask; - uint32 intinfo; - uint32 reserved1; - uint32 ncdlctl; - uint32 rdncdlcor; - uint32 wrncdlcor; - uint32 miscdlyctl; - uint32 dqsgatencdl; - uint32 spare; - uint32 tpaddr; - uint32 tpdata; - uint32 barrier; - uint32 core; -} sbmemcregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* MEMC Core Init values (OCP ID 0x80f) */ - -/* For sdr: */ -#define MEMC_SD_CONFIG_INIT 0x00048000 -#define MEMC_SD_DRAMTIM2_INIT 0x000754d8 -#define MEMC_SD_DRAMTIM3_INIT 0x000754da -#define MEMC_SD_RDNCDLCOR_INIT 0x00000000 -#define MEMC_SD_WRNCDLCOR_INIT 0x49351200 -#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */ -#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b -#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */ -#define MEMC_SD_CONTROL_INIT0 0x00000002 -#define MEMC_SD_CONTROL_INIT1 0x00000008 -#define MEMC_SD_CONTROL_INIT2 0x00000004 -#define MEMC_SD_CONTROL_INIT3 0x00000010 -#define MEMC_SD_CONTROL_INIT4 0x00000001 -#define MEMC_SD_MODEBUF_INIT 0x00000000 -#define MEMC_SD_REFRESH_INIT 0x0000840f - - -/* This is for SDRM8X8X4 */ -#define MEMC_SDR_INIT 0x0008 -#define MEMC_SDR_MODE 0x32 -#define MEMC_SDR_NCDL 0x00020032 -#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */ - -/* For ddr: */ -#define MEMC_CONFIG_INIT 0x00048000 -#define MEMC_DRAMTIM2_INIT 0x000754d8 -#define MEMC_DRAMTIM25_INIT 0x000754d9 -#define MEMC_RDNCDLCOR_INIT 0x00000000 -#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */ -#define MEMC_WRNCDLCOR_INIT 0x49351200 -#define MEMC_1_WRNCDLCOR_INIT 0x14500200 -#define MEMC_DQSGATENCDL_INIT 0x00030000 -#define MEMC_MISCDLYCTL_INIT 0x21061c1b -#define MEMC_1_MISCDLYCTL_INIT 0x21021400 -#define MEMC_NCDLCTL_INIT 0x00002001 -#define MEMC_CONTROL_INIT0 0x00000002 -#define MEMC_CONTROL_INIT1 0x00000008 -#define MEMC_MODEBUF_INIT0 0x00004000 -#define MEMC_CONTROL_INIT2 0x00000010 -#define MEMC_MODEBUF_INIT1 0x00000100 -#define MEMC_CONTROL_INIT3 0x00000010 -#define MEMC_CONTROL_INIT4 0x00000008 -#define MEMC_REFRESH_INIT 0x0000840f -#define MEMC_CONTROL_INIT5 0x00000004 -#define MEMC_MODEBUF_INIT2 0x00000000 -#define MEMC_CONTROL_INIT6 0x00000010 -#define MEMC_CONTROL_INIT7 0x00000001 - - -/* This is for DDRM16X16X2 */ -#define MEMC_DDR_INIT 0x0009 -#define MEMC_DDR_MODE 0x62 -#define MEMC_DDR_NCDL 0x0005050a -#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */ - -/* mask for sdr/ddr calibration registers */ -#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff -#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff -#define MEMC_DQSGATENCDL_G_MASK 0x000000ff - -/* masks for miscdlyctl registers */ -#define MEMC_MISC_SM_MASK 0x30000000 -#define MEMC_MISC_SM_SHIFT 28 -#define MEMC_MISC_SD_MASK 0x0f000000 -#define MEMC_MISC_SD_SHIFT 24 - -/* hw threshhold for calculating wr/rd for sdr memc */ -#define MEMC_CD_THRESHOLD 128 - -/* Low bit of init register says if memc is ddr or sdr */ -#define MEMC_CONFIG_DDR 0x00000001 - -#endif /* _SBMEMC_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h deleted file mode 100644 index c31959ab25..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpci.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * HND SiliconBackplane PCI core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sbpci_h_ -#define _sbpci_h_ - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* Sonics side: PCI core and host control registers */ -typedef struct sbpciregs { - uint32 control; /* PCI control */ - uint32 PAD[3]; - uint32 arbcontrol; /* PCI arbiter control */ - uint32 PAD[3]; - uint32 intstatus; /* Interrupt status */ - uint32 intmask; /* Interrupt mask */ - uint32 sbtopcimailbox; /* Sonics to PCI mailbox */ - uint32 PAD[9]; - uint32 bcastaddr; /* Sonics broadcast address */ - uint32 bcastdata; /* Sonics broadcast data */ - uint32 PAD[2]; - uint32 gpioin; /* ro: gpio input (>=rev2) */ - uint32 gpioout; /* rw: gpio output (>=rev2) */ - uint32 gpioouten; /* rw: gpio output enable (>= rev2) */ - uint32 gpiocontrol; /* rw: gpio control (>= rev2) */ - uint32 PAD[36]; - uint32 sbtopci0; /* Sonics to PCI translation 0 */ - uint32 sbtopci1; /* Sonics to PCI translation 1 */ - uint32 sbtopci2; /* Sonics to PCI translation 2 */ - uint32 PAD[189]; - uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ - uint16 sprom[36]; /* SPROM shadow Area */ - uint32 PAD[46]; -} sbpciregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* PCI control */ -#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ -#define PCI_RST 0x02 /* Value driven out to pin */ -#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ -#define PCI_CLK 0x08 /* Gate for clock driven out to pin */ - -/* PCI arbiter control */ -#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */ -#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */ -/* ParkID - for PCI corerev >= 8 */ -#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ -#define PCI_PARKID_SHIFT 2 -#define PCI_PARKID_EXT0 0 /* External master 0 */ -#define PCI_PARKID_EXT1 1 /* External master 1 */ -#define PCI_PARKID_EXT2 2 /* External master 2 */ -#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ -#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */ -#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */ -#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */ -#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */ - -/* Interrupt status/mask */ -#define PCI_INTA 0x01 /* PCI INTA# is asserted */ -#define PCI_INTB 0x02 /* PCI INTB# is asserted */ -#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ -#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ -#define PCI_PME 0x10 /* PCI PME# is asserted */ - -/* (General) PCI/SB mailbox interrupts, two bits per pci function */ -#define MAILBOX_F0_0 0x100 /* function 0, int 0 */ -#define MAILBOX_F0_1 0x200 /* function 0, int 1 */ -#define MAILBOX_F1_0 0x400 /* function 1, int 0 */ -#define MAILBOX_F1_1 0x800 /* function 1, int 1 */ -#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */ -#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */ -#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */ -#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */ - -/* Sonics broadcast address */ -#define BCAST_ADDR_MASK 0xff /* Broadcast register address */ - -/* Sonics to PCI translation types */ -#define SBTOPCI0_MASK 0xfc000000 -#define SBTOPCI1_MASK 0xfc000000 -#define SBTOPCI2_MASK 0xc0000000 -#define SBTOPCI_MEM 0 -#define SBTOPCI_IO 1 -#define SBTOPCI_CFG0 2 -#define SBTOPCI_CFG1 3 -#define SBTOPCI_PREF 0x4 /* prefetch enable */ -#define SBTOPCI_BURST 0x8 /* burst enable */ -#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ -#define SBTOPCI_RC_READ 0x00 /* memory read */ -#define SBTOPCI_RC_READLINE 0x10 /* memory read line */ -#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ - -/* PCI core index in SROM shadow area */ -#define SRSH_PI_OFFSET 0 /* first word */ -#define SRSH_PI_MASK 0xf000 /* bit 15:12 */ -#define SRSH_PI_SHIFT 12 /* bit 15:12 */ - -#endif /* _sbpci_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h deleted file mode 100644 index 922aeb1095..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcie.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * BCM43XX SiliconBackplane PCIE core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBPCIE_H -#define _SBPCIE_H - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* PCIE Enumeration space offsets */ -#define PCIE_CORE_CONFIG_OFFSET 0x0 -#define PCIE_FUNC0_CONFIG_OFFSET 0x400 -#define PCIE_FUNC1_CONFIG_OFFSET 0x500 -#define PCIE_FUNC2_CONFIG_OFFSET 0x600 -#define PCIE_FUNC3_CONFIG_OFFSET 0x700 -#define PCIE_SPROM_SHADOW_OFFSET 0x800 -#define PCIE_SBCONFIG_OFFSET 0xE00 - -/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ -#define PCIE_DEV_BAR0_SIZE 0x4000 -#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 -#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 -#define PCIE_BAR0_PCIECORE_OFFSET 0x2000 -#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 - -/* different register spaces to access thr'u pcie indirect access */ -#define PCIE_CONFIGREGS 1 /* Access to config space */ -#define PCIE_PCIEREGS 2 /* Access to pcie registers */ - -/* SB side: PCIE core and host control registers */ -typedef struct sbpcieregs { - uint32 PAD[3]; - uint32 biststatus; /* bist Status: 0x00C */ - uint32 gpiosel; /* PCIE gpio sel: 0x010 */ - uint32 gpioouten; /* PCIE gpio outen: 0x14 */ - uint32 PAD[4]; - uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ - uint32 PAD[54]; - uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ - uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ - uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ - uint32 PAD[4]; - - /* pcie core supports in direct access to config space */ - uint32 configaddr; /* pcie config space access: Address field: 0x120 */ - uint32 configdata; /* pcie config space access: Data field: 0x124 */ - - /* mdio access to serdes */ - uint32 mdiocontrol; /* controls the mdio access: 0x128 */ - uint32 mdiodata; /* Data to the mdio access: 0x12c */ - - /* pcie protocol phy/dllp/tlp register indirect access mechanism */ - uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ - uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ - - uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ - uint32 PAD[433]; - uint16 sprom[36]; /* SPROM shadow Area */ -} sbpcieregs_t; - -/* SB to PCIE translation masks */ -#define SBTOPCIE0_MASK 0xfc000000 -#define SBTOPCIE1_MASK 0xfc000000 -#define SBTOPCIE2_MASK 0xc0000000 - -/* Access type bits (0:1) */ -#define SBTOPCIE_MEM 0 -#define SBTOPCIE_IO 1 -#define SBTOPCIE_CFG0 2 -#define SBTOPCIE_CFG1 3 - -/* Prefetch enable bit 2 */ -#define SBTOPCIE_PF 4 - -/* Write Burst enable for memory write bit 3 */ -#define SBTOPCIE_WR_BURST 8 - -/* config access */ -#define CONFIGADDR_FUNC_MASK 0x7000 -#define CONFIGADDR_FUNC_SHF 12 -#define CONFIGADDR_REG_MASK 0x0FFF -#define CONFIGADDR_REG_SHF 0 - -/* PCIE protocol regs Indirect Address */ -#define PCIEADDR_PROT_MASK 0x300 -#define PCIEADDR_PROT_SHF 8 -#define PCIEADDR_PL_TLP 0 -#define PCIEADDR_PL_DLLP 1 -#define PCIEADDR_PL_PLP 2 - -/* PCIE protocol PHY diagnostic registers */ -#define PCIE_PLP_MODEREG 0x200 /* Mode */ -#define PCIE_PLP_STATUSREG 0x204 /* Status */ -#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ -#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ -#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ -#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ -#define PCIE_PLP_ATTNREG 0x218 /* Attention */ -#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ -#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ -#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ -#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ -#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ -#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ -#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ -#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ -#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ - -/* PCIE protocol DLLP diagnostic registers */ -#define PCIE_DLLP_LCREG 0x100 /* Link Control */ -#define PCIE_DLLP_LSREG 0x104 /* Link Status */ -#define PCIE_DLLP_LAREG 0x108 /* Link Attention */ -#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ -#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ -#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ -#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ -#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ -#define PCIE_DLLP_LRREG 0x120 /* Link Replay */ -#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ -#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ -#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ -#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ -#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ -#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ -#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ -#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ -#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ -#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ -#define PCIE_DLLP_TESTREG 0x14C /* Test */ -#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ -#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ - -/* PCIE protocol TLP diagnostic registers */ -#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */ -#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ -#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ -#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ -#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ -#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ -#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ -#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ -#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ -#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ -#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ -#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ -#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ -#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ -#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ -#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ -#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ -#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ -#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ -#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ -#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ -#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ -#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ -#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ -#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ -#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ -#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ -#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ -#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ -#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ -#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ - -/* MDIO control */ -#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ -#define MDIOCTL_DIVISOR_VAL 0x2 -#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ -#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ - -/* MDIO Data */ -#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ -#define MDIODATA_TA 0x00020000 /* Turnaround */ -#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ -#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */ -#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */ -#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */ -#define MDIODATA_WRITE 0x10000000 /* write Transaction */ -#define MDIODATA_READ 0x20000000 /* Read Transaction */ -#define MDIODATA_START 0x40000000 /* start of Transaction */ - -/* MDIO devices (SERDES modules) */ -#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ -#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ -#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ - -/* SERDES RX registers */ -#define SERDES_RX_CTRL 1 /* Rx cntrl */ -#define SERDES_RX_TIMER1 2 /* Rx Timer1 */ -#define SERDES_RX_CDR 6 /* CDR */ -#define SERDES_RX_CDRBW 7 /* CDR BW */ - -/* SERDES RX control register */ -#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ -#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ - -/* SERDES PLL registers */ -#define SERDES_PLL_CTRL 1 /* PLL control reg */ -#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ - -#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ -#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ -#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ - -/* SPROM offsets */ -#define SRSH_ASPM_OFFSET 4 /* word 4 */ -#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ -#define SRSH_CLKREQ_OFFSET 20 /* word 20 */ -#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ - -/* Linkcontrol reg offset in PCIE Cap */ -#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ -#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ -#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ -#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */ -#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ - -/* Status reg PCIE_PLP_STATUSREG */ -#define PCIE_PLP_POLARITYINV_STAT 0x10 - -#endif /* _SBPCIE_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h deleted file mode 100644 index a5cc42c496..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbpcmcia.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBPCMCIA_H -#define _SBPCMCIA_H - - -/* All the addresses that are offsets in attribute space are divided - * by two to account for the fact that odd bytes are invalid in - * attribute space and our read/write routines make the space appear - * as if they didn't exist. Still we want to show the original numbers - * as documented in the hnd_pcmcia core manual. - */ - -/* PCMCIA Function Configuration Registers */ -#define PCMCIA_FCR (0x700 / 2) - -#define FCR0_OFF 0 -#define FCR1_OFF (0x40 / 2) -#define FCR2_OFF (0x80 / 2) -#define FCR3_OFF (0xc0 / 2) - -#define PCMCIA_FCR0 (0x700 / 2) -#define PCMCIA_FCR1 (0x740 / 2) -#define PCMCIA_FCR2 (0x780 / 2) -#define PCMCIA_FCR3 (0x7c0 / 2) - -/* Standard PCMCIA FCR registers */ - -#define PCMCIA_COR 0 - -#define COR_RST 0x80 -#define COR_LEV 0x40 -#define COR_IRQEN 0x04 -#define COR_BLREN 0x01 -#define COR_FUNEN 0x01 - - -#define PCICIA_FCSR (2 / 2) -#define PCICIA_PRR (4 / 2) -#define PCICIA_SCR (6 / 2) -#define PCICIA_ESR (8 / 2) - - -#define PCM_MEMOFF 0x0000 -#define F0_MEMOFF 0x1000 -#define F1_MEMOFF 0x2000 -#define F2_MEMOFF 0x3000 -#define F3_MEMOFF 0x4000 - -/* Memory base in the function fcr's */ -#define MEM_ADDR0 (0x728 / 2) -#define MEM_ADDR1 (0x72a / 2) -#define MEM_ADDR2 (0x72c / 2) - -/* PCMCIA base plus Srom access in fcr0: */ -#define PCMCIA_ADDR0 (0x072e / 2) -#define PCMCIA_ADDR1 (0x0730 / 2) -#define PCMCIA_ADDR2 (0x0732 / 2) - -#define MEM_SEG (0x0734 / 2) -#define SROM_CS (0x0736 / 2) -#define SROM_DATAL (0x0738 / 2) -#define SROM_DATAH (0x073a / 2) -#define SROM_ADDRL (0x073c / 2) -#define SROM_ADDRH (0x073e / 2) -#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ -#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ - -/* Values for srom_cs: */ -#define SROM_IDLE 0 -#define SROM_WRITE 1 -#define SROM_READ 2 -#define SROM_WEN 4 -#define SROM_WDS 7 -#define SROM_DONE 8 - -/* Fields in srom_info: */ -#define SRI_SZ_MASK 0x03 -#define SRI_BLANK 0x04 -#define SRI_OTP 0x80 - -/* CIS stuff */ - -/* The CIS stops where the FCRs start */ -#define CIS_SIZE PCMCIA_FCR - -/* CIS tuple length field max */ -#define CIS_TUPLE_LEN_MAX 0xff - -/* Standard tuples we know about */ - -#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ -#define CISTPL_MANFID 0x20 /* Manufacturer and device id */ -#define CISTPL_FUNCID 0x21 /* Function identification */ -#define CISTPL_FUNCE 0x22 /* Function extensions */ -#define CISTPL_CFTABLE 0x1b /* Config table entry */ -#define CISTPL_END 0xff /* End of the CIS tuple chain */ - -/* Function identifier provides context for the function extentions tuple */ - - -/* Function extensions for LANs */ - -#define LAN_TECH 1 /* Technology type */ -#define LAN_SPEED 2 /* Raw bit rate */ -#define LAN_MEDIA 3 /* Transmission media */ -#define LAN_NID 4 /* Node identification (aka MAC addr) */ -#define LAN_CONN 5 /* Connector standard */ - - -/* CFTable */ -#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ -#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ -#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ - -/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll - * take one for HNBU, and use "extensions" (a la FUNCE) within it. - */ - -#define CISTPL_BRCM_HNBU 0x80 - -/* Subtypes of BRCM_HNBU: */ - -#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ -#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ -#define HNBU_BOARDREV 0x02 /* One byte board revision */ -#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) - * or 9 (sromrev > 1) bytes - */ -#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ -#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ -#define HNBU_AA 0x06 /* Antennas available */ -#define HNBU_AG 0x07 /* Antenna gain */ -#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ -#define HNBU_LEDS 0x09 /* LED set */ -#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) - * in rev 2 - */ -#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ -#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ -#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ -#define HNBU_PAPARMS5G 0x0e /* 5G PA params */ -#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ -#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ -#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, - * 2 bytes, rev 3. - */ -#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, - * 2 bytes, rev 3. - */ -#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ -#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ -#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ -#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ -#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ -#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ -#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ -#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ -#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ -#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ -#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ -#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 - * plus extra info appended. - */ - -/* sbtmstatelow */ -#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ -#define SBTML_INT_EN 0x20000 /* enable sb interrupt */ - -/* sbtmstatehigh */ -#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ - -#endif /* _SBPCMCIA_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h deleted file mode 100644 index 31a553fa99..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBSDRAM_H -#define _SBSDRAM_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* Sonics side: SDRAM core registers */ -typedef volatile struct sbsdramregs { - uint32 initcontrol; /* Generates external SDRAM initialization sequence */ - uint32 config; /* Initializes external SDRAM mode register */ - uint32 refresh; /* Controls external SDRAM refresh rate */ - uint32 pad1; - uint32 pad2; -} sbsdramregs_t; - -#endif /* !_LANGUAGE_ASSEMBLY */ - -/* SDRAM initialization control (initcontrol) register bits */ -#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */ -#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */ -#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */ -#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */ -#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */ -#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */ -#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */ -#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */ -#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */ -#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */ -#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */ -#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */ -#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */ - -/* SDRAM configuration (config) register bits */ -#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */ -#define SDRAM_BURST8 0x0001 /* Use burst of 8 */ -#define SDRAM_BURST4 0x0002 /* Use burst of 4 */ -#define SDRAM_BURST2 0x0003 /* Use burst of 2 */ -#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */ -#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */ - -/* SDRAM refresh control (refresh) register bits */ -#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */ -#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */ - -/* SDRAM Core default Init values (OCP ID 0x803) */ -#define SDRAM_INIT MEM4MX16X2 -#define SDRAM_CONFIG SDRAM_BURSTFULL -#define SDRAM_REFRESH SDRAM_REF(0x40) - -#define MEM1MX16 0x009 /* 2 MB */ -#define MEM1MX16X2 0x409 /* 4 MB */ -#define MEM2MX8X2 0x809 /* 4 MB */ -#define MEM2MX8X4 0xc09 /* 8 MB */ -#define MEM2MX32 0x439 /* 8 MB */ -#define MEM4MX16 0x019 /* 8 MB */ -#define MEM4MX16X2 0x419 /* 16 MB */ -#define MEM8MX8X2 0x819 /* 16 MB */ -#define MEM8MX16 0x829 /* 16 MB */ -#define MEM4MX32 0x429 /* 16 MB */ -#define MEM8MX8X4 0xc19 /* 32 MB */ -#define MEM8MX16X2 0xc29 /* 32 MB */ - -#endif /* _SBSDRAM_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h deleted file mode 100644 index 0e6fdc1e1a..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane embedded ram core - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _SBSOCRAM_H -#define _SBSOCRAM_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -/* Memcsocram core registers */ -typedef volatile struct sbsocramregs { - uint32 coreinfo; - uint32 bwalloc; - uint32 PAD; - uint32 biststat; - uint32 bankidx; - uint32 standbyctrl; - uint32 PAD[116]; - uint32 pwrctl; /* corerev >= 2 */ -} sbsocramregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* Register offsets */ -#define SR_COREINFO 0x00 -#define SR_BWALLOC 0x04 -#define SR_BISTSTAT 0x0c -#define SR_BANKINDEX 0x10 -#define SR_BANKSTBYCTL 0x14 -#define SR_PWRCTL 0x1e8 - -/* Coreinfo register */ -#define SRCI_PT_MASK 0x00030000 -#define SRCI_PT_SHIFT 16 -/* corerev >= 3 */ -#define SRCI_LSS_MASK 0x00f00000 -#define SRCI_LSS_SHIFT 20 -#define SRCI_LRS_MASK 0x0f000000 -#define SRCI_LRS_SHIFT 24 - -/* In corerev 0, the memory size is 2 to the power of the - * base plus 16 plus to the contents of the memsize field plus 1. - */ -#define SRCI_MS0_MASK 0xf -#define SR_MS0_BASE 16 - -/* - * In corerev 1 the bank size is 2 ^ the bank size field plus 14, - * the memory size is number of banks times bank size. - * The same applies to rom size. - */ -#define SRCI_ROMNB_MASK 0xf000 -#define SRCI_ROMNB_SHIFT 12 -#define SRCI_ROMBSZ_MASK 0xf00 -#define SRCI_ROMBSZ_SHIFT 8 -#define SRCI_SRNB_MASK 0xf0 -#define SRCI_SRNB_SHIFT 4 -#define SRCI_SRBSZ_MASK 0xf -#define SRCI_SRBSZ_SHIFT 0 - -#define SR_BSZ_BASE 14 - -/* Standby control register */ -#define SRSC_SBYOVR_MASK 0x80000000 -#define SRSC_SBYOVR_SHIFT 31 -#define SRSC_SBYOVRVAL_MASK 0x60000000 -#define SRSC_SBYOVRVAL_SHIFT 29 - -#endif /* _SBSOCRAM_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h deleted file mode 100644 index bef9183ece..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsprom.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * SPROM format definitions for the Broadcom 47xx and 43xx chip family. - * - * Copyright(c) 2002 Broadcom Corporation - */ - -#ifndef _SBSPROM_H -#define _SBSPROM_H - -#include "typedefs.h" -#include "bcmdevs.h" - -/* A word is this many bytes */ -#define SRW 2 - -/* offset into PCI config space for write enable bit */ -#define CFG_SROM_WRITABLE_OFFSET 0x88 -#define SROM_WRITEABLE 0x10 - -/* enumeration space consists of N contiguous 4Kbyte core register sets */ -#define SBCORES_BASE 0x18000000 -#define SBCORES_EACH 0x1000 - -/* offset from BAR0 for srom space */ -#define SROM_BASE 4096 - -/* number of 2-byte words in srom */ -#define SROM_SIZE 64 - -#define SROM_BYTES (SROM_SIZE * SRW) - -#define MAX_FN 4 - -/* Word 0, Hardware control */ -#define SROM_HWCTL 0 -#define HW_FUNMSK 0x000f -#define HW_FCLK 0x0200 -#define HW_CBM 0x0400 -#define HW_PIMSK 0xf000 -#define HW_PISHIFT 12 -#define HW_4301PISHIFT 13 -#define HW_PI4402 0x2 -#define HW_FUN4401 0x0001 -#define HW_FCLK4402 0x0000 - -/* Word 1, common-power/boot-rom */ -#define SROM_COMMPW 1 -/* boot rom present bit */ -#define BR_PRESSHIFT 8 -/* 15:9 for n; boot rom size is 2^(14 + n) bytes */ -#define BR_SIZESHIFT 9 - -/* Word 2, SubsystemId */ -#define SROM_SSID 2 - -/* Word 3, VendorId */ -#define SROM_VID 3 - -/* Function 0 info, function info length */ -#define SROM_FN0 4 -#define SROM_FNSZ 8 - -/* Within each function: */ -/* Word 0, deviceID */ -#define SRFN_DID 0 - -/* Words 1-2, ClassCode */ -#define SRFN_CCL 1 -/* Word 2, D0 Power */ -#define SRFN_CCHD0 2 - -/* Word 3, PME and D1D2D3 power */ -#define SRFN_PMED123 3 - -#define PME_IL 0 -#define PME_ENET0 1 -#define PME_ENET1 2 -#define PME_CODEC 3 - -#define PME_4402_ENET 0 -#define PME_4402_CODEC 1 -#define PME_4301_WL 2 -#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME) - -/* Word 4, Bar1 enable, pme reports */ -#define SRFN_B1PMER 4 -#define B1E 1 -#define B1SZMSK 0xe -#define B1SZSH 1 -#define PMERMSK 0x0ff0 -#define PME 0x0010 -#define PMERD0 0x0020 -#define PMERD1 0x0040 -#define PMERD2 0x0080 -#define PMERD3H 0x0100 -#define PMERD3CA 0x0200 -#define PMERD3CV 0x0400 -#define IGNCLKRR 0x0800 -#define B0LMSK 0xf000 - -/* Words 4-5, Bar0 Sonics value */ -#define SRFN_B0H 5 -/* Words 6-7, CIS Pointer */ -#define SRFN_CISL 6 -#define SRFN_CISH 7 - -/* Words 36-38: iLine MAC address */ -#define SROM_I_MACHI 36 -#define SROM_I_MACMID 37 -#define SROM_I_MACLO 38 - -/* Words 36-38: wireless0 MAC address on 43xx */ -#define SROM_W0_MACHI 36 -#define SROM_W0_MACMID 37 -#define SROM_W0_MACLO 38 - -/* Words 39-41: enet0 MAC address */ -#define SROM_E0_MACHI 39 -#define SROM_E0_MACMID 40 -#define SROM_E0_MACLO 41 - -/* Words 42-44: enet1 MAC address */ -#define SROM_E1_MACHI 42 -#define SROM_E1_MACMID 43 -#define SROM_E1_MACLO 44 - -/* Words 42-44: wireless1 MAC address on 4309 */ -#define SROM_W1_MACHI 42 -#define SROM_W1_MACMID 43 -#define SROM_W1_MACLO 44 - -#define SROM_EPHY 45 - -/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */ -#define SROM_REV_AA_LOCK 46 - -/* Words 47-51 wl0 PA bx */ -#define SROM_WL0_PAB0 47 -#define SROM_WL0_PAB1 48 -#define SROM_WL0_PAB2 49 -#define SROM_WL0_PAB3 50 -#define SROM_WL0_PAB4 51 - -/* Word 52: wl0/wl1 MaxPower */ -#define SROM_WL_MAXPWR 52 - -/* Words 53-55 wl1 PA bx */ -#define SROM_WL1_PAB0 53 -#define SROM_WL1_PAB1 54 -#define SROM_WL1_PAB2 55 - -/* Woprd 56: itt */ -#define SROM_ITT 56 - -/* Words 59-62: OEM Space */ -#define SROM_WL_OEM 59 -#define SROM_OEM_SIZE 4 - -/* Contents for the srom */ - -#define BU4710_SSID 0x0400 -#define VSIM4710_SSID 0x0401 -#define QT4710_SSID 0x0402 - -#define BU4610_SSID 0x0403 -#define VSIM4610_SSID 0x0404 - -#define BU4307_SSID 0x0405 -#define BCM94301CB_SSID 0x0406 -#define BCM94301MP_SSID 0x0407 -#define BCM94307MP_SSID 0x0408 -#define AP4307_SSID 0x0409 - -#define BU4309_SSID 0x040a -#define BCM94309CB_SSID 0x040b -#define BCM94309MP_SSID 0x040c -#define AP4309_SSID 0x040d - -#define BU4402_SSID 0x4402 - -#define CLASS_OTHER 0x8000 -#define CLASS_ETHER 0x0000 -#define CLASS_NET 0x0002 -#define CLASS_COMM 0x0007 -#define CLASS_MODEM 0x0300 -#define CLASS_MIPS 0x3000 -#define CLASS_PROC 0x000b -#define CLASS_FLASH 0x0100 -#define CLASS_MEM 0x0005 -#define CLASS_SERIALBUS 0x000c -#define CLASS_OHCI 0x0310 - -/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */ -#define MACHI 0x90 - -#define MACMID_BU4710I 0x4c17 -#define MACMID_BU4710E0 0x4c18 -#define MACMID_BU4710E1 0x4c19 - -#define MACMID_94710R1I 0x4c1a -#define MACMID_94710R1E0 0x4c1b -#define MACMID_94710R1E1 0x4c1c - -#define MACMID_94710R4I 0x4c1d -#define MACMID_94710R4E0 0x4c1e -#define MACMID_94710R4E1 0x4c1f - -#define MACMID_94710DEVI 0x4c20 -#define MACMID_94710DEVE0 0x4c21 -#define MACMID_94710DEVE1 0x4c22 - -#define MACMID_BU4402 0x4c23 - -#define MACMID_BU4610I 0x4c24 -#define MACMID_BU4610E0 0x4c25 -#define MACMID_BU4610E1 0x4c26 - -#define MACMID_BU4307W 0x4c27 -#define MACMID_BU4307E 0x4c28 - -#define MACMID_94301CB 0x4c29 - -#define MACMID_94301MP 0x4c2a - -#define MACMID_94307MPW 0x4c2b -#define MACMID_94307MPE 0x4c2c - -#define MACMID_AP4307W 0x4c2d -#define MACMID_AP4307E 0x4c2e - -#define MACMID_BU4309W0 0x4c2f -#define MACMID_BU4309W1 0x4c30 -#define MACMID_BU4309E 0x4c31 - -#define MACMID_94309CBW0 0x4c32 -#define MACMID_94309CBW1 0x4c33 - -#define MACMID_94309MPW0 0x4c34 -#define MACMID_94309MPW1 0x4c35 -#define MACMID_94309MPE 0x4c36 - -#define MACMID_BU4401 0x4c37 - -/* Enet phy settings one or two singles or a dual */ -/* Bits 4-0 : MII address for enet0 (0x1f for not there */ -/* Bits 9-5 : MII address for enet1 (0x1f for not there */ -/* Bit 14 : Mdio for enet0 */ -/* Bit 15 : Mdio for enet1 */ - -/* bu4710 with only one phy on enet1 with address 7: */ -#define SROM_EPHY_ONE 0x80ff - -/* bu4710 with two individual phys, at 6 and 7, */ -/* each mdio connected to its own mac: */ -#define SROM_EPHY_TWO 0x80e6 - -/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */ -#define SROM_EPHY_DUAL 0x0001 - -/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */ -#define SROM_EPHY_R1 0x0010 - -/* r4 board with a single phy on enet0 at address 5 and a switch */ -/* chip on enet1 (speciall case: 0x1e */ -#define SROM_EPHY_R4 0x83e5 - -/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */ -#define SROM_EPHY_INTERNAL 0x0001 - -/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */ -#define SROM_EPHY_ZERO 0x0000 - -#define SROM_VERS 0x0001 - - -#endif /* _SBSPROM_H */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h deleted file mode 100644 index 097a13d021..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Misc utility routines for accessing chip-specific features - * of Broadcom HNBU SiliconBackplane-based chips. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sbutils_h_ -#define _sbutils_h_ - -/* - * Data structure to export all chip specific common variables - * public (read-only) portion of sbutils handle returned by - * sb_attach()/sb_kattach() -*/ - -struct sb_pub { - - uint bustype; /* SB_BUS, PCI_BUS */ - uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */ - uint buscorerev; /* buscore rev */ - uint buscoreidx; /* buscore index */ - int ccrev; /* chip common core rev */ - uint32 cccaps; /* chip common capabilities */ - int pmurev; /* pmu core rev */ - uint32 pmucaps; /* pmu capabilities */ - uint boardtype; /* board type */ - uint boardvendor; /* board vendor */ - uint boardflags; /* board flags */ - uint chip; /* chip number */ - uint chiprev; /* chip revision */ - uint chippkg; /* chip package option */ - uint32 chipst; /* chip status */ - uint sonicsrev; /* sonics backplane rev */ - bool pr42780; /* whether PCIE 42780 WAR applies to this chip */ - bool pr32414; /* whether 432414 WAR applis to the chip */ -}; - -typedef const struct sb_pub sb_t; - -/* - * Many of the routines below take an 'sbh' handle as their first arg. - * Allocate this by calling sb_attach(). Free it by calling sb_detach(). - * At any one time, the sbh is logically focused on one particular sb core - * (the "current core"). - * Use sb_setcore() or sb_setcoreidx() to change the association to another core. - */ - -#define SB_OSH NULL /* Use for sb_kattach when no osh is available */ - -/* exported externs */ -extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, - void *sdh, char **vars, uint *varsz); -extern sb_t *sb_kattach(osl_t *osh); -extern void sb_detach(sb_t *sbh); -extern uint sb_chip(sb_t *sbh); -extern uint sb_chiprev(sb_t *sbh); -extern uint sb_chipcrev(sb_t *sbh); -extern uint sb_chippkg(sb_t *sbh); -extern uint sb_pcirev(sb_t *sbh); -extern bool sb_war16165(sb_t *sbh); -extern uint sb_pcmciarev(sb_t *sbh); -extern uint sb_boardvendor(sb_t *sbh); -extern uint sb_boardtype(sb_t *sbh); -extern uint sb_bus(sb_t *sbh); -extern uint sb_buscoretype(sb_t *sbh); -extern uint sb_buscorerev(sb_t *sbh); -extern uint sb_corelist(sb_t *sbh, uint coreid[]); -extern uint sb_coreid(sb_t *sbh); -extern uint sb_flag(sb_t *sbh); -extern uint sb_coreidx(sb_t *sbh); -extern uint sb_coreunit(sb_t *sbh); -extern uint sb_corevendor(sb_t *sbh); -extern uint sb_corerev(sb_t *sbh); -extern void *sb_osh(sb_t *sbh); -extern void sb_setosh(sb_t *sbh, osl_t *osh); -extern uint sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val); -extern void *sb_coreregs(sb_t *sbh); -extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val); -extern void sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val); -extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val); -extern bool sb_iscoreup(sb_t *sbh); -extern uint sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit); -extern void *sb_setcoreidx(sb_t *sbh, uint coreidx); -extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit); -extern int sb_corebist(sb_t *sbh); -extern void sb_commit(sb_t *sbh); -extern uint32 sb_base(uint32 admatch); -extern uint32 sb_size(uint32 admatch); -extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits); -extern void sb_core_tofixup(sb_t *sbh); -extern void sb_core_disable(sb_t *sbh, uint32 bits); -extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m); -extern uint32 sb_clock(sb_t *sbh); -extern uint32 sb_alp_clock(sb_t *sbh); -extern void sb_pci_setup(sb_t *sbh, uint coremask); -extern void sb_pcmcia_init(sb_t *sbh); -extern void sb_watchdog(sb_t *sbh, uint ticks); -extern void *sb_gpiosetcore(sb_t *sbh); -extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioin(sb_t *sbh); -extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority); -extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val); -extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority); -extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority); -extern uint32 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val); -extern uint32 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val); -extern uint32 sb_gpio_int_enable(sb_t *sbh, bool enable); - -/* GPIO event handlers */ -typedef void (*gpio_handler_t)(uint32 stat, void *arg); - -extern void *sb_gpio_handler_register(sb_t *sbh, uint32 event, - bool level, gpio_handler_t cb, void *arg); -extern void sb_gpio_handler_unregister(sb_t *sbh, void* gpioh); -extern void sb_gpio_handler_process(sb_t *sbh); - -extern void sb_clkctl_init(sb_t *sbh); -extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh); -extern bool sb_clkctl_clk(sb_t *sbh, uint mode); -extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on); -extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, - void *intrsenabled_fn, void *intr_arg); -extern void sb_deregister_intr_callback(sb_t *sbh); -extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx); -extern uint16 sb_d11_devid(sb_t *sbh); -extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice, - uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, - uint8 *pciheader); -extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset); -extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val); -extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val); -extern bool sb_backplane64(sb_t *sbh); -extern void sb_btcgpiowar(sb_t *sbh); - - -#if defined(BCMDBG_ASSERT) -extern bool sb_taclear(sb_t *sbh); -#endif - -#ifdef BCMDBG -extern void sb_dump(sb_t *sbh, struct bcmstrbuf *b); -extern void sb_dumpregs(sb_t *sbh, struct bcmstrbuf *b); -extern void sb_view(sb_t *sbh); -extern void sb_viewall(sb_t *sbh); -extern void sb_clkctl_dump(sb_t *sbh, struct bcmstrbuf *b); -extern uint8 sb_pcieL1plldown(sb_t *sbh); -extern uint32 sb_pcielcreg(sb_t *sbh, uint32 mask, uint32 val); -#endif - -extern bool sb_deviceremoved(sb_t *sbh); -extern uint32 sb_socram_size(sb_t *sbh); - -/* -* Build device path. Path size must be >= SB_DEVPATH_BUFSZ. -* The returned path is NULL terminated and has trailing '/'. -* Return 0 on success, nonzero otherwise. -*/ -extern int sb_devpath(sb_t *sbh, char *path, int size); -/* Read variable with prepending the devpath to the name */ -extern char *sb_getdevpathvar(sb_t *sbh, const char *name); -extern int sb_getdevpathintvar(sb_t *sbh, const char *name); - -extern uint8 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val); -extern void sb_war42780_clkreq(sb_t *sbh, bool clkreq); -extern void sb_pci_sleep(sb_t *sbh); -extern void sb_pci_down(sb_t *sbh); -extern void sb_pci_up(sb_t *sbh); - -/* Wake-on-wireless-LAN (WOWL) */ -extern bool sb_pci_pmecap(sb_t *sbh); -extern bool sb_pci_pmeclr(sb_t *sbh); -extern void sb_pci_pmeen(sb_t *sbh); - -/* clkctl xtal what flags */ -#define XTAL 0x1 /* primary crystal oscillator (2050) */ -#define PLL 0x2 /* main chip pll */ - -/* clkctl clk mode */ -#define CLK_FAST 0 /* force fast (pll) clock */ -#define CLK_DYNAMIC 2 /* enable dynamic clock control */ - - -/* GPIO usage priorities */ -#define GPIO_DRV_PRIORITY 0 /* Driver */ -#define GPIO_APP_PRIORITY 1 /* Application */ -#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */ - -/* GPIO pull up/down */ -#define GPIO_PULLUP 0 -#define GPIO_PULLDN 1 - -/* GPIO event regtype */ -#define GPIO_REGEVT 0 /* GPIO register event */ -#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */ -#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */ - -/* device path */ -#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */ - -#endif /* _sbutils_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h deleted file mode 100644 index f5f903a4cb..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sflash.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Broadcom SiliconBackplane chipcommon serial flash interface - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#ifndef _sflash_h_ -#define _sflash_h_ - -#include <typedefs.h> -#include <sbchipc.h> -#include <sbutils.h> - -struct sflash { - uint blocksize; /* Block size */ - uint numblocks; /* Number of blocks */ - uint32 type; /* Type */ - uint size; /* Total size in bytes */ -}; - -/* Utility functions */ -extern int sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset); -extern int sflash_read(sb_t *sbh, chipcregs_t *cc, - uint offset, uint len, uchar *buf); -extern int sflash_write(sb_t *sbh, chipcregs_t *cc, - uint offset, uint len, const uchar *buf); -extern int sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset); -extern int sflash_commit(sb_t *sbh, chipcregs_t *cc, - uint offset, uint len, const uchar *buf); -extern struct sflash *sflash_init(sb_t *sbh, chipcregs_t *cc); - -#endif /* _sflash_h_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h deleted file mode 100644 index 0a2474e499..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/trxhdr.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * TRX image file header format. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <typedefs.h> - -#define TRX_MAGIC 0x30524448 /* "HDR0" */ -#define TRX_VERSION 1 /* Version 1 */ -#define TRX_MAX_LEN 0x7A0000 /* Max length */ -#define TRX_NO_HEADER 1 /* Do not write TRX header */ -#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */ -#define TRX_MAX_OFFSET 3 /* Max number of individual files */ - -struct trx_header { - uint32 magic; /* "HDR0" */ - uint32 len; /* Length of file including header */ - uint32 crc32; /* 32-bit CRC from flag_version to end of file */ - uint32 flag_version; /* 0:15 flags, 16:31 version */ - uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ -}; - -/* Compatibility */ -typedef struct trx_header TRXHDR, *PTRXHDR; diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h deleted file mode 100644 index 20bcc8c2fd..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/typedefs.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#ifndef _TYPEDEFS_H_ -#define _TYPEDEFS_H_ - - -/* Define 'SITE_TYPEDEFS' in the compile to include a site specific - * typedef file "site_typedefs.h". - * - * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs" - * section of this file makes inferences about the compile environment - * based on defined symbols and possibly compiler pragmas. - * - * Following these two sections is the "Default Typedefs" - * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is - * defined. This section has a default set of typedefs and a few - * proprocessor symbols (TRUE, FALSE, NULL, ...). - */ - -#ifdef SITE_TYPEDEFS - -/* - * Site Specific Typedefs - * - */ - -#include "site_typedefs.h" - -#else - -/* - * Inferred Typedefs - * - */ - -/* Infer the compile environment based on preprocessor symbols and pramas. - * Override type definitions as needed, and include configuration dependent - * header files to define types. - */ - -#ifdef __cplusplus - -#define TYPEDEF_BOOL -#ifndef FALSE -#define FALSE false -#endif -#ifndef TRUE -#define TRUE true -#endif - -#else /* ! __cplusplus */ - -#if defined(_WIN32) - -#define TYPEDEF_BOOL -typedef unsigned char bool; /* consistent w/BOOL */ - -#endif /* _WIN32 */ - -#endif /* ! __cplusplus */ - -/* use the Windows ULONG_PTR type when compiling for 64 bit */ -#if defined(_WIN64) && !defined(EFI) -#include <basetsd.h> -#define TYPEDEF_UINTPTR -typedef ULONG_PTR uintptr; -#elif defined(__x86_64__) -#define TYPEDEF_UINTPTR -typedef unsigned long long int uintptr; -#endif - - -#if defined(_MINOSL_) -#define _NEED_SIZE_T_ -#endif - -#if defined(EFI) && !defined(_WIN64) -#define _NEED_SIZE_T_ -#endif - -#if defined(_NEED_SIZE_T_) -typedef long unsigned int size_t; -#endif - -#ifdef __DJGPP__ -typedef long unsigned int size_t; -#endif /* __DJGPP__ */ - -#ifdef _MSC_VER /* Microsoft C */ -#define TYPEDEF_INT64 -#define TYPEDEF_UINT64 -typedef signed __int64 int64; -typedef unsigned __int64 uint64; -#endif - -#if defined(MACOSX) -#define TYPEDEF_BOOL -#endif - -#if defined(__NetBSD__) -#define TYPEDEF_ULONG -#endif - - -#ifdef linux -#define TYPEDEF_UINT -#define TYPEDEF_USHORT -#define TYPEDEF_ULONG -#ifdef __KERNEL__ -#include <linux/version.h> -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) -#define TYPEDEF_BOOL -#endif /* >= 2.6.19 */ -#endif /* __KERNEL__ */ -#endif /* linux */ - -#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \ - !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__) && !defined(__IOPOS__) -#define TYPEDEF_UINT -#define TYPEDEF_USHORT -#endif - - -/* Do not support the (u)int64 types with strict ansi for GNU C */ -#if defined(__GNUC__) && defined(__STRICT_ANSI__) -#define TYPEDEF_INT64 -#define TYPEDEF_UINT64 -#endif - -/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode - * for singned or unsigned - */ -#if defined(__ICL) - -#define TYPEDEF_INT64 - -#if defined(__STDC__) -#define TYPEDEF_UINT64 -#endif - -#endif /* __ICL */ - -#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \ - !defined(__DJGPP__) && !defined(__IOPOS__) - -/* pick up ushort & uint from standard types.h */ -#if defined(linux) && defined(__KERNEL__) - -#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */ - -#else - -#include <sys/types.h> - -#endif - -#endif - -#if defined(MACOSX) - -#ifdef __BIG_ENDIAN__ -#define IL_BIGENDIAN -#else -#ifdef IL_BIGENDIAN -#error "IL_BIGENDIAN was defined for a little-endian compile" -#endif -#endif /* __BIG_ENDIAN__ */ - -#if !defined(__cplusplus) - -#if defined(__i386__) -typedef unsigned char bool; -#else -typedef unsigned int bool; -#endif -#define TYPE_BOOL 1 -enum { - false = 0, - true = 1 -}; - -#if defined(KERNEL) -#include <IOKit/IOTypes.h> -#endif /* KERNEL */ - -#endif /* __cplusplus */ - -#endif /* MACOSX */ - - -/* use the default typedefs in the next section of this file */ -#define USE_TYPEDEF_DEFAULTS - -#endif /* SITE_TYPEDEFS */ - - -/* - * Default Typedefs - * - */ - -#ifdef USE_TYPEDEF_DEFAULTS -#undef USE_TYPEDEF_DEFAULTS - -#ifndef TYPEDEF_BOOL -typedef /* @abstract@ */ unsigned char bool; -#endif - -/* define uchar, ushort, uint, ulong */ - -#ifndef TYPEDEF_UCHAR -typedef unsigned char uchar; -#endif - -#ifndef TYPEDEF_USHORT -typedef unsigned short ushort; -#endif - -#ifndef TYPEDEF_UINT -typedef unsigned int uint; -#endif - -#ifndef TYPEDEF_ULONG -typedef unsigned long ulong; -#endif - -/* define [u]int8/16/32/64, uintptr */ - -#ifndef TYPEDEF_UINT8 -typedef unsigned char uint8; -#endif - -#ifndef TYPEDEF_UINT16 -typedef unsigned short uint16; -#endif - -#ifndef TYPEDEF_UINT32 -typedef unsigned int uint32; -#endif - -#ifndef TYPEDEF_UINT64 -typedef unsigned long long uint64; -#endif - -#ifndef TYPEDEF_UINTPTR -typedef unsigned int uintptr; -#endif - -#ifndef TYPEDEF_INT8 -typedef signed char int8; -#endif - -#ifndef TYPEDEF_INT16 -typedef signed short int16; -#endif - -#ifndef TYPEDEF_INT32 -typedef signed int int32; -#endif - -#ifndef TYPEDEF_INT64 -typedef signed long long int64; -#endif - -/* define float32/64, float_t */ - -#ifndef TYPEDEF_FLOAT32 -typedef float float32; -#endif - -#ifndef TYPEDEF_FLOAT64 -typedef double float64; -#endif - -/* - * abstracted floating point type allows for compile time selection of - * single or double precision arithmetic. Compiling with -DFLOAT32 - * selects single precision; the default is double precision. - */ - -#ifndef TYPEDEF_FLOAT_T - -#if defined(FLOAT32) -typedef float32 float_t; -#else /* default to double precision floating point */ -typedef float64 float_t; -#endif - -#endif /* TYPEDEF_FLOAT_T */ - -/* define macro values */ - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 /* TRUE */ -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef OFF -#define OFF 0 -#endif - -#ifndef ON -#define ON 1 /* ON = 1 */ -#endif - -#define AUTO (-1) /* Auto = -1 */ - -/* define PTRSZ, INLINE */ - -#ifndef PTRSZ -#define PTRSZ sizeof(char*) -#endif - -#ifndef INLINE - -#ifdef _MSC_VER - -#define INLINE __inline - -#elif defined(__GNUC__) - -#define INLINE __inline__ - -#else - -#define INLINE - -#endif /* _MSC_VER */ - -#endif /* INLINE */ - -#undef TYPEDEF_BOOL -#undef TYPEDEF_UCHAR -#undef TYPEDEF_USHORT -#undef TYPEDEF_UINT -#undef TYPEDEF_ULONG -#undef TYPEDEF_UINT8 -#undef TYPEDEF_UINT16 -#undef TYPEDEF_UINT32 -#undef TYPEDEF_UINT64 -#undef TYPEDEF_UINTPTR -#undef TYPEDEF_INT8 -#undef TYPEDEF_INT16 -#undef TYPEDEF_INT32 -#undef TYPEDEF_INT64 -#undef TYPEDEF_FLOAT32 -#undef TYPEDEF_FLOAT64 -#undef TYPEDEF_FLOAT_T - -#endif /* USE_TYPEDEF_DEFAULTS */ - -/* - * Including the bcmdefs.h here, to make sure everyone including typedefs.h - * gets this automatically -*/ -#include "bcmdefs.h" - -#endif /* _TYPEDEFS_H_ */ diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/nvram.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/nvram.c deleted file mode 100644 index e93752a373..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/nvram.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * NVRAM variable manipulation (Linux kernel half) - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/slab.h> -#include <linux/bootmem.h> -#include <linux/wrapper.h> -#include <linux/fs.h> -#include <linux/miscdevice.h> -#include <linux/mtd/mtd.h> -#include <asm/addrspace.h> -#include <asm/io.h> -#include <asm/uaccess.h> - -#include <typedefs.h> -#include <osl.h> -#include <bcmendian.h> -#include <bcmnvram.h> -#include <sbconfig.h> -#include <sbchipc.h> -#include <sbutils.h> -#include <hndmips.h> -#include <sflash.h> - -/* In BSS to minimize text size and page aligned so it can be mmap()-ed */ -static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE))); - -/* Global SB handle */ -extern void *bcm947xx_sbh; -extern spinlock_t bcm947xx_sbh_lock; - -static int cfe_env; -extern char *cfe_env_get(char *nv_buf, const char *name); - -/* Convenience */ -#define sbh bcm947xx_sbh -#define sbh_lock bcm947xx_sbh_lock - -/* Probe for NVRAM header */ -static void __init -early_nvram_init(void) -{ - struct nvram_header *header; - chipcregs_t *cc; - struct sflash *info = NULL; - int i; - uint32 base, off, lim; - u32 *src, *dst; - - if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) { - base = KSEG1ADDR(SB_FLASH2); - switch (readl(&cc->capabilities) & CC_CAP_FLASH_MASK) { - case PFLASH: - lim = SB_FLASH2_SZ; - break; - - case SFLASH_ST: - case SFLASH_AT: - if ((info = sflash_init(sbh,cc)) == NULL) - return; - lim = info->size; - break; - - case FLASH_NONE: - default: - return; - } - } else { - /* extif assumed, Stop at 4 MB */ - base = KSEG1ADDR(SB_FLASH1); - lim = SB_FLASH1_SZ; - } - - /* XXX: hack for supporting the CFE environment stuff on WGT634U */ - src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000); - dst = (u32 *) nvram_buf; - if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) { - printk("early_nvram_init: WGT634U NVRAM found.\n"); - - for (i = 0; i < 0x1ff0; i++) { - if (*src == 0xFFFFFFFF) - break; - *dst++ = *src++; - } - cfe_env = 1; - return; - } - - off = FLASH_MIN; - while (off <= lim) { - /* Windowed flash access */ - header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE); - if (header->magic == NVRAM_MAGIC) - goto found; - off <<= 1; - } - - /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ - header = (struct nvram_header *) KSEG1ADDR(base + 4 * 1024); - if (header->magic == NVRAM_MAGIC) - goto found; - - header = (struct nvram_header *) KSEG1ADDR(base + 1 * 1024); - if (header->magic == NVRAM_MAGIC) - goto found; - - printk("early_nvram_init: NVRAM not found\n"); - return; - -found: - src = (u32 *) header; - dst = (u32 *) nvram_buf; - for (i = 0; i < sizeof(struct nvram_header); i += 4) - *dst++ = *src++; - for (; i < header->len && i < NVRAM_SPACE; i += 4) - *dst++ = ltoh32(*src++); -} - -/* Early (before mm or mtd) read-only access to NVRAM */ -static char * __init -early_nvram_get(const char *name) -{ - char *var, *value, *end, *eq; - - if (!name) - return NULL; - - /* Too early? */ - if (sbh == NULL) - return NULL; - - if (!nvram_buf[0]) - early_nvram_init(); - - if (cfe_env) - return cfe_env_get(nvram_buf, name); - - /* Look for name=value and return value */ - var = &nvram_buf[sizeof(struct nvram_header)]; - end = nvram_buf + sizeof(nvram_buf) - 2; - end[0] = end[1] = '\0'; - for (; *var; var = value + strlen(value) + 1) { - if (!(eq = strchr(var, '='))) - break; - value = eq + 1; - if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0) - return value; - } - - return NULL; -} - -static int __init -early_nvram_getall(char *buf, int count) -{ - char *var, *end; - int len = 0; - - /* Too early? */ - if (sbh == NULL) - return -1; - - if (!nvram_buf[0]) - early_nvram_init(); - - bzero(buf, count); - - /* Write name=value\0 ... \0\0 */ - var = &nvram_buf[sizeof(struct nvram_header)]; - end = nvram_buf + sizeof(nvram_buf) - 2; - end[0] = end[1] = '\0'; - for (; *var; var += strlen(var) + 1) { - if ((count - len) <= (strlen(var) + 1)) - break; - len += sprintf(buf + len, "%s", var) + 1; - } - - return 0; -} - - -char * -nvram_get(const char *name) -{ - return early_nvram_get(name); -} - -int -nvram_getall(char *buf, int count) -{ - unsigned long flags; - int ret; - - return early_nvram_getall(buf, count); -} - -/* - * Search the name=value vars for a specific one and return its value. - * Returns NULL if not found. - */ -char* -getvar(char *vars, const char *name) -{ - char *s; - int len; - - len = strlen(name); - - /* first look in vars[] */ - for (s = vars; s && *s;) { - /* CSTYLED */ - if ((memcmp(s, name, len) == 0) && (s[len] == '=')) - return (&s[len+1]); - - while (*s++); - } - - /* then query nvram */ - return (nvram_get(name)); -} - -/* - * Search the vars for a specific one and return its value as - * an integer. Returns 0 if not found. - */ -int -getintvar(char *vars, const char *name) -{ - char *val; - - if ((val = getvar(vars, name)) == NULL) - return (0); - - return (simple_strtoul(val, NULL, 0)); -} - diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c deleted file mode 100644 index c7610f0d79..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * Low-Level PCI and SB support for BCM47xx (Linux support code) - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/pci.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/paccess.h> - -#include <typedefs.h> -#include <osl.h> -#include <sbconfig.h> -#include <sbutils.h> -#include <hndpci.h> -#include <pcicfg.h> -#include <bcmdevs.h> -#include <bcmnvram.h> - -/* Global SB handle */ -extern sb_t *bcm947xx_sbh; -extern spinlock_t bcm947xx_sbh_lock; - -/* Convenience */ -#define sbh bcm947xx_sbh -#define sbh_lock bcm947xx_sbh_lock - -static int -sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&sbh_lock, flags); - ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), where, value, sizeof(*value)); - spin_unlock_irqrestore(&sbh_lock, flags); - return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static int -sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&sbh_lock, flags); - ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), where, value, sizeof(*value)); - spin_unlock_irqrestore(&sbh_lock, flags); - return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static int -sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&sbh_lock, flags); - ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), where, value, sizeof(*value)); - spin_unlock_irqrestore(&sbh_lock, flags); - return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static int -sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&sbh_lock, flags); - ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), where, &value, sizeof(value)); - spin_unlock_irqrestore(&sbh_lock, flags); - return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static int -sbpci_write_config_word(struct pci_dev *dev, int where, u16 value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&sbh_lock, flags); - ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), where, &value, sizeof(value)); - spin_unlock_irqrestore(&sbh_lock, flags); - return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static int -sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&sbh_lock, flags); - ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), where, &value, sizeof(value)); - spin_unlock_irqrestore(&sbh_lock, flags); - return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops pcibios_ops = { - sbpci_read_config_byte, - sbpci_read_config_word, - sbpci_read_config_dword, - sbpci_write_config_byte, - sbpci_write_config_word, - sbpci_write_config_dword -}; - - -void __init -pcibios_init(void) -{ - ulong flags; - - if (!(sbh = sb_kattach(SB_OSH))) - panic("sb_kattach failed"); - spin_lock_init(&sbh_lock); - - spin_lock_irqsave(&sbh_lock, flags); - sbpci_init(sbh); - spin_unlock_irqrestore(&sbh_lock, flags); - - set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000)); - mdelay(300); /* workaround for atheros cards */ - - /* Scan the SB bus */ - pci_scan_bus(0, &pcibios_ops, NULL); - -} - -char * __init -pcibios_setup(char *str) -{ - if (!strncmp(str, "ban=", 4)) { - sbpci_ban(simple_strtoul(str + 4, NULL, 0)); - return NULL; - } - - return (str); -} - -static u32 pci_iobase = 0x100; -static u32 pci_membase = SB_PCI_DMA; -static u32 pcmcia_membase = 0x40004000; - -void __init -pcibios_fixup_bus(struct pci_bus *b) -{ - struct list_head *ln; - struct pci_dev *d; - struct resource *res; - int pos, size; - u32 *base; - u8 irq; - - printk("PCI: Fixing up bus %d\n", b->number); - - /* Fix up SB */ - if (b->number == 0) { - for (ln = b->devices.next; ln != &b->devices; ln = ln->next) { - d = pci_dev_b(ln); - /* Fix up interrupt lines */ - pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq); - d->irq = irq + 2; - pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); - } - } - - /* Fix up external PCI */ - else { - for (ln = b->devices.next; ln != &b->devices; ln = ln->next) { - d = pci_dev_b(ln); - /* Fix up resource bases */ - for (pos = 0; pos < 6; pos++) { - res = &d->resource[pos]; - base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase); - if (res->end) { - size = res->end - res->start + 1; - if (*base & (size - 1)) - *base = (*base + size) & ~(size - 1); - res->start = *base; - res->end = res->start + size - 1; - *base += size; - pci_write_config_dword(d, - PCI_BASE_ADDRESS_0 + (pos << 2), res->start); - } - /* Fix up PCI bridge BAR0 only */ - if (b->number == 1 && PCI_SLOT(d->devfn) == 0) - break; - } - /* Fix up interrupt lines */ - if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL)) - d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq; - pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); - } - } -} - -unsigned int -pcibios_assign_all_busses(void) -{ - return 1; -} - -void -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ -} - -int -pcibios_enable_resources(struct pci_dev *dev) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - /* External PCI only */ - if (dev->bus->number == 0) - return 0; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for (idx = 0; idx < 6; idx++) { - r = &dev->resource[idx]; - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (dev->resource[PCI_ROM_RESOURCE].start) - cmd |= PCI_COMMAND_MEMORY; - if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - -int -pcibios_enable_device(struct pci_dev *dev, int mask) -{ - ulong flags; - uint coreidx; - void *regs; - - /* External PCI device enable */ - if (dev->bus->number != 0) - return pcibios_enable_resources(dev); - - /* These cores come out of reset enabled */ - if (dev->device == SB_MIPS || - dev->device == SB_MIPS33 || - dev->device == SB_EXTIF || - dev->device == SB_CC) - return 0; - - spin_lock_irqsave(&sbh_lock, flags); - coreidx = sb_coreidx(sbh); - regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)); - if (!regs) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* - * The USB core requires a special bit to be set during core - * reset to enable host (OHCI) mode. Resetting the SB core in - * pcibios_enable_device() is a hack for compatibility with - * vanilla usb-ohci so that it does not have to know about - * SB. A driver that wants to use the USB core in device mode - * should know about SB and should reset the bit back to 0 - * after calling pcibios_enable_device(). - */ - if (sb_coreid(sbh) == SB_USB) { - printk(KERN_INFO "SB USB 1.1 init\n"); - sb_core_disable(sbh, sb_coreflags(sbh, 0, 0)); - sb_core_reset(sbh, 1 << 29, 0); - } - /* - * USB 2.0 special considerations: - * - * 1. Since the core supports both OHCI and EHCI functions, it must - * only be reset once. - * - * 2. In addition to the standard SB reset sequence, the Host Control - * Register must be programmed to bring the USB core and various - * phy components out of reset. - */ - else if (sb_coreid(sbh) == SB_USB20H) { - - uint corerev = sb_corerev(sbh); - - printk(KERN_INFO "SB USB20H init\n"); - printk(KERN_INFO "SB COREREV: %d\n", corerev); - - if (!sb_iscoreup(sbh)) { - - printk(KERN_INFO "SB USB20H resetting\n"); - - sb_core_reset(sbh, 0, 0); - writel(0x7FF, (ulong)regs + 0x200); - udelay(1); - } - /* PRxxxx: War for 5354 failures. */ - if (corerev == 1 || corerev == 2) { - uint32 tmp; - - /* Change Flush control reg */ - tmp = readl((uintptr)regs + 0x400); - tmp &= ~8; - writel(tmp, (uintptr)regs + 0x400); - tmp = readl((uintptr)regs + 0x400); - printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp); - - /* Change Shim control reg */ - tmp = readl((uintptr)regs + 0x304); - tmp &= ~0x100; - writel(tmp, (uintptr)regs + 0x304); - tmp = readl((uintptr)regs + 0x304); - printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp); - } - - } else - sb_core_reset(sbh, 0, 0); - - sb_setcoreidx(sbh, coreidx); - spin_unlock_irqrestore(&sbh_lock, flags); - - return 0; -} - -void -pcibios_update_resource(struct pci_dev *dev, struct resource *root, - struct resource *res, int resource) -{ - unsigned long where, size; - u32 reg; - - /* External PCI only */ - if (dev->bus->number == 0) - return; - - where = PCI_BASE_ADDRESS_0 + (resource * 4); - size = res->end - res->start; - pci_read_config_dword(dev, where, ®); - - if (dev->bus->number == 1) - reg = (reg & size) | (((u32)(res->start - root->start)) & ~size); - else - reg = res->start; - - pci_write_config_dword(dev, where, reg); -} - -static void __init -quirk_sbpci_bridge(struct pci_dev *dev) -{ - if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0) - return; - - printk("PCI: Fixing up bridge\n"); - - /* Enable PCI bridge bus mastering and memory space */ - pci_set_master(dev); - pcibios_enable_resources(dev); - - /* Enable PCI bridge BAR1 prefetch and burst */ - pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3); -} - -struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge }, - { 0 } -}; - -/* - * If we set up a device for bus mastering, we need to check the latency - * timer as certain crappy BIOSes forget to set it properly. - */ -unsigned int pcibios_max_latency = 255; - -void pcibios_set_master(struct pci_dev *dev) -{ - u8 lat; - pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); - if (lat < 16) - lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; - else if (lat > pcibios_max_latency) - lat = pcibios_max_latency; - else - return; - printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat); - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); -} - diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/prom.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/prom.c deleted file mode 100644 index c9745746c1..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/prom.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Early initialization code for BCM94710 boards - * - * Copyright 2004, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <asm/bootinfo.h> - -void __init -prom_init(int argc, const char **argv) -{ - unsigned long mem; - unsigned long max; - - mips_machgroup = MACH_GROUP_BRCM; - mips_machtype = MACH_BCM947XX; - - /* Figure out memory size by finding aliases - * - * BCM47XX uses 128MB for addressing the ram, if the system contains - * less that that amount of ram it remaps the ram more often into the - * available space. - * Accessing memory after 128MB will cause an exception. - * max contains the biggest possible address supported by the platform. - * If the method wants to try something above we assume 128MB ram. - */ - max = ((unsigned long)(prom_init) | ((128 << 20) - 1)); - for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) { - if (((unsigned long)(prom_init) + mem) > max) { - mem = (128 << 20); - printk("assume 128MB RAM\n"); - break; - } - if (*(unsigned long *)((unsigned long)(prom_init) + mem) == - *(unsigned long *)(prom_init)) - break; - } - - add_memory_region(0, mem, BOOT_MEM_RAM); -} - -void __init -prom_free_prom_memory(void) -{ -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbmips.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbmips.c deleted file mode 100644 index 86870e05e1..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbmips.c +++ /dev/null @@ -1,1266 +0,0 @@ -/* - * BCM47XX Sonics SiliconBackplane MIPS core routines - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <typedefs.h> -#include <bcmdefs.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmdevs.h> -#include <bcmnvram.h> -#include <sbconfig.h> -#include <sbchipc.h> -#include <sbextif.h> -#include <sbmemc.h> -#include <mipsinc.h> -#include <sbhndmips.h> -#include <hndcpu.h> -#include <hndmips.h> - -/* sbipsflag register format, indexed by irq. */ -static const uint32 sbips_int_mask[] = { - 0, /* placeholder */ - SBIPS_INT1_MASK, - SBIPS_INT2_MASK, - SBIPS_INT3_MASK, - SBIPS_INT4_MASK -}; - -static const uint32 sbips_int_shift[] = { - 0, /* placeholder */ - SBIPS_INT1_SHIFT, - SBIPS_INT2_SHIFT, - SBIPS_INT3_SHIFT, - SBIPS_INT4_SHIFT -}; - -/* - * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs. - * Per-port BSP code is required to provide necessary translations between - * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag. - * - * See sb_irq() for the mapping. - */ -static uint shirq_map_base = 0; - -/* Returns the SB interrupt flag of the current core. */ -static uint32 sb_getflag(sb_t * sbh) -{ - osl_t *osh; - void *regs; - sbconfig_t *sb; - - osh = sb_osh(sbh); - regs = sb_coreregs(sbh); - sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF); - - return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK); -} - -/* - * Returns the MIPS IRQ assignment of the current core. If unassigned, - * 0 is returned. - */ -uint sb_irq(sb_t * sbh) -{ - osl_t *osh; - uint idx; - void *regs; - sbconfig_t *sb; - uint32 flag, sbipsflag; - uint irq = 0; - - osh = sb_osh(sbh); - flag = sb_getflag(sbh); - - idx = sb_coreidx(sbh); - - if ((regs = sb_setcore(sbh, SB_MIPS, 0)) || - (regs = sb_setcore(sbh, SB_MIPS33, 0))) { - sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF); - - /* sbipsflag specifies which core is routed to interrupts 1 to 4 */ - sbipsflag = R_REG(osh, &sb->sbipsflag); - for (irq = 1; irq <= 4; irq++) { - if (((sbipsflag & sbips_int_mask[irq]) >> - sbips_int_shift[irq]) == flag) - break; - } - if (irq == 5) - irq = 0; - } - - sb_setcoreidx(sbh, idx); - - return irq; -} - -/* Clears the specified MIPS IRQ. */ -static void BCMINITFN(sb_clearirq) (sb_t * sbh, uint irq) { - osl_t *osh; - void *regs; - sbconfig_t *sb; - - osh = sb_osh(sbh); - - if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) && - !(regs = sb_setcore(sbh, SB_MIPS33, 0))) - ASSERT(regs); - sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF); - - if (irq == 0) - W_REG(osh, &sb->sbintvec, 0); - else - OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]); -} - -/* - * Assigns the specified MIPS IRQ to the specified core. Shared MIPS - * IRQ 0 may be assigned more than once. - * - * The old assignment to the specified core is removed first. - */ -static void -BCMINITFN(sb_setirq) (sb_t * sbh, uint irq, uint coreid, uint coreunit) { - osl_t *osh; - void *regs; - sbconfig_t *sb; - uint32 flag; - uint oldirq; - - osh = sb_osh(sbh); - - regs = sb_setcore(sbh, coreid, coreunit); - ASSERT(regs); - flag = sb_getflag(sbh); - oldirq = sb_irq(sbh); - if (oldirq) - sb_clearirq(sbh, oldirq); - - if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) && - !(regs = sb_setcore(sbh, SB_MIPS33, 0))) - ASSERT(regs); - sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF); - - if (!oldirq) - AND_REG(osh, &sb->sbintvec, ~(1 << flag)); - - if (irq == 0) - OR_REG(osh, &sb->sbintvec, 1 << flag); - else { - flag <<= sbips_int_shift[irq]; - ASSERT(!(flag & ~sbips_int_mask[irq])); - flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq]; - W_REG(osh, &sb->sbipsflag, flag); - } -} - -/* - * Initializes clocks and interrupts. SB and NVRAM access must be - * initialized prior to calling. - * - * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero. - */ -void BCMINITFN(sb_mips_init) (sb_t * sbh, uint shirqmap) { - osl_t *osh; - ulong hz, ns, tmp; - extifregs_t *eir; - chipcregs_t *cc; - char *value; - uint irq; - - osh = sb_osh(sbh); - - /* Figure out current SB clock speed */ - if ((hz = sb_clock(sbh)) == 0) - hz = 100000000; - ns = 1000000000 / hz; - - /* Setup external interface timing */ - if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) { - /* Initialize extif so we can get to the LEDs and external UART */ - W_REG(osh, &eir->prog_config, CF_EN); - - /* Set timing for the flash */ - tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */ - tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */ - tmp = tmp | CEIL(120, ns); /* W0 = 120nS */ - W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */ - - /* Set programmable interface timing for external uart */ - tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */ - tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */ - tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */ - tmp = tmp | CEIL(120, ns); /* W0 = 120nS */ - W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */ - } else if ((cc = sb_setcore(sbh, SB_CC, 0))) { - /* Set timing for the flash */ - tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */ - tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */ - tmp |= CEIL(120, ns); /* W0 = 120nS */ - if ((sb_corerev(sbh) < 9) || (sb_chip(sbh) == 0x5365)) - W_REG(osh, &cc->flash_waitcount, tmp); - - if ((sb_corerev(sbh) < 9) || - ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) - || (sb_chip(sbh) == 0x5365)) { - W_REG(osh, &cc->pcmcia_memwait, tmp); - } - - /* Save shared IRQ mapping base */ - shirq_map_base = shirqmap; - } - - /* Chip specific initialization */ - switch (sb_chip(sbh)) { - case BCM4710_CHIP_ID: - /* Clear interrupt map */ - for (irq = 0; irq <= 4; irq++) - sb_clearirq(sbh, irq); - sb_setirq(sbh, 0, SB_CODEC, 0); - sb_setirq(sbh, 0, SB_EXTIF, 0); - sb_setirq(sbh, 2, SB_ENET, 1); - sb_setirq(sbh, 3, SB_ILINE20, 0); - sb_setirq(sbh, 4, SB_PCI, 0); - ASSERT(eir); - value = nvram_get("et0phyaddr"); - if (value && !strcmp(value, "31")) { - /* Enable internal UART */ - W_REG(osh, &eir->corecontrol, CC_UE); - /* Give USB its own interrupt */ - sb_setirq(sbh, 1, SB_USB, 0); - } else { - /* Disable internal UART */ - W_REG(osh, &eir->corecontrol, 0); - /* Give Ethernet its own interrupt */ - sb_setirq(sbh, 1, SB_ENET, 0); - sb_setirq(sbh, 0, SB_USB, 0); - } - break; - case BCM5350_CHIP_ID: - /* Clear interrupt map */ - for (irq = 0; irq <= 4; irq++) - sb_clearirq(sbh, irq); - sb_setirq(sbh, 0, SB_CC, 0); - sb_setirq(sbh, 0, SB_MIPS33, 0); - sb_setirq(sbh, 1, SB_D11, 0); - sb_setirq(sbh, 2, SB_ENET, 0); - sb_setirq(sbh, 3, SB_PCI, 0); - sb_setirq(sbh, 4, SB_USB, 0); - break; - case BCM4785_CHIP_ID: - /* Reassign PCI to irq 4 */ - sb_setirq(sbh, 4, SB_PCI, 0); - break; - } -} - -uint32 -BCMINITFN(sb_cpu_clock)(sb_t *sbh) -{ - extifregs_t *eir; - chipcregs_t *cc; - uint32 n, m; - uint idx; - uint32 pll_type, rate = 0; - - /* get index of the current core */ - idx = sb_coreidx(sbh); - pll_type = PLL_TYPE1; - - /* switch to extif or chipc core */ - if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) { - n = R_REG(osh, &eir->clockcontrol_n); - m = R_REG(osh, &eir->clockcontrol_sb); - } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) { - /* 5354 chip uses a non programmable PLL of frequency 240MHz */ - if (sb_chip(sbh) == BCM5354_CHIP_ID) { - rate = 240000000; - goto out; - } - pll_type = R_REG(osh, &cc->capabilities) & CC_CAP_PLL_MASK; - n = R_REG(osh, &cc->clockcontrol_n); - if ((pll_type == PLL_TYPE2) || - (pll_type == PLL_TYPE4) || - (pll_type == PLL_TYPE6) || (pll_type == PLL_TYPE7)) - m = R_REG(osh, &cc->clockcontrol_m3); - else if (pll_type == PLL_TYPE5) { - rate = 200000000; - goto out; - } else if (pll_type == PLL_TYPE3) { - if (sb_chip(sbh) == BCM5365_CHIP_ID) { - rate = 200000000; - goto out; - } - /* 5350 uses m2 to control mips */ - else - m = R_REG(osh, &cc->clockcontrol_m2); - } else - m = R_REG(osh, &cc->clockcontrol_sb); - } else - goto out; - - /* calculate rate */ - if (sb_chip(sbh) == 0x5365) - rate = 100000000; - else - rate = sb_clock_rate(pll_type, n, m); - - if (pll_type == PLL_TYPE6) - rate = SB2MIPS_T6(rate); - - out: - /* switch back to previous core */ - sb_setcoreidx(sbh, idx); - - return rate; -} - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) - -static void BCMINITFN(handler) (void) { - __asm__(".set\tmips32\n\t" "ssnop\n\t" "ssnop\n\t" - /* Disable interrupts */ - /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */ - "mfc0 $15, $12\n\t" - /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */ - "li $14, -31746\n\t" - "and $15, $15, $14\n\t" - "mtc0 $15, $12\n\t" "eret\n\t" "nop\n\t" "nop\n\t" - ".set\tmips0"); -} - -/* The following MUST come right after handler() */ -static void BCMINITFN(afterhandler) (void) { -} - -/* - * Set the MIPS, backplane and PCI clocks as closely as possible. - * - * MIPS clocks synchronization function has been moved from PLL in chipcommon - * core rev. 15 to a DLL inside the MIPS core in 4785. - */ -bool -BCMINITFN(sb_mips_setclock) (sb_t * sbh, uint32 mipsclock, uint32 sbclock, - uint32 pciclock) { - extifregs_t *eir = NULL; - chipcregs_t *cc = NULL; - mipsregs_t *mipsr = NULL; - volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, - *clockcontrol_m2; - uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, - orig_ratio_cfg; - uint32 pll_type, sync_mode; - uint ic_size, ic_lsize; - uint idx, i; - - /* PLL configuration: type 1 */ - typedef struct { - uint32 mipsclock; - uint16 n; - uint32 sb; - uint32 pci33; - uint32 pci25; - } n3m_table_t; - static n3m_table_t BCMINITDATA(type1_table)[] = { - /* 96.000 32.000 24.000 */ - { - 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011}, - /* 100.000 33.333 25.000 */ - { - 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011}, - /* 104.000 31.200 24.960 */ - { - 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009}, - /* 108.000 32.400 24.923 */ - { - 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802}, - /* 112.000 32.000 24.889 */ - { - 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403}, - /* 115.200 32.000 24.000 */ - { - 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011}, - /* 120.000 30.000 24.000 */ - { - 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011}, - /* 124.800 31.200 24.960 */ - { - 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009}, - /* 128.000 32.000 24.000 */ - { - 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305}, - /* 132.000 33.000 24.750 */ - { - 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305}, - /* 136.000 32.640 24.727 */ - { - 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603}, - /* 140.000 30.000 24.706 */ - { - 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02}, - /* 144.000 30.857 24.686 */ - { - 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021}, - /* 150.857 33.000 24.000 */ - { - 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605}, - /* 152.000 32.571 24.000 */ - { - 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02}, - /* 156.000 31.200 24.960 */ - { - 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009}, - /* 160.000 32.000 24.000 */ - { - 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309}, - /* 163.200 32.640 24.727 */ - { - 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603}, - /* 168.000 32.000 24.889 */ - { - 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403}, - /* 176.000 33.000 24.000 */ - { - 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602},}; - - /* PLL configuration: type 3 */ - typedef struct { - uint32 mipsclock; - uint16 n; - uint32 m2; /* that is the clockcontrol_m2 */ - } type3_table_t; - static type3_table_t type3_table[] = { - /* for 5350, mips clock is always double sb clock */ - {150000000, 0x311, 0x4020005}, - {200000000, 0x311, 0x4020003}, - }; - - /* PLL configuration: type 2, 4, 7 */ - typedef struct { - uint32 mipsclock; - uint32 sbclock; - uint32 pciclock; - uint16 n; - uint32 sb; - uint32 pci33; - uint32 m2; - uint32 m3; - uint32 ratio_cfg; - uint32 ratio_parm; - uint32 d11_r1; - uint32 d11_r2; - } n4m_table_t; - static n4m_table_t BCMINITDATA(type2_table)[] = { - { - 120000000, 60000000, 32000000, 0x0303, 0x01000200, - 0x01000600, 0x01000200, 0x05000200, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 150000000, 75000000, 33333333, 0x0303, 0x01000100, - 0x01000600, 0x01000100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 180000000, 80000000, 30000000, 0x0403, 0x01010000, - 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 180000000, 90000000, 30000000, 0x0403, 0x01000100, - 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 200000000, 100000000, 33333333, 0x0303, 0x02010000, - 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 211200000, 105600000, 30171428, 0x0902, 0x01000200, - 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 220800000, 110400000, 31542857, 0x1500, 0x01000200, - 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 230400000, 115200000, 32000000, 0x0604, 0x01000200, - 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 234000000, 104000000, 31200000, 0x0b01, 0x01010000, - 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 240000000, 120000000, 33333333, 0x0803, 0x01000200, - 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 252000000, 126000000, 33333333, 0x0504, 0x01000100, - 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 264000000, 132000000, 33000000, 0x0903, 0x01000200, - 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 270000000, 120000000, 30000000, 0x0703, 0x01010000, - 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 276000000, 122666666, 31542857, 0x1500, 0x01010000, - 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 280000000, 140000000, 31111111, 0x0503, 0x01000000, - 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 288000000, 128000000, 32914285, 0x0604, 0x01010000, - 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 288000000, 144000000, 32000000, 0x0404, 0x01000000, - 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 300000000, 133333333, 33333333, 0x0803, 0x01010000, - 0x01020600, 0x01010100, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 300000000, 133333333, 37500000, 0x0803, 0x01010000, - 0x01020500, 0x01010100, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 300000000, 133333333, 42857142, 0x0803, 0x01010000, - 0x01020400, 0x01010100, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 300000000, 133333333, 50000000, 0x0803, 0x01010000, - 0x01020300, 0x01010100, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 300000000, 133333333, 60000000, 0x0803, 0x01010000, - 0x01020200, 0x01010100, 0x05000100, 8, 0x012a00a9, - 9 /* ratio 4/9 */ , - 0x012a00a9}, { - 300000000, 150000000, 33333333, 0x0803, 0x01000100, - 0x01020600, 0x01010100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 300000000, 150000000, 37500000, 0x0803, 0x01000100, - 0x01020500, 0x01010100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 300000000, 150000000, 42857142, 0x0803, 0x01000100, - 0x01020400, 0x01010100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 300000000, 150000000, 50000000, 0x0803, 0x01000100, - 0x01020300, 0x01010100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 300000000, 150000000, 60000000, 0x0803, 0x01000100, - 0x01020200, 0x01010100, 0x05000100, 11, 0x0aaa0555, - 8 /* ratio 4/8 */ , - 0x00aa0055}, { - 330000000, 132000000, 33000000, 0x0903, 0x01000200, - 0x00020200, 0x01010100, 0x05000100, 0, 0, - 10 /* ratio 4/10 */ , 0x02520129}, - { - 330000000, 146666666, 33000000, 0x0903, 0x01010000, - 0x00020200, 0x01010100, 0x05000100, 0, 0, - 9 /* ratio 4/9 */ , 0x012a00a9}, - { - 330000000, 165000000, 33000000, 0x0903, 0x01000100, - 0x00020200, 0x01010100, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - { - 330000000, 165000000, 41250000, 0x0903, 0x01000100, - 0x00020100, 0x01010100, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - { - 330000000, 165000000, 55000000, 0x0903, 0x01000100, - 0x00020000, 0x01010100, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - { - 360000000, 120000000, 32000000, 0x0a03, 0x01000300, - 0x00010201, 0x01010200, 0x05000100, 0, 0, - 12 /* ratio 4/12 */ , 0x04920492}, - { - 360000000, 144000000, 32000000, 0x0a03, 0x01000200, - 0x00010201, 0x01010200, 0x05000100, 0, 0, - 10 /* ratio 4/10 */ , 0x02520129}, - { - 360000000, 160000000, 32000000, 0x0a03, 0x01010000, - 0x00010201, 0x01010200, 0x05000100, 0, 0, - 9 /* ratio 4/9 */ , 0x012a00a9}, - { - 360000000, 180000000, 32000000, 0x0a03, 0x01000100, - 0x00010201, 0x01010200, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - { - 360000000, 180000000, 40000000, 0x0a03, 0x01000100, - 0x00010101, 0x01010200, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - { - 360000000, 180000000, 53333333, 0x0a03, 0x01000100, - 0x00010001, 0x01010200, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - { - 390000000, 130000000, 32500000, 0x0b03, 0x01010100, - 0x00020101, 0x01020100, 0x05000100, 0, 0, - 12 /* ratio 4/12 */ , 0x04920492}, - { - 390000000, 156000000, 32500000, 0x0b03, 0x01000200, - 0x00020101, 0x01020100, 0x05000100, 0, 0, - 10 /* ratio 4/10 */ , 0x02520129}, - { - 390000000, 173000000, 32500000, 0x0b03, 0x01010000, - 0x00020101, 0x01020100, 0x05000100, 0, 0, - 9 /* ratio 4/9 */ , 0x012a00a9}, - { - 390000000, 195000000, 32500000, 0x0b03, 0x01000100, - 0x00020101, 0x01020100, 0x05000100, 0, 0, - 8 /* ratio 4/8 */ , 0x00aa0055}, - }; - static n4m_table_t BCMINITDATA(type4_table)[] = { - { - 120000000, 60000000, 0, 0x0009, 0x11020009, 0x01030203, - 0x11020009, 0x04000009, 11, 0x0aaa0555}, { - 150000000, 75000000, 0, 0x0009, 0x11050002, 0x01030203, - 0x11050002, 0x04000005, 11, 0x0aaa0555}, { - 192000000, 96000000, 0, 0x0702, 0x04000011, 0x11030011, - 0x04000011, 0x04000003, 11, 0x0aaa0555}, { - 198000000, 99000000, 0, 0x0603, 0x11020005, 0x11030011, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 200000000, 100000000, 0, 0x0009, 0x04020011, 0x11030011, - 0x04020011, 0x04020003, 11, 0x0aaa0555}, { - 204000000, 102000000, 0, 0x0c02, 0x11020005, 0x01030303, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 208000000, 104000000, 0, 0x0802, 0x11030002, 0x11090005, - 0x11030002, 0x04000003, 11, 0x0aaa0555}, { - 210000000, 105000000, 0, 0x0209, 0x11020005, 0x01030303, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 216000000, 108000000, 0, 0x0111, 0x11020005, 0x01030303, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 224000000, 112000000, 0, 0x0205, 0x11030002, 0x02002103, - 0x11030002, 0x04000003, 11, 0x0aaa0555}, { - 228000000, 101333333, 0, 0x0e02, 0x11030003, 0x11210005, - 0x01030305, 0x04000005, 8, 0x012a00a9}, { - 228000000, 114000000, 0, 0x0e02, 0x11020005, 0x11210005, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 240000000, 102857143, 0, 0x0109, 0x04000021, 0x01050203, - 0x11030021, 0x04000003, 13, 0x254a14a9}, { - 240000000, 120000000, 0, 0x0109, 0x11030002, 0x01050203, - 0x11030002, 0x04000003, 11, 0x0aaa0555}, { - 252000000, 100800000, 0, 0x0203, 0x04000009, 0x11050005, - 0x02000209, 0x04000002, 9, 0x02520129}, { - 252000000, 126000000, 0, 0x0203, 0x04000005, 0x11050005, - 0x04000005, 0x04000002, 11, 0x0aaa0555}, { - 264000000, 132000000, 0, 0x0602, 0x04000005, 0x11050005, - 0x04000005, 0x04000002, 11, 0x0aaa0555}, { - 272000000, 116571428, 0, 0x0c02, 0x04000021, 0x02000909, - 0x02000221, 0x04000003, 13, 0x254a14a9}, { - 280000000, 120000000, 0, 0x0209, 0x04000021, 0x01030303, - 0x02000221, 0x04000003, 13, 0x254a14a9}, { - 288000000, 123428571, 0, 0x0111, 0x04000021, 0x01030303, - 0x02000221, 0x04000003, 13, 0x254a14a9}, { - 300000000, 120000000, 0, 0x0009, 0x04000009, 0x01030203, - 0x02000902, 0x04000002, 9, 0x02520129}, { - 300000000, 150000000, 0, 0x0009, 0x04000005, 0x01030203, - 0x04000005, 0x04000002, 11, 0x0aaa0555} - }; - static n4m_table_t BCMINITDATA(type7_table)[] = { - { - 183333333, 91666666, 0, 0x0605, 0x04000011, 0x11030011, - 0x04000011, 0x04000003, 11, 0x0aaa0555}, { - 187500000, 93750000, 0, 0x0a03, 0x04000011, 0x11030011, - 0x04000011, 0x04000003, 11, 0x0aaa0555}, { - 196875000, 98437500, 0, 0x1003, 0x11020005, 0x11050011, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 200000000, 100000000, 0, 0x0311, 0x04000011, 0x11030011, - 0x04000009, 0x04000003, 11, 0x0aaa0555}, { - 200000000, 100000000, 0, 0x0311, 0x04020011, 0x11030011, - 0x04020011, 0x04020003, 11, 0x0aaa0555}, { - 206250000, 103125000, 0, 0x1103, 0x11020005, 0x11050011, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 212500000, 106250000, 0, 0x0c05, 0x11020005, 0x01030303, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 215625000, 107812500, 0, 0x1203, 0x11090009, 0x11050005, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 216666666, 108333333, 0, 0x0805, 0x11020003, 0x11030011, - 0x11020003, 0x04000003, 11, 0x0aaa0555}, { - 225000000, 112500000, 0, 0x0d03, 0x11020003, 0x11030011, - 0x11020003, 0x04000003, 11, 0x0aaa0555}, { - 233333333, 116666666, 0, 0x0905, 0x11020003, 0x11030011, - 0x11020003, 0x04000003, 11, 0x0aaa0555}, { - 237500000, 118750000, 0, 0x0e05, 0x11020005, 0x11210005, - 0x11020005, 0x04000005, 11, 0x0aaa0555}, { - 240000000, 120000000, 0, 0x0b11, 0x11020009, 0x11210009, - 0x11020009, 0x04000009, 11, 0x0aaa0555}, { - 250000000, 125000000, 0, 0x0f03, 0x11020003, 0x11210003, - 0x11020003, 0x04000003, 11, 0x0aaa0555} - }; - - ulong start, end, dst; - bool ret = FALSE; - - volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008; - volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010; - volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018; - - /* get index of the current core */ - idx = sb_coreidx(sbh); - clockcontrol_m2 = NULL; - - /* switch to chipc core */ - /* switch to extif or chipc core */ - if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) { - pll_type = PLL_TYPE1; - clockcontrol_n = &eir->clockcontrol_n; - clockcontrol_sb = &eir->clockcontrol_sb; - clockcontrol_pci = &eir->clockcontrol_pci; - clockcontrol_m2 = &cc->clockcontrol_m2; - } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) { - /* 5354 chipcommon pll setting can't be changed. - * The PMU on power up comes up with the default clk frequency - * of 240MHz - */ - if (sb_chip(sbh) == BCM5354_CHIP_ID) { - ret = TRUE; - goto done; - } - pll_type = R_REG(osh, &cc->capabilities) & CC_CAP_PLL_MASK; - if (pll_type == PLL_TYPE6) { - clockcontrol_n = NULL; - clockcontrol_sb = NULL; - clockcontrol_pci = NULL; - } else { - clockcontrol_n = &cc->clockcontrol_n; - clockcontrol_sb = &cc->clockcontrol_sb; - clockcontrol_pci = &cc->clockcontrol_pci; - clockcontrol_m2 = &cc->clockcontrol_m2; - } - } else - goto done; - - if (pll_type == PLL_TYPE6) { - /* Silence compilers */ - orig_n = orig_sb = orig_pci = 0; - } else { - /* Store the current clock register values */ - orig_n = R_REG(osh, clockcontrol_n); - orig_sb = R_REG(osh, clockcontrol_sb); - orig_pci = R_REG(osh, clockcontrol_pci); - } - - if (pll_type == PLL_TYPE1) { - /* Keep the current PCI clock if not specified */ - if (pciclock == 0) { - pciclock = - sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n), - R_REG(osh, clockcontrol_pci)); - pciclock = (pciclock <= 25000000) ? 25000000 : 33000000; - } - - /* Search for the closest MIPS clock less than or equal to a preferred value */ - for (i = 0; i < ARRAYSIZE(type1_table); i++) { - ASSERT(type1_table[i].mipsclock == - sb_clock_rate(pll_type, type1_table[i].n, - type1_table[i].sb)); - if (type1_table[i].mipsclock > mipsclock) - break; - } - if (i == 0) { - ret = FALSE; - goto done; - } else { - ret = TRUE; - i--; - } - ASSERT(type1_table[i].mipsclock <= mipsclock); - - /* No PLL change */ - if ((orig_n == type1_table[i].n) && - (orig_sb == type1_table[i].sb) && - (orig_pci == type1_table[i].pci33)) - goto done; - - /* Set the PLL controls */ - W_REG(osh, clockcontrol_n, type1_table[i].n); - W_REG(osh, clockcontrol_sb, type1_table[i].sb); - if (pciclock == 25000000) - W_REG(osh, clockcontrol_pci, type1_table[i].pci25); - else - W_REG(osh, clockcontrol_pci, type1_table[i].pci33); - - /* Reset */ - sb_watchdog(sbh, 1); - while (1) ; - } else if (pll_type == PLL_TYPE3) { - /* 5350 */ - if (sb_chip(sbh) != BCM5365_CHIP_ID) { - /* - * Search for the closest MIPS clock less than or equal to - * a preferred value. - */ - for (i = 0; i < ARRAYSIZE(type3_table); i++) { - if (type3_table[i].mipsclock > mipsclock) - break; - } - if (i == 0) { - ret = FALSE; - goto done; - } else { - ret = TRUE; - i--; - } - ASSERT(type3_table[i].mipsclock <= mipsclock); - - /* No PLL change */ - orig_m2 = R_REG(osh, &cc->clockcontrol_m2); - if ((orig_n == type3_table[i].n) - && (orig_m2 == type3_table[i].m2)) { - goto done; - } - - /* Set the PLL controls */ - W_REG(osh, clockcontrol_n, type3_table[i].n); - W_REG(osh, clockcontrol_m2, type3_table[i].m2); - - /* Reset */ - sb_watchdog(sbh, 1); - while (1) ; - } - } else if ((pll_type == PLL_TYPE2) || - (pll_type == PLL_TYPE4) || - (pll_type == PLL_TYPE6) || (pll_type == PLL_TYPE7)) { - n4m_table_t *table = NULL, *te; - uint tabsz = 0; - - ASSERT(cc); - - orig_mips = R_REG(osh, &cc->clockcontrol_m3); - - switch (pll_type) { - case PLL_TYPE6: - { - uint32 new_mips = 0; - - ret = TRUE; - if (mipsclock <= SB2MIPS_T6(CC_T6_M1)) - new_mips = CC_T6_MMASK; - - if (orig_mips == new_mips) - goto done; - - W_REG(osh, &cc->clockcontrol_m3, new_mips); - goto end_fill; - } - case PLL_TYPE2: - table = type2_table; - tabsz = ARRAYSIZE(type2_table); - break; - case PLL_TYPE4: - table = type4_table; - tabsz = ARRAYSIZE(type4_table); - break; - case PLL_TYPE7: - table = type7_table; - tabsz = ARRAYSIZE(type7_table); - break; - default: - ASSERT("No table for plltype" == NULL); - break; - } - - /* Store the current clock register values */ - orig_m2 = R_REG(osh, &cc->clockcontrol_m2); - orig_ratio_parm = 0; - orig_ratio_cfg = 0; - - /* Look up current ratio */ - for (i = 0; i < tabsz; i++) { - if ((orig_n == table[i].n) && - (orig_sb == table[i].sb) && - (orig_pci == table[i].pci33) && - (orig_m2 == table[i].m2) - && (orig_mips == table[i].m3)) { - orig_ratio_parm = table[i].ratio_parm; - orig_ratio_cfg = table[i].ratio_cfg; - break; - } - } - - /* Search for the closest MIPS clock greater or equal to a preferred value */ - for (i = 0; i < tabsz; i++) { - ASSERT(table[i].mipsclock == - sb_clock_rate(pll_type, table[i].n, - table[i].m3)); - if ((mipsclock <= table[i].mipsclock) - && ((sbclock == 0) || (sbclock <= table[i].sbclock)) - && ((pciclock == 0) - || (pciclock <= table[i].pciclock))) - break; - } - if (i == tabsz) { - ret = FALSE; - goto done; - } else { - te = &table[i]; - ret = TRUE; - } - - /* No PLL change */ - if ((orig_n == te->n) && - (orig_sb == te->sb) && - (orig_pci == te->pci33) && - (orig_m2 == te->m2) && (orig_mips == te->m3)) - goto done; - - /* Set the PLL controls */ - W_REG(osh, clockcontrol_n, te->n); - W_REG(osh, clockcontrol_sb, te->sb); - W_REG(osh, clockcontrol_pci, te->pci33); - W_REG(osh, &cc->clockcontrol_m2, te->m2); - W_REG(osh, &cc->clockcontrol_m3, te->m3); - - /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */ - if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) && - (sb_clock_rate(pll_type, te->n, te->m2) == 120000000)) - W_REG(osh, &cc->chipcontrol, - R_REG(osh, &cc->chipcontrol) | 0x100); - - /* No ratio change */ - if (sb_chip(sbh) != BCM4785_CHIP_ID) { - if (orig_ratio_parm == te->ratio_parm) - goto end_fill; - } - - /* Preload the code into the cache */ - icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize); - if (sb_chip(sbh) == BCM4785_CHIP_ID) { - start = ((ulong) && start_fill_4785) & ~(ic_lsize - 1); - end = ((ulong) - && end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - - 1); - } else { - start = ((ulong) && start_fill) & ~(ic_lsize - 1); - end = ((ulong) - && end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1); - } - while (start < end) { - cache_op(start, Fill_I); - start += ic_lsize; - } - - /* 4785 clock freq change procedures */ - if (sb_chip(sbh) == BCM4785_CHIP_ID) { - start_fill_4785: - /* Switch to async */ - MTC0(C0_BROADCOM, 4, (1 << 22)); - - /* Set clock ratio in MIPS */ - *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1); - *dll_r2 = te->d11_r2; - - /* Enable new settings in MIPS */ - *dll_r1 = *dll_r1 | 0xc0000000; - - /* Set active cfg */ - MTC0(C0_BROADCOM, 2, - MFC0(C0_BROADCOM, 2) | (1 << 3) | 1); - - /* Fake soft reset (clock cfg registers not reset) */ - MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2)); - - /* Clear active cfg */ - MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3)); - - /* set watchdog timer */ - W_REG(osh, &cc->watchdog, 20); - (void)R_REG(osh, &cc->chipid); - - /* wait for timer interrupt */ - __asm__ __volatile__(".set\tmips3\n\t" - "sync\n\t" "wait\n\t" - ".set\tmips0"); - end_fill_4785: - while (1) ; - } - /* Generic clock freq change procedures */ - else { - /* Copy the handler */ - start = (ulong) & handler; - end = (ulong) & afterhandler; - dst = KSEG1ADDR(0x180); - for (i = 0; i < (end - start); i += 4) - *((ulong *) (dst + i)) = - *((ulong *) (start + i)); - - /* Preload the handler into the cache one line at a time */ - for (i = 0; i < (end - start); i += ic_lsize) - cache_op(dst + i, Fill_I); - - /* Clear BEV bit */ - MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV); - - /* Enable interrupts */ - MTC0(C0_STATUS, 0, - MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE)); - - /* Enable MIPS timer interrupt */ - if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) && - !(mipsr = sb_setcore(sbh, SB_MIPS33, 0))) - ASSERT(mipsr); - W_REG(osh, &mipsr->intmask, 1); - - start_fill: - /* step 1, set clock ratios */ - MTC0(C0_BROADCOM, 3, te->ratio_parm); - MTC0(C0_BROADCOM, 1, te->ratio_cfg); - - /* step 2: program timer intr */ - W_REG(osh, &mipsr->timer, 100); - (void)R_REG(osh, &mipsr->timer); - - /* step 3, switch to async */ - sync_mode = MFC0(C0_BROADCOM, 4); - MTC0(C0_BROADCOM, 4, 1 << 22); - - /* step 4, set cfg active */ - MTC0(C0_BROADCOM, 2, (1 << 3) | 1); - - /* steps 5 & 6 */ - __asm__ __volatile__(".set\tmips3\n\t" "wait\n\t" - ".set\tmips0"); - - /* step 7, clear cfg active */ - MTC0(C0_BROADCOM, 2, 0); - - /* Additional Step: set back to orig sync mode */ - MTC0(C0_BROADCOM, 4, sync_mode); - - /* step 8, fake soft reset */ - MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2)); - - end_fill: - /* set watchdog timer */ - W_REG(osh, &cc->watchdog, 20); - (void)R_REG(osh, &cc->chipid); - - /* wait for timer interrupt */ - __asm__ __volatile__(".set\tmips3\n\t" - "sync\n\t" "wait\n\t" - ".set\tmips0"); - while (1) ; - } - } - - done: - /* Enable 4785 DLL */ - if (sb_chip(sbh) == BCM4785_CHIP_ID) { - uint32 tmp; - - /* set mask to 1e, enable DLL (bit 0) */ - *dll_ctrl |= 0x0041e021; - - /* enable aggressive hardware mode */ - *dll_ctrl |= 0x00000080; - - /* wait for lock flag to clear */ - while ((*dll_ctrl & 0x2) == 0) ; - - /* clear sticky flags (clear on write 1) */ - tmp = *dll_ctrl; - *dll_ctrl = tmp; - - /* set mask to 5b'10001 */ - *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000; - - /* enable sync mode */ - MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff); - (void)MFC0(C0_BROADCOM, 4); - } - - /* switch back to previous core */ - sb_setcoreidx(sbh, idx); - - return ret; -} - -void BCMINITFN(enable_pfc) (uint32 mode) { - ulong start, end; - uint ic_size, ic_lsize; - - /* If auto then choose the correct mode for this - * platform, currently we only ever select one mode - */ - if (mode == PFC_AUTO) - mode = PFC_INST; - - icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize); - - /* enable prefetch cache if available */ - if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) { - start = ((ulong) && setpfc_start) & ~(ic_lsize - 1); - end = ((ulong) - && setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1); - - /* Preload setpfc code into the cache one line at a time */ - while (start < end) { - cache_op(start, Fill_I); - start += ic_lsize; - } - - /* Now set the pfc */ - setpfc_start: - /* write range */ - *(volatile uint32 *)PFC_CR1 = 0xffff0000; - - /* enable */ - *(volatile uint32 *)PFC_CR0 = mode; - setpfc_end: - /* Compiler foder */ - ic_size = 0; - } -} - -/* returns the ncdl value to be programmed into sdram_ncdl for calibration */ -uint32 BCMINITFN(sb_memc_get_ncdl) (sb_t * sbh) { - osl_t *osh; - sbmemcregs_t *memc; - uint32 ret = 0; - uint32 config, rd, wr, misc, dqsg, cd, sm, sd; - uint idx, rev; - - osh = sb_osh(sbh); - - idx = sb_coreidx(sbh); - - memc = (sbmemcregs_t *) sb_setcore(sbh, SB_MEMC, 0); - if (memc == 0) - goto out; - - rev = sb_corerev(sbh); - - config = R_REG(osh, &memc->config); - wr = R_REG(osh, &memc->wrncdlcor); - rd = R_REG(osh, &memc->rdncdlcor); - misc = R_REG(osh, &memc->miscdlyctl); - dqsg = R_REG(osh, &memc->dqsgatencdl); - - rd &= MEMC_RDNCDLCOR_RD_MASK; - wr &= MEMC_WRNCDLCOR_WR_MASK; - dqsg &= MEMC_DQSGATENCDL_G_MASK; - - if (config & MEMC_CONFIG_DDR) { - ret = (wr << 16) | (rd << 8) | dqsg; - } else { - if (rev > 0) - cd = rd; - else - cd = (rd == - MEMC_CD_THRESHOLD) ? rd : (wr + - MEMC_CD_THRESHOLD); - sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT; - sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT; - ret = (sm << 16) | (sd << 8) | cd; - } - - out: - /* switch back to previous core */ - sb_setcoreidx(sbh, idx); - - return ret; -} - -void hnd_cpu_reset(sb_t * sbh) -{ - if (sb_chip(sbh) == BCM4785_CHIP_ID) - MTC0(C0_BROADCOM, 4, (1 << 22)); - sb_watchdog(sbh, 1); - if (sb_chip(sbh) == BCM4785_CHIP_ID) { - __asm__ __volatile__(".set\tmips3\n\t" - "sync\n\t" "wait\n\t" ".set\tmips0"); - } - while (1) ; -} - -#if defined(BCMPERFSTATS) -/* - * CP0 Register 25 supports 4 semi-independent 32bit performance counters. - * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?) - * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters - * $25 select 6 is the global perf control register. - */ -/* enable and start instruction counting */ - -void hndmips_perf_cyclecount_enable(void) -{ - MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */ - MTC0(C0_PERFORMANCE, 4, 0x8048 | MFC0(C0_PERFORMANCE, 4)); /* enable cycles counting for counter 0 */ - MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */ -} - -void hndmips_perf_instrcount_enable(void) -{ - MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */ - MTC0(C0_PERFORMANCE, 4, 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instructions counting for counter 0 */ - MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */ -} - -/* enable and start I$ hit and I$ miss counting */ -void hndmips_perf_icachecount_enable(void) -{ - MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */ - MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */ - MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */ - MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */ -} - -/* enable and start D$ hit and I$ miss counting */ -void hndmips_perf_dcachecount_enable(void) -{ - MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */ - MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */ - MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */ - MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */ -} - -void hndmips_perf_icache_miss_enable() -{ - MTC0(C0_PERFORMANCE, 4, 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */ - MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */ -} - -void hndmips_perf_icache_hit_enable() -{ - MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5)); - /* enable cache hits counting for counter 2 */ - MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */ -} - -uint32 hndmips_perf_read_instrcount() -{ - return -(long)(MFC0(C0_PERFORMANCE, 0)); -} - -uint32 hndmips_perf_read_cache_miss() -{ - return -(long)(MFC0(C0_PERFORMANCE, 1)); -} - -uint32 hndmips_perf_read_cache_hit() -{ - return -(long)(MFC0(C0_PERFORMANCE, 2)); -} - -#endif diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbpci.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbpci.c deleted file mode 100644 index c8846e7743..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbpci.c +++ /dev/null @@ -1,780 +0,0 @@ -/* - * Low-Level PCI and SB support for BCM47xx - * - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <typedefs.h> -#include <osl.h> -#include <pcicfg.h> -#include <bcmdevs.h> -#include <sbconfig.h> -#include <sbutils.h> -#include <sbpci.h> -#include <bcmendian.h> -#include <bcmnvram.h> -#include <hndcpu.h> -#include <hndmips.h> -#include <hndpci.h> - -/* debug/trace */ -#ifdef BCMDBG_PCI -#define PCI_MSG(args) printf args -#else -#define PCI_MSG(args) -#endif /* BCMDBG_PCI */ - -/* Can free sbpci_init() memory after boot */ -#ifndef linux -#define __init -#endif /* linux */ - -/* Emulated configuration space */ -typedef struct { - int n; - uint size0; - uint size1; - uint size2; - uint size3; -} sb_bar_cfg_t; -static pci_config_regs sb_config_regs[SB_MAXCORES]; -static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES]; - -/* Links to emulated and real PCI configuration spaces */ -#define MAXFUNCS 2 -typedef struct { - pci_config_regs *emu; /* emulated PCI config */ - pci_config_regs *pci; /* real PCI config */ - sb_bar_cfg_t *bar; /* region sizes */ -} sb_pci_cfg_t; -static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS]; - -/* Special emulated config space for non-existing device */ -static pci_config_regs sb_pci_null = { 0xffff, 0xffff }; - -/* Banned cores */ -static uint16 pci_ban[SB_MAXCORES] = { 0 }; -static uint pci_banned = 0; - -/* CardBus mode */ -static bool cardbus = FALSE; - -/* Disable PCI host core */ -static bool pci_disabled = FALSE; - -/* Host bridge slot #, default to 0 */ -static uint8 pci_hbslot = 0; - -/* Internal macros */ -#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */ -#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to - * access host bridge PCI cfg space - * from SB - */ - -/* - * Functions for accessing external PCI configuration space - */ - -/* Assume one-hot slot wiring */ -#define PCI_SLOT_MAX 16 /* Max. PCI Slots */ - -static uint32 config_cmd(sb_t * sbh, uint bus, uint dev, uint func, uint off) -{ - uint coreidx; - sbpciregs_t *regs; - uint32 addr = 0; - osl_t *osh; - - /* CardBusMode supports only one device */ - if (cardbus && dev > 1) - return 0; - - osh = sb_osh(sbh); - - coreidx = sb_coreidx(sbh); - regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0); - - /* Type 0 transaction */ - if (bus == 1) { - /* Skip unwired slots */ - if (dev < PCI_SLOT_MAX) { - uint32 win; - - /* Slide the PCI window to the appropriate slot */ - win = - (SBTOPCI_CFG0 | - ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK)); - W_REG(osh, ®s->sbtopci1, win); - addr = SB_PCI_CFG | - ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) | - (func << PCICFG_FUN_SHIFT) | (off & ~3); - } - } else { - /* Type 1 transaction */ - W_REG(osh, ®s->sbtopci1, SBTOPCI_CFG1); - addr = SB_PCI_CFG | - (bus << PCICFG_BUS_SHIFT) | - (dev << PCICFG_SLOT_SHIFT) | - (func << PCICFG_FUN_SHIFT) | (off & ~3); - } - - sb_setcoreidx(sbh, coreidx); - - return addr; -} - -/* - * Read host bridge PCI config registers from Silicon Backplane (>=rev8). - * - * It returns TRUE to indicate that access to the host bridge's pci config - * from SB is ok, and values in 'addr' and 'val' are valid. - * - * It can only read registers at multiple of 4-bytes. Callers must pick up - * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects - * the register address where value in 'val' is read. - */ -static bool -sb_pcihb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, - uint32 ** addr, uint32 * val) -{ - sbpciregs_t *regs; - osl_t *osh; - uint coreidx; - bool ret = FALSE; - - /* sanity check */ - ASSERT(bus == 1); - ASSERT(dev == pci_hbslot); - ASSERT(func == 0); - - osh = sb_osh(sbh); - - /* read pci config when core rev >= 8 */ - coreidx = sb_coreidx(sbh); - regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0); - if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) { - *addr = (uint32 *) & regs->pcicfg[func][off >> 2]; - *val = R_REG(osh, *addr); - ret = TRUE; - } - sb_setcoreidx(sbh, coreidx); - - return ret; -} - -int -extpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, - void *buf, int len) -{ - uint32 addr = 0, *reg = NULL, val; - int ret = 0; - - /* - * Set value to -1 when: - * flag 'pci_disabled' is true; - * value of 'addr' is zero; - * REG_MAP() fails; - * BUSPROBE() fails; - */ - if (pci_disabled) - val = 0xffffffff; - else if (bus == 1 && dev == pci_hbslot && func == 0 && - sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ; - else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) || - ((reg = (uint32 *) REG_MAP(addr, len)) == 0) || - (BUSPROBE(val, reg) != 0)) - val = 0xffffffff; - - PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n", - __FUNCTION__, val, reg, addr, len, off, buf)); - - val >>= 8 * (off & 3); - if (len == 4) - *((uint32 *) buf) = val; - else if (len == 2) - *((uint16 *) buf) = (uint16) val; - else if (len == 1) - *((uint8 *) buf) = (uint8) val; - else - ret = -1; - - if (reg && addr) - REG_UNMAP(reg); - - return ret; -} - -int -extpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, - void *buf, int len) -{ - osl_t *osh; - uint32 addr = 0, *reg = NULL, val; - int ret = 0; - - osh = sb_osh(sbh); - - /* - * Ignore write attempt when: - * flag 'pci_disabled' is true; - * value of 'addr' is zero; - * REG_MAP() fails; - * BUSPROBE() fails; - */ - if (pci_disabled) - return 0; - else if (bus == 1 && dev == pci_hbslot && func == 0 && - sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ; - else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) || - ((reg = (uint32 *) REG_MAP(addr, len)) == 0) || - (BUSPROBE(val, reg) != 0)) - goto done; - - if (len == 4) - val = *((uint32 *) buf); - else if (len == 2) { - val &= ~(0xffff << (8 * (off & 3))); - val |= *((uint16 *) buf) << (8 * (off & 3)); - } else if (len == 1) { - val &= ~(0xff << (8 * (off & 3))); - val |= *((uint8 *) buf) << (8 * (off & 3)); - } else { - ret = -1; - goto done; - } - - PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg)); - - W_REG(osh, reg, val); - - done: - if (reg && addr) - REG_UNMAP(reg); - - return ret; -} - -/* - * Must access emulated PCI configuration at these locations even when - * the real PCI config space exists and is accessible. - * - * PCI_CFG_VID (0x00) - * PCI_CFG_DID (0x02) - * PCI_CFG_PROGIF (0x09) - * PCI_CFG_SUBCL (0x0a) - * PCI_CFG_BASECL (0x0b) - * PCI_CFG_HDR (0x0e) - * PCI_CFG_INT (0x3c) - * PCI_CFG_PIN (0x3d) - */ -#define FORCE_EMUCFG(off, len) \ - ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \ - (off == PCI_CFG_PROGIF) || \ - (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \ - (off == PCI_CFG_HDR) || \ - (off == PCI_CFG_INT) || (off == PCI_CFG_PIN)) - -/* Sync the emulation registers and the real PCI config registers. */ -static void -sb_pcid_read_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg, - uint off, uint len) -{ - osl_t *osh; - uint oldidx; - - ASSERT(cfg); - ASSERT(cfg->emu); - ASSERT(cfg->pci); - - /* decide if real PCI config register access is necessary */ - if (FORCE_EMUCFG(off, len)) - return; - - osh = sb_osh(sbh); - - /* access to the real pci config space only when the core is up */ - oldidx = sb_coreidx(sbh); - sb_setcoreidx(sbh, coreidx); - if (sb_iscoreup(sbh)) { - if (len == 4) - *(uint32 *) ((ulong) cfg->emu + off) = - htol32(R_REG - (osh, (uint32 *) ((ulong) cfg->pci + off))); - else if (len == 2) - *(uint16 *) ((ulong) cfg->emu + off) = - htol16(R_REG - (osh, (uint16 *) ((ulong) cfg->pci + off))); - else if (len == 1) - *(uint8 *) ((ulong) cfg->emu + off) = - R_REG(osh, (uint8 *) ((ulong) cfg->pci + off)); - } - sb_setcoreidx(sbh, oldidx); -} - -static void -sb_pcid_write_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg, - uint off, uint len) -{ - osl_t *osh; - uint oldidx; - - ASSERT(cfg); - ASSERT(cfg->emu); - ASSERT(cfg->pci); - - osh = sb_osh(sbh); - - /* decide if real PCI config register access is necessary */ - if (FORCE_EMUCFG(off, len)) - return; - - /* access to the real pci config space only when the core is up */ - oldidx = sb_coreidx(sbh); - sb_setcoreidx(sbh, coreidx); - if (sb_iscoreup(sbh)) { - if (len == 4) - W_REG(osh, (uint32 *) ((ulong) cfg->pci + off), - ltoh32(*(uint32 *) ((ulong) cfg->emu + off))); - else if (len == 2) - W_REG(osh, (uint16 *) ((ulong) cfg->pci + off), - ltoh16(*(uint16 *) ((ulong) cfg->emu + off))); - else if (len == 1) - W_REG(osh, (uint8 *) ((ulong) cfg->pci + off), - *(uint8 *) ((ulong) cfg->emu + off)); - } - sb_setcoreidx(sbh, oldidx); -} - -/* - * Functions for accessing translated SB configuration space - */ -static int -sb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len) -{ - pci_config_regs *cfg; - - if (dev >= SB_MAXCORES || func >= MAXFUNCS - || (off + len) > sizeof(pci_config_regs)) - return -1; - cfg = sb_pci_cfg[dev][func].emu; - - ASSERT(ISALIGNED(off, len)); - ASSERT(ISALIGNED((uintptr) buf, len)); - - /* use special config space if the device does not exist */ - if (!cfg) - cfg = &sb_pci_null; - /* sync emulation with real PCI config if necessary */ - else if (sb_pci_cfg[dev][func].pci) - sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len); - - if (len == 4) - *((uint32 *) buf) = ltoh32(*((uint32 *) ((ulong) cfg + off))); - else if (len == 2) - *((uint16 *) buf) = ltoh16(*((uint16 *) ((ulong) cfg + off))); - else if (len == 1) - *((uint8 *) buf) = *((uint8 *) ((ulong) cfg + off)); - else - return -1; - - return 0; -} - -static int -sb_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf, - int len) -{ - uint coreidx; - void *regs; - pci_config_regs *cfg; - osl_t *osh; - sb_bar_cfg_t *bar; - - if (dev >= SB_MAXCORES || func >= MAXFUNCS - || (off + len) > sizeof(pci_config_regs)) - return -1; - cfg = sb_pci_cfg[dev][func].emu; - if (!cfg) - return -1; - - ASSERT(ISALIGNED(off, len)); - ASSERT(ISALIGNED((uintptr) buf, len)); - - osh = sb_osh(sbh); - - /* Emulate BAR sizing */ - if (off >= OFFSETOF(pci_config_regs, base[0]) && - off <= OFFSETOF(pci_config_regs, base[3]) && - len == 4 && *((uint32 *) buf) == ~0) { - coreidx = sb_coreidx(sbh); - if ((regs = sb_setcoreidx(sbh, dev))) { - bar = sb_pci_cfg[dev][func].bar; - /* Highest numbered address match register */ - if (off == OFFSETOF(pci_config_regs, base[0])) - cfg->base[0] = ~(bar->size0 - 1); - else if (off == OFFSETOF(pci_config_regs, base[1]) - && bar->n >= 1) - cfg->base[1] = ~(bar->size1 - 1); - else if (off == OFFSETOF(pci_config_regs, base[2]) - && bar->n >= 2) - cfg->base[2] = ~(bar->size2 - 1); - else if (off == OFFSETOF(pci_config_regs, base[3]) - && bar->n >= 3) - cfg->base[3] = ~(bar->size3 - 1); - } - sb_setcoreidx(sbh, coreidx); - } else if (len == 4) - *((uint32 *) ((ulong) cfg + off)) = htol32(*((uint32 *) buf)); - else if (len == 2) - *((uint16 *) ((ulong) cfg + off)) = htol16(*((uint16 *) buf)); - else if (len == 1) - *((uint8 *) ((ulong) cfg + off)) = *((uint8 *) buf); - else - return -1; - - /* sync emulation with real PCI config if necessary */ - if (sb_pci_cfg[dev][func].pci) - sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, - len); - - return 0; -} - -int -sbpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, - void *buf, int len) -{ - if (bus == 0) - return sb_read_config(sbh, bus, dev, func, off, buf, len); - else - return extpci_read_config(sbh, bus, dev, func, off, buf, len); -} - -int -sbpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, - void *buf, int len) -{ - if (bus == 0) - return sb_write_config(sbh, bus, dev, func, off, buf, len); - else - return extpci_write_config(sbh, bus, dev, func, off, buf, len); -} - -void sbpci_ban(uint16 core) -{ - if (pci_banned < ARRAYSIZE(pci_ban)) - pci_ban[pci_banned++] = core; -} - -/* - * Initiliaze PCI core. Return 0 after a successful initialization. - * Otherwise return -1 to indicate there is no PCI core and return 1 - * to indicate PCI core is disabled. - */ -int __init sbpci_init_pci(sb_t * sbh) -{ - uint chip, chiprev, chippkg, host; - uint32 boardflags; - sbpciregs_t *pci; - sbconfig_t *sb; - uint32 val; - int ret = 0; - char *hbslot; - osl_t *osh; - - chip = sb_chip(sbh); - chiprev = sb_chiprev(sbh); - chippkg = sb_chippkg(sbh); - - osh = sb_osh(sbh); - - if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) { - printk("PCI: no core\n"); - pci_disabled = TRUE; - return -1; - } - - if ((chip == 0x4310) && (chiprev == 0)) - pci_disabled = TRUE; - - sb = (sbconfig_t *) ((ulong) pci + SBCONFIGOFF); - - boardflags = (uint32) getintvar(NULL, "boardflags"); - - /* - * The 200-pin BCM4712 package does not bond out PCI. Even when - * PCI is bonded out, some boards may leave the pins - * floating. - */ - if (((chip == BCM4712_CHIP_ID) && - ((chippkg == BCM4712SMALL_PKG_ID) || - (chippkg == BCM4712MID_PKG_ID))) || (boardflags & BFL_NOPCI)) - pci_disabled = TRUE; - - /* Enable the core */ - sb_core_reset(sbh, 0, 0); - - /* - * If the PCI core should not be touched (disabled, not bonded - * out, or pins floating), do not even attempt to access core - * registers. Otherwise, try to determine if it is in host - * mode. - */ - if (pci_disabled) - host = 0; - else - host = !BUSPROBE(val, &pci->control); - - if (!host) { - ret = 1; - - /* Disable PCI interrupts in client mode */ - W_REG(osh, &sb->sbintvec, 0); - - /* Disable the PCI bridge in client mode */ - sbpci_ban(SB_PCI); - sb_core_disable(sbh, 0); - - printk("PCI: Disabled\n"); - } else { - printk("PCI: Initializing host\n"); - - /* Disable PCI SBReqeustTimeout for BCM4785 */ - if (chip == BCM4785_CHIP_ID) { - AND_REG(osh, &sb->sbimconfiglow, ~0x00000070); - sb_commit(sbh); - } - - /* Reset the external PCI bus and enable the clock */ - W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */ - W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */ - OSL_DELAY(150); /* delay > 100 us */ - W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */ - /* Use internal arbiter and park REQ/GRNT at external master 0 */ - W_REG(osh, &pci->arbcontrol, PCI_INT_ARB); - OSL_DELAY(1); /* delay 1 us */ - if (sb_corerev(sbh) >= 8) { - val = getintvar(NULL, "parkid"); - ASSERT(val <= PCI_PARKID_LAST); - OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT); - OSL_DELAY(1); - } - - /* Enable CardBusMode */ - cardbus = getintvar(NULL, "cardbus") == 1; - if (cardbus) { - printk("PCI: Enabling CardBus\n"); - /* GPIO 1 resets the CardBus device on bcm94710ap */ - sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY); - sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY); - W_REG(osh, &pci->sprom[0], - R_REG(osh, &pci->sprom[0]) | 0x400); - } - - /* 64 MB I/O access window */ - W_REG(osh, &pci->sbtopci0, SBTOPCI_IO); - /* 64 MB configuration access window */ - W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0); - /* 1 GB memory access window */ - W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA); - - /* Host bridge slot # nvram overwrite */ - if ((hbslot = nvram_get("pcihbslot"))) { - pci_hbslot = simple_strtoul(hbslot, NULL, 0); - ASSERT(pci_hbslot < PCI_MAX_DEVICES); - } - - /* Enable PCI bridge BAR0 prefetch and burst */ - val = 6; - sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, - sizeof(val)); - - /* Enable PCI interrupts */ - W_REG(osh, &pci->intmask, PCI_INTA); - } - - return ret; -} - -/* - * Get the PCI region address and size information. - */ -static void __init -sbpci_init_regions(sb_t * sbh, uint func, pci_config_regs * cfg, - sb_bar_cfg_t * bar) -{ - osl_t *osh; - uint16 coreid; - void *regs; - sbconfig_t *sb; - uint32 base; - - osh = sb_osh(sbh); - coreid = sb_coreid(sbh); - regs = sb_coreregs(sbh); - sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF); - - switch (coreid) { - case SB_USB20H: - base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0))); - - cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */ - cfg->base[1] = 0; - cfg->base[2] = 0; - cfg->base[3] = 0; - cfg->base[4] = 0; - cfg->base[5] = 0; - bar->n = 1; - bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */ - bar->size1 = 0; - bar->size2 = 0; - bar->size3 = 0; - break; - default: - cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0))); - cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1))); - cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2))); - cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3))); - cfg->base[4] = 0; - cfg->base[5] = 0; - bar->n = - (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> - SBIDL_AR_SHIFT; - bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0)); - bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1)); - bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2)); - bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3)); - break; - } -} - -/* - * Construct PCI config spaces for SB cores so that they - * can be accessed as if they were PCI devices. - */ -static void __init sbpci_init_cores(sb_t * sbh) -{ - uint chiprev, coreidx, i; - sbconfig_t *sb; - pci_config_regs *cfg, *pci; - sb_bar_cfg_t *bar; - void *regs; - osl_t *osh; - uint16 vendor, device; - uint16 coreid; - uint8 class, subclass, progif; - uint dev; - uint8 header; - uint func; - - chiprev = sb_chiprev(sbh); - coreidx = sb_coreidx(sbh); - - osh = sb_osh(sbh); - - /* Scan the SB bus */ - bzero(sb_config_regs, sizeof(sb_config_regs)); - bzero(sb_bar_cfg, sizeof(sb_bar_cfg)); - bzero(sb_pci_cfg, sizeof(sb_pci_cfg)); - memset(&sb_pci_null, -1, sizeof(sb_pci_null)); - cfg = sb_config_regs; - bar = sb_bar_cfg; - for (dev = 0; dev < SB_MAXCORES; dev++) { - /* Check if the core exists */ - if (!(regs = sb_setcoreidx(sbh, dev))) - continue; - sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF); - - /* Check if this core is banned */ - coreid = sb_coreid(sbh); - for (i = 0; i < pci_banned; i++) - if (coreid == pci_ban[i]) - break; - if (i < pci_banned) - continue; - - for (func = 0; func < MAXFUNCS; ++func) { - /* Make sure we won't go beyond the limit */ - if (cfg >= &sb_config_regs[SB_MAXCORES]) { - printk("PCI: too many emulated devices\n"); - goto done; - } - - /* Convert core id to pci id */ - if (sb_corepciid - (sbh, func, &vendor, &device, &class, &subclass, - &progif, &header)) - continue; - - /* - * Differentiate real PCI config from emulated. - * non zero 'pci' indicate there is a real PCI config space - * for this device. - */ - switch (device) { - case BCM47XX_GIGETH_ID: - pci = - (pci_config_regs *) ((uint32) regs + 0x800); - break; - case BCM47XX_SATAXOR_ID: - pci = - (pci_config_regs *) ((uint32) regs + 0x400); - break; - case BCM47XX_ATA100_ID: - pci = - (pci_config_regs *) ((uint32) regs + 0x800); - break; - default: - pci = NULL; - break; - } - /* Supported translations */ - cfg->vendor = htol16(vendor); - cfg->device = htol16(device); - cfg->rev_id = chiprev; - cfg->prog_if = progif; - cfg->sub_class = subclass; - cfg->base_class = class; - cfg->header_type = header; - sbpci_init_regions(sbh, func, cfg, bar); - /* Save core interrupt flag */ - cfg->int_pin = - R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK; - /* Save core interrupt assignment */ - cfg->int_line = sb_irq(sbh); - /* Indicate there is no SROM */ - *((uint32 *) & cfg->sprom_control) = 0xffffffff; - - /* Point to the PCI config spaces */ - sb_pci_cfg[dev][func].emu = cfg; - sb_pci_cfg[dev][func].pci = pci; - sb_pci_cfg[dev][func].bar = bar; - cfg++; - bar++; - } - } - - done: - sb_setcoreidx(sbh, coreidx); -} - -/* - * Initialize PCI core and construct PCI config spaces for SB cores. - * Must propagate sbpci_init_pci() return value to the caller to let - * them know the PCI core initialization status. - */ -int __init sbpci_init(sb_t * sbh) -{ - int status = sbpci_init_pci(sbh); - sbpci_init_cores(sbh); - return status; -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbutils.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbutils.c deleted file mode 100644 index 5c85dd7c9f..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sbutils.c +++ /dev/null @@ -1,4179 +0,0 @@ -/* - * Misc utility routines for accessing chip-specific features - * of the SiliconBackplane-based Broadcom chips. - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#include <typedefs.h> -#include <bcmdefs.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmdevs.h> -#include <sbconfig.h> -#include <sbchipc.h> -#include <sbextif.h> -#include <sbpci.h> -#include <sbpcie.h> -#include <pcicfg.h> -#include <sbpcmcia.h> -#include <sbsocram.h> -#include <bcmnvram.h> -#include <bcmsrom.h> -#include <hndpmu.h> - -/* debug/trace */ -#define SB_ERROR(args) - -#ifdef BCMDBG -#define SB_MSG(args) printf args -#else -#define SB_MSG(args) -#endif /* BCMDBG */ - -typedef uint32(*sb_intrsoff_t) (void *intr_arg); -typedef void (*sb_intrsrestore_t) (void *intr_arg, uint32 arg); -typedef bool(*sb_intrsenabled_t) (void *intr_arg); - -typedef struct gpioh_item { - void *arg; - bool level; - gpio_handler_t handler; - uint32 event; - struct gpioh_item *next; -} gpioh_item_t; - -/* misc sb info needed by some of the routines */ -typedef struct sb_info { - - struct sb_pub sb; /* back plane public state (must be first field) */ - - void *osh; /* osl os handle */ - void *sdh; /* bcmsdh handle */ - - void *curmap; /* current regs va */ - void *regs[SB_MAXCORES]; /* other regs va */ - - uint curidx; /* current core index */ - uint dev_coreid; /* the core provides driver functions */ - - bool memseg; /* flag to toggle MEM_SEG register */ - - uint gpioidx; /* gpio control core index */ - uint gpioid; /* gpio control coretype */ - - uint numcores; /* # discovered cores */ - uint coreid[SB_MAXCORES]; /* id of each core */ - - void *intr_arg; /* interrupt callback function arg */ - sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */ - sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */ - sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */ - - uint8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */ - bool pr42767_war; - uint8 pcie_polarity; - bool pcie_war_ovr; /* Override ASPM/Clkreq settings */ - - uint8 pmecap_offset; /* PM Capability offset in the config space */ - bool pmecap; /* Capable of generating PME */ - - gpioh_item_t *gpioh_head; /* GPIO event handlers list */ - - char *vars; - uint varsz; -} sb_info_t; - -/* local prototypes */ -static sb_info_t *sb_doattach(sb_info_t * si, uint devid, osl_t * osh, - void *regs, uint bustype, void *sdh, - char **vars, uint * varsz); -static void sb_scan(sb_info_t * si); -static uint _sb_coreidx(sb_info_t * si); -static uint sb_pcidev2chip(uint pcidev); -static uint sb_chip2numcores(uint chip); -static bool sb_ispcie(sb_info_t * si); -static uint8 sb_find_pci_capability(sb_info_t * si, uint8 req_cap_id, - uchar * buf, uint32 * buflen); -static int sb_pci_fixcfg(sb_info_t * si); -/* routines to access mdio slave device registers */ -static int sb_pcie_mdiowrite(sb_info_t * si, uint physmedia, uint readdr, - uint val); -static int sb_pcie_mdioread(sb_info_t * si, uint physmedia, uint readdr, - uint * ret_val); - -/* dev path concatenation util */ -static char *sb_devpathvar(sb_t * sbh, char *var, int len, const char *name); - -/* WARs */ -static void sb_war43448(sb_t * sbh); -static void sb_war43448_aspm(sb_t * sbh); -static void sb_war32414_forceHT(sb_t * sbh, bool forceHT); -static void sb_war30841(sb_info_t * si); -static void sb_war42767(sb_t * sbh); -static void sb_war42767_clkreq(sb_t * sbh); - -/* delay needed between the mdio control/ mdiodata register data access */ -#define PR28829_DELAY() OSL_DELAY(10) - -/* size that can take bitfielddump */ -#define BITFIELD_DUMP_SIZE 32 - -/* global variable to indicate reservation/release of gpio's */ -static uint32 sb_gpioreservation = 0; - -/* global flag to prevent shared resources from being initialized multiple times in sb_attach() */ -static bool sb_onetimeinit = FALSE; - -#define SB_INFO(sbh) (sb_info_t*)(uintptr)sbh -#define SET_SBREG(si, r, mask, val) \ - W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val))) -#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \ - ISALIGNED((x), SB_CORE_SIZE)) -#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE)) -#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF) -#define BADCOREADDR 0 -#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES) -#define BADIDX (SB_MAXCORES+1) -#define NOREV -1 /* Invalid rev */ - -#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI)) -#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE)) -#define PCMCIA(si) ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->memseg == TRUE)) - -/* sonicsrev */ -#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT) -#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT) - -#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr)) -#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v)) -#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v))) -#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v))) - -/* - * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ - * after core switching to avoid invalid register accesss inside ISR. - */ -#define INTR_OFF(si, intr_val) \ - if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ - intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } -#define INTR_RESTORE(si, intr_val) \ - if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ - (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } - -/* dynamic clock control defines */ -#define LPOMINFREQ 25000 /* low power oscillator min */ -#define LPOMAXFREQ 43000 /* low power oscillator max */ -#define XTALMINFREQ 19800000 /* 20 MHz - 1% */ -#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */ -#define PCIMINFREQ 25000000 /* 25 MHz */ -#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */ - -#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ -#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ - -/* force HT war check */ -#define FORCEHT_WAR32414(si) \ - (((PCIE(si)) && (si->sb.chip == BCM4311_CHIP_ID) && ((si->sb.chiprev <= 1))) || \ - ((PCI(si) || PCIE(si)) && (si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev <= 3))) - -#define PCIE_ASPMWARS(si) \ - ((PCIE(si)) && ((si->sb.buscorerev >= 3) && (si->sb.buscorerev <= 5))) - -/* GPIO Based LED powersave defines */ -#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */ -#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */ - -#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) - -static uint32 sb_read_sbreg(sb_info_t * si, volatile uint32 * sbr) -{ - uint8 tmp; - uint32 val, intr_val = 0; - - /* - * compact flash only has 11 bits address, while we needs 12 bits address. - * MEM_SEG will be OR'd with other 11 bits address in hardware, - * so we program MEM_SEG with 12th bit when necessary(access sb regsiters). - * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special - */ - if (PCMCIA(si)) { - INTR_OFF(si, intr_val); - tmp = 1; - OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1); - sbr = (volatile uint32 *)((uintptr) sbr & ~(1 << 11)); /* mask out bit 11 */ - } - - val = R_REG(si->osh, sbr); - - if (PCMCIA(si)) { - tmp = 0; - OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1); - INTR_RESTORE(si, intr_val); - } - - return (val); -} - -static void sb_write_sbreg(sb_info_t * si, volatile uint32 * sbr, uint32 v) -{ - uint8 tmp; - volatile uint32 dummy; - uint32 intr_val = 0; - - /* - * compact flash only has 11 bits address, while we needs 12 bits address. - * MEM_SEG will be OR'd with other 11 bits address in hardware, - * so we program MEM_SEG with 12th bit when necessary(access sb regsiters). - * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special - */ - if (PCMCIA(si)) { - INTR_OFF(si, intr_val); - tmp = 1; - OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1); - sbr = (volatile uint32 *)((uintptr) sbr & ~(1 << 11)); /* mask out bit 11 */ - } - - if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) { -#ifdef IL_BIGENDIAN - dummy = R_REG(si->osh, sbr); - W_REG(si->osh, ((volatile uint16 *)sbr + 1), - (uint16) ((v >> 16) & 0xffff)); - dummy = R_REG(si->osh, sbr); - W_REG(si->osh, (volatile uint16 *)sbr, (uint16) (v & 0xffff)); -#else - dummy = R_REG(si->osh, sbr); - W_REG(si->osh, (volatile uint16 *)sbr, (uint16) (v & 0xffff)); - dummy = R_REG(si->osh, sbr); - W_REG(si->osh, ((volatile uint16 *)sbr + 1), - (uint16) ((v >> 16) & 0xffff)); -#endif /* IL_BIGENDIAN */ - } else - W_REG(si->osh, sbr, v); - - if (PCMCIA(si)) { - tmp = 0; - OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1); - INTR_RESTORE(si, intr_val); - } -} - -/* - * Allocate a sb handle. - * devid - pci device id (used to determine chip#) - * osh - opaque OS handle - * regs - virtual address of initial core registers - * bustype - pci/pcmcia/sb/sdio/etc - * vars - pointer to a pointer area for "environment" variables - * varsz - pointer to int to return the size of the vars - */ -sb_t *sb_attach(uint devid, osl_t * osh, void *regs, - uint bustype, void *sdh, char **vars, - uint * varsz) { - sb_info_t *si; - - /* alloc sb_info_t */ - if ((si = MALLOC(osh, sizeof(sb_info_t))) == NULL) { - SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", - MALLOCED(osh))); - return (NULL); - } - - if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, varsz) == - NULL) { - MFREE(osh, si, sizeof(sb_info_t)); - return (NULL); - } - si->vars = vars ? *vars : NULL; - si->varsz = varsz ? *varsz : 0; - - return (sb_t *) si; -} - -/* Using sb_kattach depends on SB_BUS support, either implicit */ -/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */ -#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS) - -/* global kernel resource */ -static sb_info_t ksi; - -/* generic kernel variant of sb_attach() */ -sb_t *BCMINITFN(sb_kattach) (osl_t * osh) { - static bool ksi_attached = FALSE; - uint32 *regs; - - if (!ksi_attached) { - uint32 cid; - - regs = (uint32 *) REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE); - cid = R_REG(osh, (uint32 *) regs); - if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) && - ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) && - ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) { - uint32 *scc, val; - - scc = - (uint32 *) ((uchar *) regs + - OFFSETOF(chipcregs_t, slow_clk_ctl)); - val = R_REG(osh, scc); - SB_ERROR((" initial scc = 0x%x\n", val)); - val |= SCC_SS_XTAL; - W_REG(osh, scc, val); - } - - if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void *)regs, SB_BUS, NULL, - osh != SB_OSH ? &ksi.vars : NULL, - osh != SB_OSH ? &ksi.varsz : NULL) == NULL) - return NULL; - ksi_attached = TRUE; - } - - return &ksi.sb; -} -#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */ - -static sb_info_t *BCMINITFN(sb_doattach) (sb_info_t * si, uint devid, - osl_t * osh, void *regs, - uint bustype, void *sdh, - char **vars, uint * varsz) { - uint origidx; - chipcregs_t *cc; - sbconfig_t *sb; - uint32 w; - char *pvars; - - ASSERT(GOODREGS(regs)); - - bzero((uchar *) si, sizeof(sb_info_t)); - si->sb.buscoreidx = si->gpioidx = BADIDX; - - si->curmap = regs; - si->sdh = sdh; - si->osh = osh; - - /* check to see if we are a sb core mimic'ing a pci core */ - if (bustype == PCI_BUS) { - if (OSL_PCI_READ_CONFIG - (si->osh, PCI_SPROM_CONTROL, - sizeof(uint32)) == 0xffffffff) { - SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB " "devid:0x%x\n", __FUNCTION__, devid)); - bustype = SB_BUS; - } - } - si->sb.bustype = bustype; - if (si->sb.bustype != BUSTYPE(si->sb.bustype)) { - SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n", si->sb.bustype, BUSTYPE(si->sb.bustype))); - return NULL; - } - - /* need to set memseg flag for CF card first before any sb registers access */ - if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) - si->memseg = TRUE; - - /* kludge to enable the clock on the 4306 which lacks a slowclock */ - if (BUSTYPE(si->sb.bustype) == PCI_BUS && !sb_ispcie(si)) - sb_clkctl_xtal(&si->sb, XTAL | PLL, ON); - - if (BUSTYPE(si->sb.bustype) == PCI_BUS) { - w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32)); - if (!GOODCOREADDR(w)) - OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, - sizeof(uint32), SB_ENUM_BASE); - } - - /* initialize current core index value */ - si->curidx = _sb_coreidx(si); - - if (si->curidx == BADIDX) { - SB_ERROR(("sb_doattach: bad core index\n")); - return NULL; - } - - /* get sonics backplane revision */ - sb = REGS2SB(regs); - si->sb.sonicsrev = - (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT; - /* keep and reuse the initial register mapping */ - origidx = si->curidx; - if (BUSTYPE(si->sb.bustype) == SB_BUS) - si->regs[origidx] = regs; - - /* is core-0 a chipcommon core? */ - si->numcores = 1; - cc = (chipcregs_t *) sb_setcoreidx(&si->sb, 0); - if (sb_coreid(&si->sb) != SB_CC) - cc = NULL; - - /* determine chip id and rev */ - if (cc) { - /* chip common core found! */ - si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK; - si->sb.chiprev = - (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> - CID_REV_SHIFT; - si->sb.chippkg = - (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> - CID_PKG_SHIFT; - } else { - /* no chip common core -- must convert device id to chip id */ - if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) { - SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid)); - sb_setcoreidx(&si->sb, origidx); - return NULL; - } - } - - /* get chipcommon rev */ - si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV; - - /* get chipcommon capabilites */ - si->sb.cccaps = cc ? R_REG(si->osh, &cc->capabilities) : 0; - - /* determine numcores */ - if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6))) - si->numcores = - (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT; - else - si->numcores = sb_chip2numcores(si->sb.chip); - - /* return to original core */ - sb_setcoreidx(&si->sb, origidx); - - /* sanity checks */ - ASSERT(si->sb.chip); - - /* scan for cores */ - sb_scan(si); - - /* fixup necessary chip/core configurations */ - if (BUSTYPE(si->sb.bustype) == PCI_BUS && sb_pci_fixcfg(si)) { - SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n")); - return NULL; - } - - /* Init nvram from sprom/otp if they exist */ - if (srom_var_init - (&si->sb, BUSTYPE(si->sb.bustype), regs, si->osh, vars, varsz)) { - SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n")); - return (NULL); - } - pvars = vars ? *vars : NULL; - - /* PMU specific initializations */ - if ((si->sb.cccaps & CC_CAP_PMU) && !sb_onetimeinit) { - sb_pmu_init(&si->sb, si->osh); - /* Find out Crystal frequency and init PLL */ - sb_pmu_pll_init(&si->sb, si->osh, getintvar(pvars, "xtalfreq")); - /* Initialize PMU resources (up/dn timers, dep masks, etc.) */ - sb_pmu_res_init(&si->sb, si->osh); - } - if (cc == NULL) { - /* - * The chip revision number is hardwired into all - * of the pci function config rev fields and is - * independent from the individual core revision numbers. - * For example, the "A0" silicon of each chip is chip rev 0. - * For PCMCIA we get it from the CIS instead. - */ - if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) { - ASSERT(vars); - si->sb.chiprev = getintvar(*vars, "chiprev"); - } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) { - w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, - sizeof(uint32)); - si->sb.chiprev = w & 0xff; - } else - si->sb.chiprev = 0; - } - - if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) { - w = getintvar(pvars, "regwindowsz"); - si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE; - } - /* gpio control core is required */ - if (!GOODIDX(si->gpioidx)) { - SB_ERROR(("sb_doattach: gpio control core not found\n")); - return NULL; - } - - /* get boardtype and boardrev */ - switch (BUSTYPE(si->sb.bustype)) { - case PCI_BUS: - /* do a pci config read to get subsystem id and subvendor id */ - w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32)); - /* Let nvram variables override subsystem Vend/ID */ - if ((si->sb.boardvendor = - (uint16) sb_getdevpathintvar(&si->sb, "boardvendor")) == 0) - si->sb.boardvendor = w & 0xffff; - else - SB_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", si->sb.boardvendor, w & 0xffff)); - if ((si->sb.boardtype = - (uint16) sb_getdevpathintvar(&si->sb, "boardtype")) == 0) - si->sb.boardtype = (w >> 16) & 0xffff; - else - SB_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", si->sb.boardtype, (w >> 16) & 0xffff)); - break; - - case PCMCIA_BUS: - si->sb.boardvendor = getintvar(pvars, "manfid"); - si->sb.boardtype = getintvar(pvars, "prodid"); - break; - - case SB_BUS: - case JTAG_BUS: - si->sb.boardvendor = VENDOR_BROADCOM; - if (pvars == NULL - || ((si->sb.boardtype = getintvar(pvars, "prodid")) == 0)) - if ((si->sb.boardtype = - getintvar(NULL, "boardtype")) == 0) - si->sb.boardtype = 0xffff; - break; - } - - if (si->sb.boardtype == 0) { - SB_ERROR(("sb_doattach: unknown board type\n")); - ASSERT(si->sb.boardtype); - } - - si->sb.boardflags = getintvar(pvars, "boardflags"); - - /* setup the GPIO based LED powersave register */ - if (si->sb.ccrev >= 16) { - if ((pvars == NULL) || ((w = getintvar(pvars, "leddc")) == 0)) - w = DEFAULT_GPIOTIMERVAL; - sb_corereg(&si->sb, SB_CC_IDX, - OFFSETOF(chipcregs_t, gpiotimerval), ~0, w); - } - - /* Determine if this board needs override */ - if (PCIE(si) && (si->sb.chip == BCM4321_CHIP_ID)) - si->pcie_war_ovr = ((si->sb.boardvendor == VENDOR_APPLE) && - ((uint8) getintvar(pvars, "sromrev") == 4) - && ((uint8) getintvar(pvars, "boardrev") <= - 0x71)) - || ((uint32) getintvar(pvars, "boardflags2") & - BFL2_PCIEWAR_OVR); - - if (PCIE_ASPMWARS(si)) { - sb_war43448_aspm((void *)si); - sb_war42767_clkreq((void *)si); - } - - if (FORCEHT_WAR32414(si)) { - si->sb.pr32414 = TRUE; - sb_clkctl_init(&si->sb); - sb_war32414_forceHT(&si->sb, 1); - } - - if (PCIE(si) && ((si->sb.buscorerev == 6) || (si->sb.buscorerev == 7))) - si->sb.pr42780 = TRUE; - - if (PCIE_ASPMWARS(si)) - sb_pcieclkreq(&si->sb, 1, 0); - - if (PCIE(si) && - (((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev == 2)) || - ((si->sb.chip == BCM4312_CHIP_ID) && (si->sb.chiprev == 0)))) - sb_set_initiator_to(&si->sb, 0x3, - sb_findcoreidx(&si->sb, SB_D11, 0)); - - /* Disable gpiopullup and gpiopulldown */ - if (!sb_onetimeinit && si->sb.ccrev >= 20) { - cc = (chipcregs_t *) sb_setcore(&si->sb, SB_CC, 0); - W_REG(osh, &cc->gpiopullup, 0); - W_REG(osh, &cc->gpiopulldown, 0); - sb_setcoreidx(&si->sb, origidx); - } -#ifdef BCMDBG - /* clear any previous epidiag-induced target abort */ - sb_taclear(&si->sb); -#endif /* BCMDBG */ - -#ifdef HNDRTE - sb_onetimeinit = TRUE; -#endif - - return (si); -} - -/* Enable/Disable clkreq for PCIE (4311B0/4321B1) */ -void sb_war42780_clkreq(sb_t * sbh, bool clkreq) { - sb_info_t *si; - - si = SB_INFO(sbh); - - /* Don't change clkreq value if serdespll war has not yet been applied */ - if (!si->pr42767_war && PCIE_ASPMWARS(si)) - return; - - sb_pcieclkreq(sbh, 1, (int32) clkreq); -} - -static void BCMINITFN(sb_war43448) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - - /* if not pcie bus, we're done */ - if (!PCIE(si) || !PCIE_ASPMWARS(si)) - return; - - /* Restore the polarity */ - if (si->pcie_polarity != 0) - sb_pcie_mdiowrite((void *)(uintptr) & si->sb, MDIODATA_DEV_RX, - SERDES_RX_CTRL, si->pcie_polarity); -} - -static void BCMINITFN(sb_war43448_aspm) (sb_t * sbh) { - uint32 w; - uint16 val16, *reg16; - sbpcieregs_t *pcieregs; - sb_info_t *si; - - si = SB_INFO(sbh); - - /* if not pcie bus, we're done */ - if (!PCIE(si) || !PCIE_ASPMWARS(si)) - return; - - /* no ASPM stuff on QT or VSIM */ - if (si->sb.chippkg == HDLSIM_PKG_ID || si->sb.chippkg == HWSIM_PKG_ID) - return; - - pcieregs = (sbpcieregs_t *) sb_setcoreidx(sbh, si->sb.buscoreidx); - - /* Enable ASPM in the shadow SROM and Link control */ - reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET]; - val16 = R_REG(si->osh, reg16); - if (!si->pcie_war_ovr) - val16 |= SRSH_ASPM_ENB; - else - val16 &= ~SRSH_ASPM_ENB; - W_REG(si->osh, reg16, val16); - - w = OSL_PCI_READ_CONFIG(si->osh, si->pciecap_lcreg_offset, - sizeof(uint32)); - if (!si->pcie_war_ovr) - w |= PCIE_ASPM_ENAB; - else - w &= ~PCIE_ASPM_ENAB; - OSL_PCI_WRITE_CONFIG(si->osh, si->pciecap_lcreg_offset, sizeof(uint32), - w); -} - -static void BCMINITFN(sb_war32414_forceHT) (sb_t * sbh, bool forceHT) { - sb_info_t *si; - uint32 val = 0; - - si = SB_INFO(sbh); - - ASSERT(FORCEHT_WAR32414(si)); - - if (forceHT) - val = SYCC_HR; - sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl), - SYCC_HR, val); -} - -uint sb_coreid(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT); -} - -uint sb_flag(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - return R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK; -} - -uint sb_coreidx(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->curidx); -} - -static uint _sb_coreidx(sb_info_t * si) -{ - - sbconfig_t *sb; - uint32 sbaddr = 0; - - ASSERT(si); - - switch (BUSTYPE(si->sb.bustype)) { - case SB_BUS: - sb = REGS2SB(si->curmap); - sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0)); - break; - - case PCI_BUS: - sbaddr = - OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32)); - break; - - case PCMCIA_BUS:{ - uint8 tmp = 0; - - OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1); - sbaddr = (uint) tmp << 12; - OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1); - sbaddr |= (uint) tmp << 16; - OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1); - sbaddr |= (uint) tmp << 24; - break; - } - -#ifdef BCMJTAG - case JTAG_BUS: - sbaddr = (uint32) si->curmap; - break; -#endif /* BCMJTAG */ - - default: - ASSERT(0); - } - - if (!GOODCOREADDR(sbaddr)) - return BADIDX; - - return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE); -} - -uint sb_corevendor(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT); -} - -uint sb_corerev(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - uint sbidh; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - sbidh = R_SBREG(si, &sb->sbidhigh); - - return (SBCOREREV(sbidh)); -} - -void *sb_osh(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - return si->osh; -} - -void sb_setosh(sb_t * sbh, osl_t * osh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - if (si->osh != NULL) { - SB_ERROR(("osh is already set....\n")); - ASSERT(!si->osh); - } - si->osh = osh; -} - -/* set sbtmstatelow core-specific flags */ -void sb_coreflags_wo(sb_t * sbh, uint32 mask, uint32 val) -{ - sb_info_t *si; - sbconfig_t *sb; - uint32 w; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - ASSERT((val & ~mask) == 0); - - /* mask and set */ - w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val; - W_SBREG(si, &sb->sbtmstatelow, w); -} - -/* set/clear sbtmstatelow core-specific flags */ -uint32 sb_coreflags(sb_t * sbh, uint32 mask, uint32 val) -{ - sb_info_t *si; - sbconfig_t *sb; - uint32 w; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - ASSERT((val & ~mask) == 0); - - /* mask and set */ - if (mask || val) { - w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val; - W_SBREG(si, &sb->sbtmstatelow, w); - } - - /* return the new value - * for write operation, the following readback ensures the completion of write opration. - */ - return (R_SBREG(si, &sb->sbtmstatelow)); -} - -/* set/clear sbtmstatehigh core-specific flags */ -uint32 sb_coreflagshi(sb_t * sbh, uint32 mask, uint32 val) -{ - sb_info_t *si; - sbconfig_t *sb; - uint32 w; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - ASSERT((val & ~mask) == 0); - ASSERT((mask & ~SBTMH_FL_MASK) == 0); - - /* mask and set */ - if (mask || val) { - w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val; - W_SBREG(si, &sb->sbtmstatehigh, w); - } - - /* return the new value */ - return (R_SBREG(si, &sb->sbtmstatehigh)); -} - -/* Run bist on current core. Caller needs to take care of core-specific bist hazards */ -int sb_corebist(sb_t * sbh) -{ - uint32 sblo; - sb_info_t *si; - sbconfig_t *sb; - int result = 0; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - sblo = R_SBREG(si, &sb->sbtmstatelow); - W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE)); - - SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), - 100000); - - if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF) - result = -1; - - W_SBREG(si, &sb->sbtmstatelow, sblo); - - return result; -} - -bool sb_iscoreup(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - return ((R_SBREG(si, &sb->sbtmstatelow) & - (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK); -} - -/* - * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation, - * switch back to the original core, and return the new value. - * - * When using the silicon backplane, no fidleing with interrupts or core switches are needed. - * - * Also, when using pci/pcie, we can optimize away the core switching for pci registers - * and (on newer pci cores) chipcommon registers. - */ -uint sb_corereg(sb_t * sbh, uint coreidx, uint regoff, uint mask, uint val) -{ - uint origidx = 0; - uint32 *r = NULL; - uint w; - uint intr_val = 0; - bool fast = FALSE; - sb_info_t *si; - - si = SB_INFO(sbh); - - ASSERT(GOODIDX(coreidx)); - ASSERT(regoff < SB_CORE_SIZE); - ASSERT((val & ~mask) == 0); - -#if 0 - if (BUSTYPE(si->sb.bustype) == SB_BUS) { - /* If internal bus, we can always get at everything */ - fast = TRUE; - /* map if does not exist */ - if (!si->regs[coreidx]) { - si->regs[coreidx] = - (void *)REG_MAP(si->coresba[coreidx], SB_CORE_SIZE); - ASSERT(GOODREGS(si->regs[coreidx])); - } - r = (uint32 *) ((uchar *) si->regs[coreidx] + regoff); - } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) { - /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */ - - if ((si->coreid[coreidx] == SB_CC) && - ((si->sb.buscoretype == SB_PCIE) - || (si->sb.buscorerev >= 13))) { - /* Chipc registers are mapped at 12KB */ - - fast = TRUE; - r = (uint32 *) ((char *)si->curmap + - PCI_16KB0_CCREGS_OFFSET + regoff); - } else if (si->sb.buscoreidx == coreidx) { - /* pci registers are at either in the last 2KB of an 8KB window - * or, in pcie and pci rev 13 at 8KB - */ - fast = TRUE; - if ((si->sb.buscoretype == SB_PCIE) - || (si->sb.buscorerev >= 13)) - r = (uint32 *) ((char *)si->curmap + - PCI_16KB0_PCIREGS_OFFSET + - regoff); - else - r = (uint32 *) ((char *)si->curmap + - ((regoff >= SBCONFIGOFF) ? - PCI_BAR0_PCISBR_OFFSET : - PCI_BAR0_PCIREGS_OFFSET) - + regoff); - } - } -#endif - - if (!fast) { - INTR_OFF(si, intr_val); - - /* save current core index */ - origidx = sb_coreidx(&si->sb); - - /* switch core */ - r = (uint32 *) ((uchar *) sb_setcoreidx(&si->sb, coreidx) + - regoff); - } - ASSERT(r); - - /* mask and set */ - if (mask || val) { - if (regoff >= SBCONFIGOFF) { - w = (R_SBREG(si, r) & ~mask) | val; - W_SBREG(si, r, w); - } else { - w = (R_REG(si->osh, r) & ~mask) | val; - W_REG(si->osh, r, w); - } - } - - /* readback */ - if (regoff >= SBCONFIGOFF) - w = R_SBREG(si, r); - else { - if ((si->sb.chip == BCM5354_CHIP_ID) && - (coreidx == SB_CC_IDX) && - (regoff == OFFSETOF(chipcregs_t, watchdog))) { - w = val; - } else - w = R_REG(si->osh, r); - } - - if (!fast) { - /* restore core index */ - if (origidx != coreidx) - sb_setcoreidx(&si->sb, origidx); - - INTR_RESTORE(si, intr_val); - } - - return (w); -} - -#define DWORD_ALIGN(x) (x & ~(0x03)) -#define BYTE_POS(x) (x & 0x3) -#define WORD_POS(x) (x & 0x1) - -#define BYTE_SHIFT(x) (8 * BYTE_POS(x)) -#define WORD_SHIFT(x) (16 * WORD_POS(x)) - -#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF) -#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF) - -#define read_pci_cfg_byte(a) \ - (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff) - -#define read_pci_cfg_word(a) \ - (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff) - -/* return cap_offset if requested capability exists in the PCI config space */ -static uint8 -sb_find_pci_capability(sb_info_t * si, uint8 req_cap_id, uchar * buf, - uint32 * buflen) -{ - uint8 cap_id; - uint8 cap_ptr = 0; - uint32 bufsize; - uint8 byte_val; - - if (BUSTYPE(si->sb.bustype) != PCI_BUS) - goto end; - - /* check for Header type 0 */ - byte_val = read_pci_cfg_byte(PCI_CFG_HDR); - if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) - goto end; - - /* check if the capability pointer field exists */ - byte_val = read_pci_cfg_byte(PCI_CFG_STAT); - if (!(byte_val & PCI_CAPPTR_PRESENT)) - goto end; - - cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR); - /* check if the capability pointer is 0x00 */ - if (cap_ptr == 0x00) - goto end; - - /* loop thr'u the capability list and see if the pcie capabilty exists */ - - cap_id = read_pci_cfg_byte(cap_ptr); - - while (cap_id != req_cap_id) { - cap_ptr = read_pci_cfg_byte((cap_ptr + 1)); - if (cap_ptr == 0x00) - break; - cap_id = read_pci_cfg_byte(cap_ptr); - } - if (cap_id != req_cap_id) { - goto end; - } - /* found the caller requested capability */ - if ((buf != NULL) && (buflen != NULL)) { - uint8 cap_data; - - bufsize = *buflen; - if (!bufsize) - goto end; - *buflen = 0; - /* copy the cpability data excluding cap ID and next ptr */ - cap_data = cap_ptr + 2; - if ((bufsize + cap_data) > SZPCR) - bufsize = SZPCR - cap_data; - *buflen = bufsize; - while (bufsize--) { - *buf = read_pci_cfg_byte(cap_data); - cap_data++; - buf++; - } - } - end: - return cap_ptr; -} - -uint8 sb_pcieclkreq(sb_t * sbh, uint32 mask, uint32 val) -{ - sb_info_t *si; - uint32 reg_val; - uint8 offset; - - si = SB_INFO(sbh); - - offset = si->pciecap_lcreg_offset; - if (!offset) - return 0; - - reg_val = OSL_PCI_READ_CONFIG(si->osh, offset, sizeof(uint32)); - /* set operation */ - if (mask) { - if (val) - reg_val |= PCIE_CLKREQ_ENAB; - else - reg_val &= ~PCIE_CLKREQ_ENAB; - OSL_PCI_WRITE_CONFIG(si->osh, offset, sizeof(uint32), reg_val); - reg_val = OSL_PCI_READ_CONFIG(si->osh, offset, sizeof(uint32)); - } - if (reg_val & PCIE_CLKREQ_ENAB) - return 1; - else - return 0; -} - -#ifdef BCMDBG - -uint32 sb_pcielcreg(sb_t * sbh, uint32 mask, uint32 val) -{ - sb_info_t *si; - uint32 reg_val; - uint8 offset; - - si = SB_INFO(sbh); - - if (!PCIE(si)) - return 0; - - offset = si->pciecap_lcreg_offset; - if (!offset) - return 0; - - /* set operation */ - if (mask) - OSL_PCI_WRITE_CONFIG(si->osh, offset, sizeof(uint32), val); - - reg_val = OSL_PCI_READ_CONFIG(si->osh, offset, sizeof(uint32)); - - return reg_val; -} - -uint8 sb_pcieL1plldown(sb_t * sbh) -{ - sb_info_t *si; - uint intr_val = 0; - uint origidx; - uint32 reg_val; - - si = SB_INFO(sbh); - - if (!PCIE(si)) - return 0; - if (!((si->sb.buscorerev == 3) || (si->sb.buscorerev == 4))) - return 0; - - if (!sb_pcieclkreq((void *)(uintptr) sbh, 0, 0)) { - SB_ERROR(("PCIEL1PLLDOWN requires Clkreq be enabled, so enable it\n")); - sb_pcieclkreq((void *)(uintptr) sbh, 1, 1); - } - reg_val = sb_pcielcreg((void *)(uintptr) sbh, 0, 0); - if (reg_val & PCIE_CAP_LCREG_ASPML0s) { - SB_ERROR(("PCIEL1PLLDOWN requires L0s to be disabled\n")); - reg_val &= ~PCIE_CAP_LCREG_ASPML0s; - sb_pcielcreg((void *)(uintptr) sbh, 1, reg_val); - } else - SB_ERROR(("PCIEL1PLLDOWN: L0s is already disabled\n")); - - /* turnoff intrs, change core, set original back, turn on intrs back on */ - origidx = si->curidx; - INTR_OFF(si, intr_val); - sb_setcore(sbh, SB_PCIE, 0); - - sb_pcie_writereg((void *)(uintptr) sbh, (void *)PCIE_PCIEREGS, - PCIE_DLLP_PCIE11, 0); - - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); - return 1; -} -#endif /* BCMDBG */ - -/* return TRUE if PCIE capability exists in the pci config space */ -static bool sb_ispcie(sb_info_t * si) -{ - uint8 cap_ptr; - - cap_ptr = sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL); - if (!cap_ptr) - return FALSE; - - si->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET; - - return TRUE; -} - -/* Wake-on-wireless-LAN (WOWL) support functions */ -/* return TRUE if PM capability exists in the pci config space */ -bool sb_pci_pmecap(sb_t * sbh) -{ - uint8 cap_ptr; - uint32 pmecap; - sb_info_t *si; - - si = SB_INFO(sbh); - - if (si == NULL || !(PCI(si) || PCIE(si))) - return FALSE; - - if (!si->pmecap_offset) { - cap_ptr = - sb_find_pci_capability(si, PCI_CAP_POWERMGMTCAP_ID, NULL, - NULL); - if (!cap_ptr) - return FALSE; - - si->pmecap_offset = cap_ptr; - - pmecap = - OSL_PCI_READ_CONFIG(si->osh, si->pmecap_offset, - sizeof(uint32)); - - /* At least one state can generate PME */ - si->pmecap = (pmecap & PME_CAP_PM_STATES) != 0; - } - - return (si->pmecap); -} - -/* Enable PME generation and disable clkreq */ -void sb_pci_pmeen(sb_t * sbh) -{ - sb_info_t *si; - uint32 w; - si = SB_INFO(sbh); - - /* if not pmecapable return */ - if (!sb_pci_pmecap(sbh)) - return; - - w = OSL_PCI_READ_CONFIG(si->osh, si->pmecap_offset + PME_CSR_OFFSET, - sizeof(uint32)); - w |= (PME_CSR_PME_EN); - OSL_PCI_WRITE_CONFIG(si->osh, si->pmecap_offset + PME_CSR_OFFSET, - sizeof(uint32), w); - - /* Disable clkreq */ - if (si->pr42767_war) { - sb_pcieclkreq(sbh, 1, 0); - si->pr42767_war = FALSE; - } else if (si->sb.pr42780) { - sb_pcieclkreq(sbh, 1, 1); - } -} - -/* Disable PME generation, clear the PME status bit if set and - * return TRUE if PME status set - */ -bool sb_pci_pmeclr(sb_t * sbh) -{ - sb_info_t *si; - uint32 w; - bool ret = FALSE; - - si = SB_INFO(sbh); - - if (!sb_pci_pmecap(sbh)) - return ret; - - w = OSL_PCI_READ_CONFIG(si->osh, si->pmecap_offset + PME_CSR_OFFSET, - sizeof(uint32)); - - SB_ERROR(("sb_pci_pmeclr PMECSR : 0x%x\n", w)); - ret = (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT; - - /* PMESTAT is cleared by writing 1 to it */ - w &= ~(PME_CSR_PME_EN); - - OSL_PCI_WRITE_CONFIG(si->osh, si->pmecap_offset + PME_CSR_OFFSET, - sizeof(uint32), w); - - return ret; -} - -/* use pci dev id to determine chip id for chips not having a chipcommon core */ -static uint BCMINITFN(sb_pcidev2chip) (uint pcidev) { - if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID)) - return (BCM4710_CHIP_ID); - if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID)) - return (BCM4402_CHIP_ID); - if (pcidev == BCM4401_ENET_ID) - return (BCM4402_CHIP_ID); - if (pcidev == SDIOH_FPGA_ID) - return (SDIOH_FPGA_ID); - - return (0); -} - -/* Scan the enumeration space to find all cores starting from the given - * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba' - * is the default core address at chip POR time and 'regs' is the virtual - * address that the default core is mapped at. 'ncores' is the number of - * cores expected on bus 'sbba'. It returns the total number of cores - * starting from bus 'sbba', inclusive. - */ - -static void BCMINITFN(sb_scan) (sb_info_t * si) { - sb_t *sbh; - uint origidx; - uint i; - bool pci; - bool pcie; - uint pciidx; - uint pcieidx; - uint pcirev; - uint pcierev; - - sbh = (sb_t *) si; - - /* numcores should already be set */ - ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES)); - - /* save current core index */ - origidx = sb_coreidx(&si->sb); - - si->sb.buscorerev = NOREV; - si->sb.buscoreidx = BADIDX; - - si->gpioidx = BADIDX; - - pci = pcie = FALSE; - pcirev = pcierev = NOREV; - pciidx = pcieidx = BADIDX; - - for (i = 0; i < si->numcores; i++) { - sb_setcoreidx(&si->sb, i); - si->coreid[i] = sb_coreid(&si->sb); - - if (si->coreid[i] == SB_PCI) { - pciidx = i; - pcirev = sb_corerev(&si->sb); - pci = TRUE; - } else if (si->coreid[i] == SB_PCIE) { - pcieidx = i; - pcierev = sb_corerev(&si->sb); - pcie = TRUE; - } else if (si->coreid[i] == SB_PCMCIA) { - si->sb.buscorerev = sb_corerev(&si->sb); - si->sb.buscoretype = si->coreid[i]; - si->sb.buscoreidx = i; - } - } - if (pci && pcie) { - if (sb_ispcie(si)) - pci = FALSE; - else - pcie = FALSE; - } - if (pci) { - si->sb.buscoretype = SB_PCI; - si->sb.buscorerev = pcirev; - si->sb.buscoreidx = pciidx; - } else if (pcie) { - si->sb.buscoretype = SB_PCIE; - si->sb.buscorerev = pcierev; - si->sb.buscoreidx = pcieidx; - } - - /* - * Find the gpio "controlling core" type and index. - * Precedence: - * - if there's a chip common core - use that - * - else if there's a pci core (rev >= 2) - use that - * - else there had better be an extif core (4710 only) - */ - if (GOODIDX(sb_findcoreidx(sbh, SB_CC, 0))) { - si->gpioidx = sb_findcoreidx(sbh, SB_CC, 0); - si->gpioid = SB_CC; - } else if (PCI(si) && (si->sb.buscorerev >= 2)) { - si->gpioidx = si->sb.buscoreidx; - si->gpioid = SB_PCI; - } else if (sb_findcoreidx(sbh, SB_EXTIF, 0)) { - si->gpioidx = sb_findcoreidx(sbh, SB_EXTIF, 0); - si->gpioid = SB_EXTIF; - } else - ASSERT(si->gpioidx != BADIDX); - - /* return to original core index */ - sb_setcoreidx(&si->sb, origidx); -} - -/* may be called with core in reset */ -void sb_detach(sb_t * sbh) -{ - sb_info_t *si; - uint idx; - - si = SB_INFO(sbh); - - if (si == NULL) - return; - - if (BUSTYPE(si->sb.bustype) == SB_BUS) - for (idx = 0; idx < SB_MAXCORES; idx++) - if (si->regs[idx]) { - REG_UNMAP(si->regs[idx]); - si->regs[idx] = NULL; - } -#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS) - if (si != &ksi) -#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */ - MFREE(si->osh, si, sizeof(sb_info_t)); -} - - -/* convert chip number to number of i/o cores */ -static uint BCMINITFN(sb_chip2numcores) (uint chip) { - if (chip == BCM4710_CHIP_ID) - return (9); - if (chip == BCM4402_CHIP_ID) - return (3); - if (chip == BCM4306_CHIP_ID) /* < 4306c0 */ - return (6); - if (chip == BCM4704_CHIP_ID) - return (9); - if (chip == BCM5365_CHIP_ID) - return (7); - if (chip == SDIOH_FPGA_ID) - return (2); - - SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip)); - ASSERT(0); - return (1); -} - -/* return index of coreid or BADIDX if not found */ -uint sb_findcoreidx(sb_t * sbh, uint coreid, uint coreunit) -{ - sb_info_t *si; - uint found; - uint i; - - si = SB_INFO(sbh); - - found = 0; - - for (i = 0; i < si->numcores; i++) - if (si->coreid[i] == coreid) { - if (found == coreunit) - return (i); - found++; - } - - return (BADIDX); -} - -/* - * this function changes logical "focus" to the indiciated core, - * must be called with interrupt off. - * Moreover, callers should keep interrupts off during switching out of and back to d11 core - */ -void *sb_setcoreidx(sb_t * sbh, uint coreidx) -{ - sb_info_t *si; - uint32 sbaddr; - uint8 tmp; - - si = SB_INFO(sbh); - - if (coreidx >= si->numcores) - return (NULL); - - /* - * If the user has provided an interrupt mask enabled function, - * then assert interrupts are disabled before switching the core. - */ - ASSERT((si->intrsenabled_fn == NULL) - || !(*(si)->intrsenabled_fn) ((si)->intr_arg)); - - sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE); - - switch (BUSTYPE(si->sb.bustype)) { - case SB_BUS: - /* map new one */ - if (!si->regs[coreidx]) { - si->regs[coreidx] = - (void *)REG_MAP(sbaddr, SB_CORE_SIZE); - ASSERT(GOODREGS(si->regs[coreidx])); - } - si->curmap = si->regs[coreidx]; - break; - - case PCI_BUS: - /* point bar0 window */ - OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr); - break; - - case PCMCIA_BUS: - tmp = (sbaddr >> 12) & 0x0f; - OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1); - tmp = (sbaddr >> 16) & 0xff; - OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1); - tmp = (sbaddr >> 24) & 0xff; - OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1); - break; -#ifdef BCMJTAG - case JTAG_BUS: - /* map new one */ - if (!si->regs[coreidx]) { - si->regs[coreidx] = (void *)sbaddr; - ASSERT(GOODREGS(si->regs[coreidx])); - } - si->curmap = si->regs[coreidx]; - break; -#endif /* BCMJTAG */ - } - - si->curidx = coreidx; - - return (si->curmap); -} - -/* - * this function changes logical "focus" to the indiciated core, - * must be called with interrupt off. - * Moreover, callers should keep interrupts off during switching out of and back to d11 core - */ -void *sb_setcore(sb_t * sbh, uint coreid, uint coreunit) -{ - uint idx; - - idx = sb_findcoreidx(sbh, coreid, coreunit); - if (!GOODIDX(idx)) - return (NULL); - - return (sb_setcoreidx(sbh, idx)); -} - -/* return chip number */ -uint BCMINITFN(sb_chip) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.chip); -} - -/* return chip revision number */ -uint BCMINITFN(sb_chiprev) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.chiprev); -} - -/* return chip common revision number */ -uint BCMINITFN(sb_chipcrev) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.ccrev); -} - -/* return chip package option */ -uint BCMINITFN(sb_chippkg) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.chippkg); -} - -/* return PCI core rev. */ -uint BCMINITFN(sb_pcirev) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.buscorerev); -} - -bool BCMINITFN(sb_war16165) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - - return (PCI(si) && (si->sb.buscorerev <= 10)); -} - -static void BCMINITFN(sb_war30841) (sb_info_t * si) { - sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128); - sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100); - sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466); -} - -/* return PCMCIA core rev. */ -uint BCMINITFN(sb_pcmciarev) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.buscorerev); -} - -/* return board vendor id */ -uint BCMINITFN(sb_boardvendor) (sb_t * sbh) { - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.boardvendor); -} - -/* return boardtype */ -uint BCMINITFN(sb_boardtype) (sb_t * sbh) { - sb_info_t *si; - char *var; - - si = SB_INFO(sbh); - - if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) { - /* boardtype format is a hex string */ - si->sb.boardtype = getintvar(NULL, "boardtype"); - - /* backward compatibility for older boardtype string format */ - if ((si->sb.boardtype == 0) - && (var = getvar(NULL, "boardtype"))) { - if (!strcmp(var, "bcm94710dev")) - si->sb.boardtype = BCM94710D_BOARD; - else if (!strcmp(var, "bcm94710ap")) - si->sb.boardtype = BCM94710AP_BOARD; - else if (!strcmp(var, "bu4710")) - si->sb.boardtype = BU4710_BOARD; - else if (!strcmp(var, "bcm94702mn")) - si->sb.boardtype = BCM94702MN_BOARD; - else if (!strcmp(var, "bcm94710r1")) - si->sb.boardtype = BCM94710R1_BOARD; - else if (!strcmp(var, "bcm94710r4")) - si->sb.boardtype = BCM94710R4_BOARD; - else if (!strcmp(var, "bcm94702cpci")) - si->sb.boardtype = BCM94702CPCI_BOARD; - else if (!strcmp(var, "bcm95380_rr")) - si->sb.boardtype = BCM95380RR_BOARD; - } - } - - return (si->sb.boardtype); -} - -/* return bus type of sbh device */ -uint sb_bus(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - return (si->sb.bustype); -} - -/* return bus core type */ -uint sb_buscoretype(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - - return (si->sb.buscoretype); -} - -/* return bus core revision */ -uint sb_buscorerev(sb_t * sbh) -{ - sb_info_t *si; - si = SB_INFO(sbh); - - return (si->sb.buscorerev); -} - -/* return list of found cores */ -uint sb_corelist(sb_t * sbh, uint coreid[]) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - - bcopy((uchar *) si->coreid, (uchar *) coreid, - (si->numcores * sizeof(uint))); - return (si->numcores); -} - -/* return current register mapping */ -void *sb_coreregs(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - ASSERT(GOODREGS(si->curmap)); - - return (si->curmap); -} - -#if defined(BCMDBG_ASSERT) -/* traverse all cores to find and clear source of serror */ -static void sb_serr_clear(sb_info_t * si) -{ - sbconfig_t *sb; - uint origidx; - uint i, intr_val = 0; - void *corereg = NULL; - - INTR_OFF(si, intr_val); - origidx = sb_coreidx(&si->sb); - - for (i = 0; i < si->numcores; i++) { - corereg = sb_setcoreidx(&si->sb, i); - if (NULL != corereg) { - sb = REGS2SB(corereg); - if ((R_SBREG(si, &sb->sbtmstatehigh)) & SBTMH_SERR) { - AND_SBREG(si, &sb->sbtmstatehigh, ~SBTMH_SERR); - SB_ERROR(("sb_serr_clear: SError at core 0x%x\n", sb_coreid(&si->sb))); - } - } - } - - sb_setcoreidx(&si->sb, origidx); - INTR_RESTORE(si, intr_val); -} - -/* - * Check if any inband, outband or timeout errors has happened and clear them. - * Must be called with chip clk on ! - */ -bool sb_taclear(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - uint origidx; - uint intr_val = 0; - bool rc = FALSE; - uint32 inband = 0, serror = 0, timeout = 0; - void *corereg = NULL; - volatile uint32 imstate, tmstate; - - si = SB_INFO(sbh); - - if (BUSTYPE(si->sb.bustype) == PCI_BUS) { - volatile uint32 stcmd; - - /* inband error is Target abort for PCI */ - stcmd = - OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CMD, sizeof(uint32)); - inband = stcmd & PCI_CFG_CMD_STAT_TA; - if (inband) { -#ifdef BCMDBG - SB_ERROR(("inband:\n")); - sb_viewall((void *)si); -#endif - OSL_PCI_WRITE_CONFIG(si->osh, PCI_CFG_CMD, - sizeof(uint32), stcmd); - } - - /* serror */ - stcmd = - OSL_PCI_READ_CONFIG(si->osh, PCI_INT_STATUS, - sizeof(uint32)); - serror = stcmd & PCI_SBIM_STATUS_SERR; - if (serror) { -#ifdef BCMDBG - SB_ERROR(("serror:\n")); - sb_viewall((void *)si); -#endif - sb_serr_clear(si); - OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_STATUS, - sizeof(uint32), stcmd); - } - - /* timeout */ - imstate = sb_corereg(sbh, si->sb.buscoreidx, - SBCONFIGOFF + OFFSETOF(sbconfig_t, - sbimstate), 0, 0); - if ((imstate != 0xffffffff) && (imstate & (SBIM_IBE | SBIM_TO))) { - sb_corereg(sbh, si->sb.buscoreidx, - SBCONFIGOFF + OFFSETOF(sbconfig_t, - sbimstate), ~0, - (imstate & ~(SBIM_IBE | SBIM_TO))); - /* inband = imstate & SBIM_IBE; same as TA above */ - timeout = imstate & SBIM_TO; - if (timeout) { -#ifdef BCMDBG - SB_ERROR(("timeout:\n")); - sb_viewall((void *)si); -#endif - } - } - - if (inband) { - /* dump errlog for sonics >= 2.3 */ - if (si->sb.sonicsrev == SONICS_2_2) ; - else { - uint32 imerrlog, imerrloga; - imerrlog = - sb_corereg(sbh, si->sb.buscoreidx, - SBIMERRLOG, 0, 0); - if (imerrlog & SBTMEL_EC) { - imerrloga = - sb_corereg(sbh, si->sb.buscoreidx, - SBIMERRLOGA, 0, 0); - /* clear errlog */ - sb_corereg(sbh, si->sb.buscoreidx, - SBIMERRLOG, ~0, 0); - SB_ERROR(("sb_taclear: ImErrLog 0x%x, ImErrLogA 0x%x\n", imerrlog, imerrloga)); - } - } - } - - } else if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) { - - INTR_OFF(si, intr_val); - origidx = sb_coreidx(sbh); - - corereg = sb_setcore(sbh, SB_PCMCIA, 0); - if (NULL != corereg) { - sb = REGS2SB(corereg); - - imstate = R_SBREG(si, &sb->sbimstate); - /* handle surprise removal */ - if ((imstate != 0xffffffff) - && (imstate & (SBIM_IBE | SBIM_TO))) { - AND_SBREG(si, &sb->sbimstate, - ~(SBIM_IBE | SBIM_TO)); - inband = imstate & SBIM_IBE; - timeout = imstate & SBIM_TO; - } - tmstate = R_SBREG(si, &sb->sbtmstatehigh); - if ((tmstate != 0xffffffff) - && (tmstate & SBTMH_INT_STATUS)) { - if (!inband) { - serror = 1; - sb_serr_clear(si); - } - OR_SBREG(si, &sb->sbtmstatelow, SBTML_INT_ACK); - AND_SBREG(si, &sb->sbtmstatelow, - ~SBTML_INT_ACK); - } - } - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); - - } - - if (inband | timeout | serror) { - rc = TRUE; - SB_ERROR(("sb_taclear: inband 0x%x, serror 0x%x, timeout 0x%x!\n", inband, serror, timeout)); - } - - return (rc); -} -#endif /* BCMDBG */ - -/* do buffered registers update */ -void sb_commit(sb_t * sbh) -{ - sb_info_t *si; - uint origidx; - uint intr_val = 0; - - si = SB_INFO(sbh); - - origidx = si->curidx; - ASSERT(GOODIDX(origidx)); - - INTR_OFF(si, intr_val); - - /* switch over to chipcommon core if there is one, else use pci */ - if (si->sb.ccrev != NOREV) { - chipcregs_t *ccregs = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0); - - /* do the buffer registers update */ - W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT); - W_REG(si->osh, &ccregs->broadcastdata, 0x0); - } else if (PCI(si)) { - sbpciregs_t *pciregs = - (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0); - - /* do the buffer registers update */ - W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT); - W_REG(si->osh, &pciregs->bcastdata, 0x0); - } else - ASSERT(0); - - /* restore core index */ - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); -} - -/* reset and re-enable a core - * inputs: - * bits - core specific bits that are set during and after reset sequence - * resetbits - core specific bits that are set only during reset sequence - */ -void sb_core_reset(sb_t * sbh, uint32 bits, uint32 resetbits) -{ - sb_info_t *si; - sbconfig_t *sb; - volatile uint32 dummy; - - si = SB_INFO(sbh); - ASSERT(GOODREGS(si->curmap)); - sb = REGS2SB(si->curmap); - - /* - * Must do the disable sequence first to work for arbitrary current core state. - */ - sb_core_disable(sbh, (bits | resetbits)); - - /* - * Now do the initialization sequence. - */ - - /* set reset while enabling the clock and forcing them on throughout the core */ - W_SBREG(si, &sb->sbtmstatelow, - (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits)); - dummy = R_SBREG(si, &sb->sbtmstatelow); - OSL_DELAY(1); - - if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) { - W_SBREG(si, &sb->sbtmstatehigh, 0); - } - if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) { - AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO)); - } - - /* clear reset and allow it to propagate throughout the core */ - W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits)); - dummy = R_SBREG(si, &sb->sbtmstatelow); - OSL_DELAY(1); - - /* leave clock enabled */ - W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits)); - dummy = R_SBREG(si, &sb->sbtmstatelow); - OSL_DELAY(1); -} - -void sb_core_tofixup(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - - si = SB_INFO(sbh); - - if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || - (PCI(si) && (si->sb.buscorerev >= 5))) - return; - - ASSERT(GOODREGS(si->curmap)); - sb = REGS2SB(si->curmap); - - if (BUSTYPE(si->sb.bustype) == SB_BUS) { - SET_SBREG(si, &sb->sbimconfiglow, - SBIMCL_RTO_MASK | SBIMCL_STO_MASK, - (0x5 << SBIMCL_RTO_SHIFT) | 0x3); - } else { - if (sb_coreid(sbh) == SB_PCI) { - SET_SBREG(si, &sb->sbimconfiglow, - SBIMCL_RTO_MASK | SBIMCL_STO_MASK, - (0x3 << SBIMCL_RTO_SHIFT) | 0x2); - } else { - SET_SBREG(si, &sb->sbimconfiglow, - (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0); - } - } - - sb_commit(sbh); -} - -/* - * Set the initiator timeout for the "master core". - * The master core is defined to be the core in control - * of the chip and so it issues accesses to non-memory - * locations (Because of dma *any* core can access memeory). - * - * The routine uses the bus to decide who is the master: - * SB_BUS => mips - * JTAG_BUS => chipc - * PCI_BUS => pci or pcie - * PCMCIA_BUS => pcmcia - * SDIO_BUS => pcmcia - * - * This routine exists so callers can disable initiator - * timeouts so accesses to very slow devices like otp - * won't cause an abort. The routine allows arbitrary - * settings of the service and request timeouts, though. - * - * Returns the timeout state before changing it or -1 - * on error. - */ - -#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK) - -uint32 sb_set_initiator_to(sb_t * sbh, uint32 to, uint idx) -{ - sb_info_t *si; - uint origidx; - uint intr_val = 0; - uint32 tmp, ret = 0xffffffff; - sbconfig_t *sb; - - si = SB_INFO(sbh); - - if ((to & ~TO_MASK) != 0) - return ret; - - /* Figure out the master core */ - if (idx == BADIDX) { - switch (BUSTYPE(si->sb.bustype)) { - case PCI_BUS: - idx = si->sb.buscoreidx; - break; - case JTAG_BUS: - idx = SB_CC_IDX; - break; - case PCMCIA_BUS: - case SDIO_BUS: - idx = sb_findcoreidx(sbh, SB_PCMCIA, 0); - break; - case SB_BUS: - if ((idx = sb_findcoreidx(sbh, SB_MIPS33, 0)) == BADIDX) - idx = sb_findcoreidx(sbh, SB_MIPS, 0); - break; - default: - ASSERT(0); - } - if (idx == BADIDX) - return ret; - } - - INTR_OFF(si, intr_val); - origidx = sb_coreidx(sbh); - - sb = REGS2SB(sb_setcoreidx(sbh, idx)); - - tmp = R_SBREG(si, &sb->sbimconfiglow); - ret = tmp & TO_MASK; - W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to); - - sb_commit(sbh); - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); - return ret; -} - -void sb_core_disable(sb_t * sbh, uint32 bits) -{ - sb_info_t *si; - volatile uint32 dummy; - uint32 rej; - sbconfig_t *sb; - - si = SB_INFO(sbh); - - ASSERT(GOODREGS(si->curmap)); - sb = REGS2SB(si->curmap); - - /* if core is already in reset, just return */ - if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET) - return; - - /* reject value changed between sonics 2.2 and 2.3 */ - if (si->sb.sonicsrev == SONICS_2_2) - rej = (1 << SBTML_REJ_SHIFT); - else - rej = (2 << SBTML_REJ_SHIFT); - - /* if clocks are not enabled, put into reset and return */ - if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0) - goto disable; - - /* set target reject and spin until busy is clear (preserve core-specific bits) */ - OR_SBREG(si, &sb->sbtmstatelow, rej); - dummy = R_SBREG(si, &sb->sbtmstatelow); - OSL_DELAY(1); - SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000); - if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY) - SB_ERROR(("%s: target state still busy\n", __FUNCTION__)); - - if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) { - OR_SBREG(si, &sb->sbimstate, SBIM_RJ); - dummy = R_SBREG(si, &sb->sbimstate); - OSL_DELAY(1); - SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000); - } - - /* set reset and reject while enabling the clocks */ - W_SBREG(si, &sb->sbtmstatelow, - (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET)); - dummy = R_SBREG(si, &sb->sbtmstatelow); - OSL_DELAY(10); - - /* don't forget to clear the initiator reject bit */ - if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) - AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ); - - disable: - /* leave reset and reject asserted */ - W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET)); - OSL_DELAY(1); -} - -/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */ -void sb_watchdog(sb_t * sbh, uint ticks) -{ - sb_info_t *si = SB_INFO(sbh); - - /* make sure we come up in fast clock mode; or if clearing, clear clock */ - if (ticks) - sb_clkctl_clk(sbh, CLK_FAST); - else - sb_clkctl_clk(sbh, CLK_DYNAMIC); - - if (sbh->chip == BCM4328_CHIP_ID && ticks != 0) - sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, min_res_mask), - PMURES_BIT(RES4328_ROM_SWITCH), - PMURES_BIT(RES4328_ROM_SWITCH)); - - /* instant NMI */ - switch (si->gpioid) { - case SB_CC: - sb_corereg(sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, - ticks); - break; - case SB_EXTIF: - sb_corereg(sbh, si->gpioidx, OFFSETOF(extifregs_t, watchdog), - ~0, ticks); - break; - } -} - -/* initialize the pcmcia core */ -void sb_pcmcia_init(sb_t * sbh) -{ - sb_info_t *si; - uint8 cor = 0; - - si = SB_INFO(sbh); - - /* enable d11 mac interrupts */ - OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1); - cor |= COR_IRQEN | COR_FUNEN; - OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1); - -} - -void BCMINITFN(sb_pci_up) (sb_t * sbh) { - sb_info_t *si = SB_INFO(sbh); - if (si->gpioid == SB_EXTIF) - return; - - /* if not pci bus, we're done */ - if (BUSTYPE(si->sb.bustype) != PCI_BUS) - return; - - if (FORCEHT_WAR32414(si)) - sb_war32414_forceHT(sbh, 1); - - if (PCIE_ASPMWARS(si) || si->sb.pr42780) - sb_pcieclkreq(sbh, 1, 0); - - if (PCIE(si) && - (((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev == 2)) || - ((si->sb.chip == BCM4312_CHIP_ID) && (si->sb.chiprev == 0)))) - sb_set_initiator_to((void *)si, 0x3, - sb_findcoreidx((void *)si, SB_D11, 0)); -} - -/* Unconfigure and/or apply various WARs when system is going to sleep mode */ -void BCMUNINITFN(sb_pci_sleep) (sb_t * sbh) { - sb_info_t *si = SB_INFO(sbh); - if (si->gpioid == SB_EXTIF) - return; - uint32 w; - - /* if not pci bus, we're done */ - if (!PCIE(si) || !PCIE_ASPMWARS(si)) - return; - - w = OSL_PCI_READ_CONFIG(si->osh, si->pciecap_lcreg_offset, - sizeof(uint32)); - w &= ~PCIE_CAP_LCREG_ASPML1; - OSL_PCI_WRITE_CONFIG(si->osh, si->pciecap_lcreg_offset, sizeof(uint32), - w); -} - -/* Unconfigure and/or apply various WARs when going down */ -void BCMINITFN(sb_pci_down) (sb_t * sbh) { - sb_info_t *si = SB_INFO(sbh); - if (si->gpioid == SB_EXTIF) - return; - - /* if not pci bus, we're done */ - if (BUSTYPE(si->sb.bustype) != PCI_BUS) - return; - - if (FORCEHT_WAR32414(si)) - sb_war32414_forceHT(sbh, 0); - - if (si->pr42767_war) { - sb_pcieclkreq(sbh, 1, 1); - si->pr42767_war = FALSE; - } else if (si->sb.pr42780) { - sb_pcieclkreq(sbh, 1, 1); - } -} - -static void BCMINITFN(sb_war42767_clkreq) (sb_t * sbh) { - sbpcieregs_t *pcieregs; - uint16 val16, *reg16; - sb_info_t *si; - - si = SB_INFO(sbh); - - /* if not pcie bus, we're done */ - if (!PCIE(si) || !PCIE_ASPMWARS(si)) - return; - - pcieregs = (sbpcieregs_t *) sb_setcoreidx(sbh, si->sb.buscoreidx); - reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET]; - val16 = R_REG(si->osh, reg16); - /* if clockreq is not advertized advertize it */ - if (!si->pcie_war_ovr) { - val16 |= SRSH_CLKREQ_ENB; - si->pr42767_war = TRUE; - - si->sb.pr42780 = TRUE; - } else - val16 &= ~SRSH_CLKREQ_ENB; - W_REG(si->osh, reg16, val16); -} - -static void BCMINITFN(sb_war42767) (sb_t * sbh) { - uint32 w = 0; - sb_info_t *si; - - si = SB_INFO(sbh); - - /* if not pcie bus, we're done */ - if (!PCIE(si) || !PCIE_ASPMWARS(si)) - return; - - sb_pcie_mdioread(si, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w); - if (w & PLL_CTRL_FREQDET_EN) { - w &= ~PLL_CTRL_FREQDET_EN; - sb_pcie_mdiowrite(si, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w); - } -} - -/* - * Configure the pci core for pci client (NIC) action - * coremask is the bitvec of cores by index to be enabled. - */ -void BCMINITFN(sb_pci_setup) (sb_t * sbh, uint coremask) { - sb_info_t *si; - sbconfig_t *sb; - sbpciregs_t *pciregs; - uint32 sbflag; - uint32 w; - uint idx; - - si = SB_INFO(sbh); - - /* if not pci bus, we're done */ - if (BUSTYPE(si->sb.bustype) != PCI_BUS) - return; - - ASSERT(PCI(si) || PCIE(si)); - ASSERT(si->sb.buscoreidx != BADIDX); - - /* get current core index */ - idx = si->curidx; - - /* we interrupt on this backplane flag number */ - ASSERT(GOODREGS(si->curmap)); - sb = REGS2SB(si->curmap); - sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK; - - /* switch over to pci core */ - pciregs = (sbpciregs_t *) sb_setcoreidx(sbh, si->sb.buscoreidx); - sb = REGS2SB(pciregs); - - /* - * Enable sb->pci interrupts. Assume - * PCI rev 2.3 support was added in pci core rev 6 and things changed.. - */ - if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) { - /* pci config write to set this core bit in PCIIntMask */ - w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32)); - w |= (coremask << PCI_SBIM_SHIFT); - OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w); - } else { - /* set sbintvec bit for our flag number */ - OR_SBREG(si, &sb->sbintvec, (1 << sbflag)); - } - - if (PCI(si)) { - OR_REG(si->osh, &pciregs->sbtopci2, - (SBTOPCI_PREF | SBTOPCI_BURST)); - if (si->sb.buscorerev >= 11) - OR_REG(si->osh, &pciregs->sbtopci2, - SBTOPCI_RC_READMULTI); - if (si->sb.buscorerev < 5) { - SET_SBREG(si, &sb->sbimconfiglow, - SBIMCL_RTO_MASK | SBIMCL_STO_MASK, - (0x3 << SBIMCL_RTO_SHIFT) | 0x2); - sb_commit(sbh); - } - } - - /* PCIE workarounds */ - if (PCIE(si)) { - if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) { - w = sb_pcie_readreg((void *)(uintptr) sbh, - (void *)(uintptr) PCIE_PCIEREGS, - PCIE_TLP_WORKAROUNDSREG); - w |= 0x8; - sb_pcie_writereg((void *)(uintptr) sbh, - (void *)(uintptr) PCIE_PCIEREGS, - PCIE_TLP_WORKAROUNDSREG, w); - } - - if (si->sb.buscorerev == 1) { - w = sb_pcie_readreg((void *)(uintptr) sbh, - (void *)(uintptr) PCIE_PCIEREGS, - PCIE_DLLP_LCREG); - w |= (0x40); - sb_pcie_writereg((void *)(uintptr) sbh, - (void *)(uintptr) PCIE_PCIEREGS, - PCIE_DLLP_LCREG, w); - } - - if (si->sb.buscorerev == 0) - sb_war30841(si); - - if ((si->sb.buscorerev >= 3) && (si->sb.buscorerev <= 5)) { - w = sb_pcie_readreg((void *)(uintptr) sbh, - (void *)(uintptr) PCIE_PCIEREGS, - PCIE_DLLP_PMTHRESHREG); - w &= ~(PCIE_L1THRESHOLDTIME_MASK); - w |= (PCIE_L1THRESHOLD_WARVAL << - PCIE_L1THRESHOLDTIME_SHIFT); - sb_pcie_writereg((void *)(uintptr) sbh, - (void *)(uintptr) PCIE_PCIEREGS, - PCIE_DLLP_PMTHRESHREG, w); - - sb_war43448(sbh); - - sb_war42767(sbh); - - sb_war43448_aspm(sbh); - sb_war42767_clkreq(sbh); - } - } - - /* switch back to previous core */ - sb_setcoreidx(sbh, idx); -} - -uint32 sb_base(uint32 admatch) -{ - uint32 base; - uint type; - - type = admatch & SBAM_TYPE_MASK; - ASSERT(type < 3); - - base = 0; - - if (type == 0) { - base = admatch & SBAM_BASE0_MASK; - } else if (type == 1) { - ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */ - base = admatch & SBAM_BASE1_MASK; - } else if (type == 2) { - ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */ - base = admatch & SBAM_BASE2_MASK; - } - - return (base); -} - -uint32 sb_size(uint32 admatch) -{ - uint32 size; - uint type; - - type = admatch & SBAM_TYPE_MASK; - ASSERT(type < 3); - - size = 0; - - if (type == 0) { - size = - 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + - 1); - } else if (type == 1) { - ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */ - size = - 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + - 1); - } else if (type == 2) { - ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */ - size = - 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + - 1); - } - - return (size); -} - -/* return the core-type instantiation # of the current core */ -uint sb_coreunit(sb_t * sbh) -{ - sb_info_t *si; - uint idx; - uint coreid; - uint coreunit; - uint i; - - si = SB_INFO(sbh); - coreunit = 0; - - idx = si->curidx; - - ASSERT(GOODREGS(si->curmap)); - coreid = sb_coreid(sbh); - - /* count the cores of our type */ - for (i = 0; i < idx; i++) - if (si->coreid[i] == coreid) - coreunit++; - - return (coreunit); -} - -static uint32 BCMINITFN(factor6) (uint32 x) { - switch (x) { - case CC_F6_2: - return 2; - case CC_F6_3: - return 3; - case CC_F6_4: - return 4; - case CC_F6_5: - return 5; - case CC_F6_6: - return 6; - case CC_F6_7: - return 7; - default: - return 0; - } -} - -/* calculate the speed the SB would run at given a set of clockcontrol values */ -uint32 BCMINITFN(sb_clock_rate) (uint32 pll_type, uint32 n, uint32 m) { - uint32 n1, n2, clock, m1, m2, m3, mc; - - n1 = n & CN_N1_MASK; - n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT; - - if (pll_type == PLL_TYPE6) { - if (m & CC_T6_MMASK) - return CC_T6_M1; - else - return CC_T6_M0; - } else if ((pll_type == PLL_TYPE1) || - (pll_type == PLL_TYPE3) || - (pll_type == PLL_TYPE4) || (pll_type == PLL_TYPE7)) { - n1 = factor6(n1); - n2 += CC_F5_BIAS; - } else if (pll_type == PLL_TYPE2) { - n1 += CC_T2_BIAS; - n2 += CC_T2_BIAS; - ASSERT((n1 >= 2) && (n1 <= 7)); - ASSERT((n2 >= 5) && (n2 <= 23)); - } else if (pll_type == PLL_TYPE5) { - return (100000000); - } else - ASSERT(0); - /* PLL types 3 and 7 use BASE2 (25Mhz) */ - if ((pll_type == PLL_TYPE3) || (pll_type == PLL_TYPE7)) { - clock = CC_CLOCK_BASE2 * n1 * n2; - } else - clock = CC_CLOCK_BASE1 * n1 * n2; - - if (clock == 0) - return 0; - - m1 = m & CC_M1_MASK; - m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT; - m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT; - mc = (m & CC_MC_MASK) >> CC_MC_SHIFT; - - if ((pll_type == PLL_TYPE1) || - (pll_type == PLL_TYPE3) || - (pll_type == PLL_TYPE4) || (pll_type == PLL_TYPE7)) { - m1 = factor6(m1); - if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3)) - m2 += CC_F5_BIAS; - else - m2 = factor6(m2); - m3 = factor6(m3); - - switch (mc) { - case CC_MC_BYPASS: - return (clock); - case CC_MC_M1: - return (clock / m1); - case CC_MC_M1M2: - return (clock / (m1 * m2)); - case CC_MC_M1M2M3: - return (clock / (m1 * m2 * m3)); - case CC_MC_M1M3: - return (clock / (m1 * m3)); - default: - return (0); - } - } else { - ASSERT(pll_type == PLL_TYPE2); - - m1 += CC_T2_BIAS; - m2 += CC_T2M2_BIAS; - m3 += CC_T2_BIAS; - ASSERT((m1 >= 2) && (m1 <= 7)); - ASSERT((m2 >= 3) && (m2 <= 10)); - ASSERT((m3 >= 2) && (m3 <= 7)); - - if ((mc & CC_T2MC_M1BYP) == 0) - clock /= m1; - if ((mc & CC_T2MC_M2BYP) == 0) - clock /= m2; - if ((mc & CC_T2MC_M3BYP) == 0) - clock /= m3; - - return (clock); - } -} - -/* returns the current speed the SB is running at */ -uint32 BCMINITFN(sb_clock) (sb_t * sbh) { - sb_info_t *si; - extifregs_t *eir; - chipcregs_t *cc; - uint32 n, m; - uint idx; - uint32 cap, pll_type, rate; - uint intr_val = 0; - - si = SB_INFO(sbh); - idx = si->curidx; - pll_type = PLL_TYPE1; - - INTR_OFF(si, intr_val); - - /* switch to extif or chipc core */ - if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) { - n = R_REG(si->osh, &eir->clockcontrol_n); - m = R_REG(si->osh, &eir->clockcontrol_sb); - } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) { - - cap = R_REG(si->osh, &cc->capabilities); - - if (cap & CC_CAP_PMU) { - - if (sb_chip(sbh) == BCM5354_CHIP_ID) { - /* 5354 has a constant sb clock of 120MHz */ - rate = 120000000; - goto end; - } else - if (sb_chip(sbh) == BCM4328_CHIP_ID) { - rate = 80000000; - goto end; - } else - ASSERT(0); - } - - pll_type = cap & CC_CAP_PLL_MASK; - if (pll_type == PLL_NONE) { - INTR_RESTORE(si, intr_val); - return 80000000; - } - n = R_REG(si->osh, &cc->clockcontrol_n); - if (pll_type == PLL_TYPE6) - m = R_REG(si->osh, &cc->clockcontrol_m3); - else if (pll_type == PLL_TYPE3 - && !(BCMINIT(sb_chip) (sbh) == 0x5365)) - m = R_REG(si->osh, &cc->clockcontrol_m2); - else - m = R_REG(si->osh, &cc->clockcontrol_sb); - } else { - INTR_RESTORE(si, intr_val); - return 0; - } - - /* calculate rate */ - if (BCMINIT(sb_chip) (sbh) == 0x5365) - rate = 100000000; - else { - rate = sb_clock_rate(pll_type, n, m); - - if (pll_type == PLL_TYPE3) - rate = rate / 2; - } - - end: - /* switch back to previous core */ - sb_setcoreidx(sbh, idx); - - INTR_RESTORE(si, intr_val); - - return rate; -} - -uint32 BCMINITFN(sb_alp_clock) (sb_t * sbh) { - uint32 clock = ALP_CLOCK; - - if (sbh->cccaps & CC_CAP_PMU) - clock = sb_pmu_alp_clock(sbh, sb_osh(sbh)); - - return clock; -} - -/* change logical "focus" to the gpio core for optimized access */ -void *sb_gpiosetcore(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - - return (sb_setcoreidx(sbh, si->gpioidx)); -} - -/* mask&set gpiocontrol bits */ -uint32 sb_gpiocontrol(sb_t * sbh, uint32 mask, uint32 val, uint8 priority) -{ - sb_info_t *si; - uint regoff; - - si = SB_INFO(sbh); - regoff = 0; - - /* gpios could be shared on router platforms - * ignore reservation if it's high priority (e.g., test apps) - */ - if ((priority != GPIO_HI_PRIORITY) && - (BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) { - mask = priority ? (sb_gpioreservation & mask) : - ((sb_gpioreservation | mask) & ~(sb_gpioreservation)); - val &= mask; - } - - switch (si->gpioid) { - case SB_CC: - regoff = OFFSETOF(chipcregs_t, gpiocontrol); - break; - - case SB_PCI: - regoff = OFFSETOF(sbpciregs_t, gpiocontrol); - break; - - case SB_EXTIF: - return (0); - } - - return (sb_corereg(sbh, si->gpioidx, regoff, mask, val)); -} - -/* mask&set gpio output enable bits */ -uint32 sb_gpioouten(sb_t * sbh, uint32 mask, uint32 val, uint8 priority) -{ - sb_info_t *si; - uint regoff; - - si = SB_INFO(sbh); - regoff = 0; - - /* gpios could be shared on router platforms - * ignore reservation if it's high priority (e.g., test apps) - */ - if ((priority != GPIO_HI_PRIORITY) && - (BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) { - mask = priority ? (sb_gpioreservation & mask) : - ((sb_gpioreservation | mask) & ~(sb_gpioreservation)); - val &= mask; - } - - switch (si->gpioid) { - case SB_CC: - regoff = OFFSETOF(chipcregs_t, gpioouten); - break; - - case SB_PCI: - regoff = OFFSETOF(sbpciregs_t, gpioouten); - break; - - case SB_EXTIF: - regoff = OFFSETOF(extifregs_t, gpio[0].outen); - break; - } - - return (sb_corereg(sbh, si->gpioidx, regoff, mask, val)); -} - -/* mask&set gpio output bits */ -uint32 sb_gpioout(sb_t * sbh, uint32 mask, uint32 val, uint8 priority) -{ - sb_info_t *si; - uint regoff; - - si = SB_INFO(sbh); - regoff = 0; - - /* gpios could be shared on router platforms - * ignore reservation if it's high priority (e.g., test apps) - */ - if ((priority != GPIO_HI_PRIORITY) && - (BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) { - mask = priority ? (sb_gpioreservation & mask) : - ((sb_gpioreservation | mask) & ~(sb_gpioreservation)); - val &= mask; - } - - switch (si->gpioid) { - case SB_CC: - regoff = OFFSETOF(chipcregs_t, gpioout); - break; - - case SB_PCI: - regoff = OFFSETOF(sbpciregs_t, gpioout); - break; - - case SB_EXTIF: - regoff = OFFSETOF(extifregs_t, gpio[0].out); - break; - } - - return (sb_corereg(sbh, si->gpioidx, regoff, mask, val)); -} - -/* reserve one gpio */ -uint32 sb_gpioreserve(sb_t * sbh, uint32 gpio_bitmask, uint8 priority) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - - /* only cores on SB_BUS share GPIO's and only applcation users need to - * reserve/release GPIO - */ - if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) { - ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority)); - return -1; - } - /* make sure only one bit is set */ - if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) { - ASSERT((gpio_bitmask) - && !((gpio_bitmask) & (gpio_bitmask - 1))); - return -1; - } - - /* already reserved */ - if (sb_gpioreservation & gpio_bitmask) - return -1; - /* set reservation */ - sb_gpioreservation |= gpio_bitmask; - - return sb_gpioreservation; -} - -/* release one gpio */ -/* - * releasing the gpio doesn't change the current value on the GPIO last write value - * persists till some one overwrites it -*/ - -uint32 sb_gpiorelease(sb_t * sbh, uint32 gpio_bitmask, uint8 priority) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - - /* only cores on SB_BUS share GPIO's and only applcation users need to - * reserve/release GPIO - */ - if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) { - ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority)); - return -1; - } - /* make sure only one bit is set */ - if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) { - ASSERT((gpio_bitmask) - && !((gpio_bitmask) & (gpio_bitmask - 1))); - return -1; - } - - /* already released */ - if (!(sb_gpioreservation & gpio_bitmask)) - return -1; - - /* clear reservation */ - sb_gpioreservation &= ~gpio_bitmask; - - return sb_gpioreservation; -} - -/* return the current gpioin register value */ -uint32 sb_gpioin(sb_t * sbh) -{ - sb_info_t *si; - uint regoff; - - si = SB_INFO(sbh); - regoff = 0; - - switch (si->gpioid) { - case SB_CC: - regoff = OFFSETOF(chipcregs_t, gpioin); - break; - - case SB_PCI: - regoff = OFFSETOF(sbpciregs_t, gpioin); - break; - - case SB_EXTIF: - regoff = OFFSETOF(extifregs_t, gpioin); - break; - } - - return (sb_corereg(sbh, si->gpioidx, regoff, 0, 0)); -} - -/* mask&set gpio interrupt polarity bits */ -uint32 sb_gpiointpolarity(sb_t * sbh, uint32 mask, uint32 val, uint8 priority) -{ - sb_info_t *si; - uint regoff; - - si = SB_INFO(sbh); - regoff = 0; - - /* gpios could be shared on router platforms */ - if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) { - mask = priority ? (sb_gpioreservation & mask) : - ((sb_gpioreservation | mask) & ~(sb_gpioreservation)); - val &= mask; - } - - switch (si->gpioid) { - case SB_CC: - regoff = OFFSETOF(chipcregs_t, gpiointpolarity); - break; - - case SB_PCI: - /* pci gpio implementation does not support interrupt polarity */ - ASSERT(0); - break; - - case SB_EXTIF: - regoff = OFFSETOF(extifregs_t, gpiointpolarity); - break; - } - - return (sb_corereg(sbh, si->gpioidx, regoff, mask, val)); -} - -/* mask&set gpio interrupt mask bits */ -uint32 sb_gpiointmask(sb_t * sbh, uint32 mask, uint32 val, uint8 priority) -{ - sb_info_t *si; - uint regoff; - - si = SB_INFO(sbh); - regoff = 0; - - /* gpios could be shared on router platforms */ - if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) { - mask = priority ? (sb_gpioreservation & mask) : - ((sb_gpioreservation | mask) & ~(sb_gpioreservation)); - val &= mask; - } - - switch (si->gpioid) { - case SB_CC: - regoff = OFFSETOF(chipcregs_t, gpiointmask); - break; - - case SB_PCI: - /* pci gpio implementation does not support interrupt mask */ - ASSERT(0); - break; - - case SB_EXTIF: - regoff = OFFSETOF(extifregs_t, gpiointmask); - break; - } - - return (sb_corereg(sbh, si->gpioidx, regoff, mask, val)); -} - -/* assign the gpio to an led */ -uint32 sb_gpioled(sb_t * sbh, uint32 mask, uint32 val) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - if (si->sb.ccrev < 16) - return -1; - - /* gpio led powersave reg */ - return (sb_corereg - (sbh, SB_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, - val)); -} - -/* mask&set gpio timer val */ -uint32 sb_gpiotimerval(sb_t * sbh, uint32 mask, uint32 gpiotimerval) -{ - sb_info_t *si; - si = SB_INFO(sbh); - - if (si->sb.ccrev < 16) - return -1; - - return (sb_corereg(sbh, SB_CC_IDX, - OFFSETOF(chipcregs_t, gpiotimerval), mask, - gpiotimerval)); -} - -uint32 sb_gpiopull(sb_t * sbh, bool updown, uint32 mask, uint32 val) -{ - sb_info_t *si; - uint offs; - - si = SB_INFO(sbh); - if (si->sb.ccrev < 20) - return -1; - - offs = - (updown ? OFFSETOF(chipcregs_t, gpiopulldown) : - OFFSETOF(chipcregs_t, gpiopullup)); - return (sb_corereg(sbh, SB_CC_IDX, offs, mask, val)); -} - -uint32 sb_gpioevent(sb_t * sbh, uint regtype, uint32 mask, uint32 val) -{ - sb_info_t *si; - uint offs; - - si = SB_INFO(sbh); - if (si->sb.ccrev < 11) - return -1; - - if (regtype == GPIO_REGEVT) - offs = OFFSETOF(chipcregs_t, gpioevent); - else if (regtype == GPIO_REGEVT_INTMSK) - offs = OFFSETOF(chipcregs_t, gpioeventintmask); - else if (regtype == GPIO_REGEVT_INTPOL) - offs = OFFSETOF(chipcregs_t, gpioeventintpolarity); - else - return -1; - - return (sb_corereg(sbh, SB_CC_IDX, offs, mask, val)); -} - -void *BCMINITFN(sb_gpio_handler_register) (sb_t * sbh, uint32 event, - bool level, gpio_handler_t cb, - void *arg) { - sb_info_t *si; - gpioh_item_t *gi; - - ASSERT(event); - ASSERT(cb); - - si = SB_INFO(sbh); - if (si->sb.ccrev < 11) - return NULL; - - if ((gi = MALLOC(si->osh, sizeof(gpioh_item_t))) == NULL) - return NULL; - - bzero(gi, sizeof(gpioh_item_t)); - gi->event = event; - gi->handler = cb; - gi->arg = arg; - gi->level = level; - - gi->next = si->gpioh_head; - si->gpioh_head = gi; - - return (void *)(gi); -} - -void BCMINITFN(sb_gpio_handler_unregister) (sb_t * sbh, void *gpioh) { - sb_info_t *si; - gpioh_item_t *p, *n; - - si = SB_INFO(sbh); - if (si->sb.ccrev < 11) - return; - - ASSERT(si->gpioh_head); - if ((void *)si->gpioh_head == gpioh) { - si->gpioh_head = si->gpioh_head->next; - MFREE(si->osh, gpioh, sizeof(gpioh_item_t)); - return; - } else { - p = si->gpioh_head; - n = p->next; - while (n) { - if ((void *)n == gpioh) { - p->next = n->next; - MFREE(si->osh, gpioh, sizeof(gpioh_item_t)); - return; - } - p = n; - n = n->next; - } - } - - ASSERT(0); /* Not found in list */ -} - -void sb_gpio_handler_process(sb_t * sbh) -{ - sb_info_t *si; - gpioh_item_t *h; - uint32 status; - uint32 level = sb_gpioin(sbh); - uint32 edge = sb_gpioevent(sbh, GPIO_REGEVT, 0, 0); - - si = SB_INFO(sbh); - for (h = si->gpioh_head; h != NULL; h = h->next) { - if (h->handler) { - status = (h->level ? level : edge); - - if (status & h->event) - h->handler(status, h->arg); - } - } - - sb_gpioevent(sbh, GPIO_REGEVT, edge, edge); /* clear edge-trigger status */ -} - -uint32 sb_gpio_int_enable(sb_t * sbh, bool enable) -{ - sb_info_t *si; - uint offs; - - si = SB_INFO(sbh); - if (si->sb.ccrev < 11) - return -1; - - offs = OFFSETOF(chipcregs_t, intmask); - return (sb_corereg - (sbh, SB_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0))); -} - -#ifdef BCMDBG -void sb_dump(sb_t * sbh, struct bcmstrbuf *b) -{ - sb_info_t *si; - uint i; - - si = SB_INFO(sbh); - - bcm_bprintf(b, - "si %p chip 0x%x chiprev 0x%x boardtype 0x%x boardvendor 0x%x bus %d\n", - si, si->sb.chip, si->sb.chiprev, si->sb.boardtype, - si->sb.boardvendor, si->sb.bustype); - bcm_bprintf(b, "osh %p curmap %p\n", si->osh, si->curmap); - bcm_bprintf(b, - "sonicsrev %d ccrev %d buscoretype 0x%x buscorerev %d curidx %d\n", - si->sb.sonicsrev, si->sb.ccrev, si->sb.buscoretype, - si->sb.buscorerev, si->curidx); - - bcm_bprintf(b, "forceHT %d ASPM overflowPR42780 %d pcie_polarity %d\n", - si->sb.pr32414, si->sb.pr42780, si->pcie_polarity); - - bcm_bprintf(b, "cores: "); - for (i = 0; i < si->numcores; i++) - bcm_bprintf(b, "0x%x ", si->coreid[i]); - bcm_bprintf(b, "\n"); -} - -/* print interesting sbconfig registers */ -void sb_dumpregs(sb_t * sbh, struct bcmstrbuf *b) -{ - sb_info_t *si; - sbconfig_t *sb; - uint origidx; - uint curidx, i, intr_val = 0; - - si = SB_INFO(sbh); - origidx = si->curidx; - - INTR_OFF(si, intr_val); - curidx = si->curidx; - - for (i = 0; i < si->numcores; i++) { - sb = REGS2SB(sb_setcoreidx(sbh, i)); - - bcm_bprintf(b, "core 0x%x: \n", si->coreid[i]); - bcm_bprintf(b, - "sbtmstatelow 0x%x sbtmstatehigh 0x%x sbidhigh 0x%x " - "sbimstate 0x%x\n sbimconfiglow 0x%x sbimconfighigh 0x%x\n", - R_SBREG(si, &sb->sbtmstatelow), R_SBREG(si, - &sb-> - sbtmstatehigh), - R_SBREG(si, &sb->sbidhigh), R_SBREG(si, - &sb->sbimstate), - R_SBREG(si, &sb->sbimconfiglow), R_SBREG(si, - &sb-> - sbimconfighigh)); - } - - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); -} - -void sb_view(sb_t * sbh) -{ - sb_info_t *si; - sbconfig_t *sb; - - si = SB_INFO(sbh); - sb = REGS2SB(si->curmap); - - if (si->sb.sonicsrev > SONICS_2_2) - SB_ERROR(("sbimerrlog 0x%x sbimerrloga 0x%x\n", - sb_corereg(sbh, sb_coreidx(&si->sb), SBIMERRLOG, 0, - 0), sb_corereg(sbh, sb_coreidx(&si->sb), - SBIMERRLOGA, 0, 0))); - - SB_ERROR(("sbipsflag 0x%x sbtpsflag 0x%x sbtmerrloga 0x%x sbtmerrlog 0x%x\n", R_SBREG(si, &sb->sbipsflag), R_SBREG(si, &sb->sbtpsflag), R_SBREG(si, &sb->sbtmerrloga), R_SBREG(si, &sb->sbtmerrlog))); - SB_ERROR(("sbadmatch3 0x%x sbadmatch2 0x%x sbadmatch1 0x%x\n", - R_SBREG(si, &sb->sbadmatch3), R_SBREG(si, &sb->sbadmatch2), - R_SBREG(si, &sb->sbadmatch1))); - SB_ERROR(("sbimstate 0x%x sbintvec 0x%x sbtmstatelow 0x%x sbtmstatehigh 0x%x\n", R_SBREG(si, &sb->sbimstate), R_SBREG(si, &sb->sbintvec), R_SBREG(si, &sb->sbtmstatelow), R_SBREG(si, &sb->sbtmstatehigh))); - SB_ERROR(("sbbwa0 0x%x sbimconfiglow 0x%x sbimconfighigh 0x%x sbadmatch0 0x%x\n", R_SBREG(si, &sb->sbbwa0), R_SBREG(si, &sb->sbimconfiglow), R_SBREG(si, &sb->sbimconfighigh), R_SBREG(si, &sb->sbadmatch0))); - SB_ERROR(("sbtmconfiglow 0x%x sbtmconfighigh 0x%x sbbconfig 0x%x sbbstate 0x%x\n", R_SBREG(si, &sb->sbtmconfiglow), R_SBREG(si, &sb->sbtmconfighigh), R_SBREG(si, &sb->sbbconfig), R_SBREG(si, &sb->sbbstate))); - SB_ERROR(("sbactcnfg 0x%x sbflagst 0x%x sbidlow 0x%x sbidhigh 0x%x\n", - R_SBREG(si, &sb->sbactcnfg), R_SBREG(si, &sb->sbflagst), - R_SBREG(si, &sb->sbidlow), R_SBREG(si, &sb->sbidhigh))); -} - -void sb_viewall(sb_t * sbh) -{ - sb_info_t *si; - uint curidx, i; - uint intr_val = 0; - - si = SB_INFO(sbh); - curidx = si->curidx; - - for (i = 0; i < si->numcores; i++) { - INTR_OFF(si, intr_val); - sb_setcoreidx(sbh, i); - sb_view(sbh); - INTR_RESTORE(si, intr_val); - } - - sb_setcoreidx(sbh, curidx); -} -#endif /* BCMDBG */ - -/* return the slow clock source - LPO, XTAL, or PCI */ -static uint sb_slowclk_src(sb_info_t * si) -{ - chipcregs_t *cc; - - ASSERT(sb_coreid(&si->sb) == SB_CC); - - if (si->sb.ccrev < 6) { - if ((BUSTYPE(si->sb.bustype) == PCI_BUS) && - (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) - & PCI_CFG_GPIO_SCS)) - return (SCC_SS_PCI); - else - return (SCC_SS_XTAL); - } else if (si->sb.ccrev < 10) { - cc = (chipcregs_t *) sb_setcoreidx(&si->sb, si->curidx); - return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK); - } else /* Insta-clock */ - return (SCC_SS_XTAL); -} - -/* return the ILP (slowclock) min or max frequency */ -static uint sb_slowclk_freq(sb_info_t * si, bool max_freq) -{ - chipcregs_t *cc; - uint32 slowclk; - uint div; - - ASSERT(sb_coreid(&si->sb) == SB_CC); - - cc = (chipcregs_t *) sb_setcoreidx(&si->sb, si->curidx); - - /* shouldn't be here unless we've established the chip has dynamic clk control */ - ASSERT(R_REG(si->osh, &cc->capabilities) & CC_CAP_PWR_CTL); - - slowclk = sb_slowclk_src(si); - if (si->sb.ccrev < 6) { - if (slowclk == SCC_SS_PCI) - return (max_freq ? (PCIMAXFREQ / 64) - : (PCIMINFREQ / 64)); - else - return (max_freq ? (XTALMAXFREQ / 32) - : (XTALMINFREQ / 32)); - } else if (si->sb.ccrev < 10) { - div = - 4 * - (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> - SCC_CD_SHIFT) - + 1); - if (slowclk == SCC_SS_LPO) - return (max_freq ? LPOMAXFREQ : LPOMINFREQ); - else if (slowclk == SCC_SS_XTAL) - return (max_freq ? (XTALMAXFREQ / div) - : (XTALMINFREQ / div)); - else if (slowclk == SCC_SS_PCI) - return (max_freq ? (PCIMAXFREQ / div) - : (PCIMINFREQ / div)); - else - ASSERT(0); - } else { - /* Chipc rev 10 is InstaClock */ - div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; - div = 4 * (div + 1); - return (max_freq ? XTALMAXFREQ : (XTALMINFREQ / div)); - } - return (0); -} - -static void BCMINITFN(sb_clkctl_setdelay) (sb_info_t * si, void *chipcregs) { - chipcregs_t *cc; - uint slowmaxfreq, pll_delay, slowclk; - uint pll_on_delay, fref_sel_delay; - - pll_delay = PLL_DELAY; - - /* If the slow clock is not sourced by the xtal then add the xtal_on_delay - * since the xtal will also be powered down by dynamic clk control logic. - */ - - slowclk = sb_slowclk_src(si); - if (slowclk != SCC_SS_XTAL) - pll_delay += XTAL_ON_DELAY; - - /* Starting with 4318 it is ILP that is used for the delays */ - slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE); - - pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; - fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; - - cc = (chipcregs_t *) chipcregs; - W_REG(si->osh, &cc->pll_on_delay, pll_on_delay); - W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay); -} - -/* initialize power control delay registers */ -void BCMINITFN(sb_clkctl_init) (sb_t * sbh) { - sb_info_t *si; - uint origidx; - chipcregs_t *cc; - - si = SB_INFO(sbh); - - origidx = si->curidx; - - if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0)) == NULL) - return; - - if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2)) - W_REG(si->osh, &cc->chipcontrol, - (si->sb.chiprev == - 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT); - - if (!(R_REG(si->osh, &cc->capabilities) & CC_CAP_PWR_CTL)) - goto done; - - /* set all Instaclk chip ILP to 1 MHz */ - if (si->sb.ccrev >= 10) - SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK, - (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); - - sb_clkctl_setdelay(si, (void *)(uintptr) cc); - - done: - sb_setcoreidx(sbh, origidx); -} - -/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */ -uint16 BCMINITFN(sb_clkctl_fast_pwrup_delay) (sb_t * sbh) { - sb_info_t *si; - uint origidx; - chipcregs_t *cc; - uint slowminfreq; - uint16 fpdelay; - uint intr_val = 0; - - si = SB_INFO(sbh); - fpdelay = 0; - origidx = si->curidx; - - INTR_OFF(si, intr_val); - - if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0)) == NULL) - goto done; - - if (sbh->cccaps & CC_CAP_PMU) { - fpdelay = sb_pmu_fast_pwrup_delay(sbh, si->osh); - goto done; - } - - if (!(sbh->cccaps & CC_CAP_PWR_CTL)) - goto done; - - slowminfreq = sb_slowclk_freq(si, FALSE); - fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) + - (slowminfreq - 1)) / slowminfreq; - - done: - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); - return (fpdelay); -} - -/* turn primary xtal and/or pll off/on */ -int sb_clkctl_xtal(sb_t * sbh, uint what, bool on) -{ - sb_info_t *si; - uint32 in, out, outen; - - si = SB_INFO(sbh); - - switch (BUSTYPE(si->sb.bustype)) { - - case PCMCIA_BUS: - return (0); - - case PCI_BUS: - - /* pcie core doesn't have any mapping to control the xtal pu */ - if (PCIE(si)) - return -1; - - in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32)); - out = - OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)); - outen = - OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, - sizeof(uint32)); - - /* - * Avoid glitching the clock if GPRS is already using it. - * We can't actually read the state of the PLLPD so we infer it - * by the value of XTAL_PU which *is* readable via gpioin. - */ - if (on && (in & PCI_CFG_GPIO_XTAL)) - return (0); - - if (what & XTAL) - outen |= PCI_CFG_GPIO_XTAL; - if (what & PLL) - outen |= PCI_CFG_GPIO_PLL; - - if (on) { - /* turn primary xtal on */ - if (what & XTAL) { - out |= PCI_CFG_GPIO_XTAL; - if (what & PLL) - out |= PCI_CFG_GPIO_PLL; - OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, - sizeof(uint32), out); - OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, - sizeof(uint32), outen); - OSL_DELAY(XTAL_ON_DELAY); - } - - /* turn pll on */ - if (what & PLL) { - out &= ~PCI_CFG_GPIO_PLL; - OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, - sizeof(uint32), out); - OSL_DELAY(2000); - } - } else { - if (what & XTAL) - out &= ~PCI_CFG_GPIO_XTAL; - if (what & PLL) - out |= PCI_CFG_GPIO_PLL; - OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, - sizeof(uint32), out); - OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, - sizeof(uint32), outen); - } - - default: - return (-1); - } - - return (0); -} - -/* set dynamic clk control mode (forceslow, forcefast, dynamic) */ -/* returns true if we are forcing fast clock */ -bool sb_clkctl_clk(sb_t * sbh, uint mode) -{ - sb_info_t *si; - uint origidx; - chipcregs_t *cc; - uint32 scc; - uint intr_val = 0; - - si = SB_INFO(sbh); - - /* chipcommon cores prior to rev6 don't support dynamic clock control */ - if (si->sb.ccrev < 6) - return (FALSE); - - /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */ - ASSERT(si->sb.ccrev != 10); - - INTR_OFF(si, intr_val); - - origidx = si->curidx; - - if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) && - (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10)) - goto done; - - if (FORCEHT_WAR32414(si)) - goto done; - - cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0); - ASSERT(cc != NULL); - - if (!(R_REG(si->osh, &cc->capabilities) & CC_CAP_PWR_CTL) - && (si->sb.ccrev < 20)) - goto done; - - switch (mode) { - case CLK_FAST: /* force fast (pll) clock */ - if (si->sb.ccrev < 10) { - /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */ - sb_clkctl_xtal(&si->sb, XTAL, ON); - - SET_REG(si->osh, &cc->slow_clk_ctl, - (SCC_XC | SCC_FS | SCC_IP), SCC_IP); - } else if (si->sb.ccrev < 20) { - OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR); - } else { - OR_REG(si->osh, &cc->clk_ctl_st, CCS_FORCEHT); - } - - /* wait for the PLL */ - if (R_REG(si->osh, &cc->capabilities) & CC_CAP_PMU) { - SPINWAIT(((R_REG(si->osh, &cc->clk_ctl_st) & - CCS_HTAVAIL) == 0), PMU_MAX_TRANSITION_DLY); - ASSERT(R_REG(si->osh, &cc->clk_ctl_st) & CCS_HTAVAIL); - } else { - OSL_DELAY(PLL_DELAY); - } - break; - - case CLK_DYNAMIC: /* enable dynamic clock control */ - if (si->sb.ccrev < 10) { - scc = R_REG(si->osh, &cc->slow_clk_ctl); - scc &= ~(SCC_FS | SCC_IP | SCC_XC); - if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) - scc |= SCC_XC; - W_REG(si->osh, &cc->slow_clk_ctl, scc); - - /* for dynamic control, we have to release our xtal_pu "force on" */ - if (scc & SCC_XC) - sb_clkctl_xtal(&si->sb, XTAL, OFF); - } else if (si->sb.ccrev < 20) { - /* Instaclock */ - AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR); - } else { - AND_REG(si->osh, &cc->clk_ctl_st, ~CCS_FORCEHT); - } - break; - - default: - ASSERT(0); - } - - done: - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); - return (mode == CLK_FAST); -} - -/* register driver interrupt disabling and restoring callback functions */ -void -sb_register_intr_callback(sb_t * sbh, void *intrsoff_fn, - void *intrsrestore_fn, void *intrsenabled_fn, - void *intr_arg) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - si->intr_arg = intr_arg; - si->intrsoff_fn = (sb_intrsoff_t) intrsoff_fn; - si->intrsrestore_fn = (sb_intrsrestore_t) intrsrestore_fn; - si->intrsenabled_fn = (sb_intrsenabled_t) intrsenabled_fn; - /* save current core id. when this function called, the current core - * must be the core which provides driver functions(il, et, wl, etc.) - */ - si->dev_coreid = si->coreid[si->curidx]; -} - -void sb_deregister_intr_callback(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - si->intrsoff_fn = NULL; -} - -#ifdef BCMDBG -/* dump dynamic clock control related registers */ -void sb_clkctl_dump(sb_t * sbh, struct bcmstrbuf *b) -{ - sb_info_t *si; - chipcregs_t *cc; - uint origidx; - uint intr_val = 0; - - si = SB_INFO(sbh); - - INTR_OFF(si, intr_val); - - origidx = si->curidx; - - if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0)) == NULL) { - INTR_RESTORE(si, intr_val); - return; - } - - if (!(R_REG(si->osh, &cc->capabilities) & CC_CAP_PWR_CTL)) - goto done; - - bcm_bprintf(b, "pll_on_delay 0x%x fref_sel_delay 0x%x ", - cc->pll_on_delay, cc->fref_sel_delay); - if ((si->sb.ccrev >= 6) && (si->sb.ccrev < 10)) - bcm_bprintf(b, "slow_clk_ctl 0x%x ", cc->slow_clk_ctl); - if (si->sb.ccrev >= 10) { - bcm_bprintf(b, "system_clk_ctl 0x%x ", cc->system_clk_ctl); - bcm_bprintf(b, "clkstatestretch 0x%x ", cc->clkstatestretch); - } - if (BUSTYPE(si->sb.bustype) == PCI_BUS) - bcm_bprintf(b, "gpioout 0x%x gpioouten 0x%x ", - OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, - sizeof(uint32)), - OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, - sizeof(uint32))); - bcm_bprintf(b, "\n"); - - done: - sb_setcoreidx(sbh, origidx); - INTR_RESTORE(si, intr_val); -} -#endif /* BCMDBG */ - -uint16 BCMINITFN(sb_d11_devid) (sb_t * sbh) { - sb_info_t *si = SB_INFO(sbh); - uint16 device; - -#if defined(BCM4328) - /* Fix device id for dual band BCM4328 */ - if (sbh->chip == BCM4328_CHIP_ID && - (sbh->chippkg == BCM4328USBDUAL_PKG_ID - || sbh->chippkg == BCM4328SDIODUAL_PKG_ID)) - device = BCM4328_D11DUAL_ID; - else -#endif /* BCM4328 */ - /* Let an nvram variable with devpath override devid */ - if ((device = (uint16) sb_getdevpathintvar(sbh, "devid")) != 0) ; - /* Get devid from OTP/SPROM depending on where the SROM is read */ - else if ((device = (uint16) getintvar(si->vars, "devid")) != 0) ; - /* - * no longer support wl0id, but keep the code - * here for backward compatibility. - */ - else if ((device = (uint16) getintvar(si->vars, "wl0id")) != 0) ; - /* Chip specific conversion */ - else if (sbh->chip == BCM4712_CHIP_ID) { - if (sbh->chippkg == BCM4712SMALL_PKG_ID) - device = BCM4306_D11G_ID; - else - device = BCM4306_D11DUAL_ID; - } - /* ignore it */ - else - device = 0xffff; - - return device; -} - -int -BCMINITFN(sb_corepciid) (sb_t * sbh, uint func, uint16 * pcivendor, - uint16 * pcidevice, uint8 * pciclass, - uint8 * pcisubclass, uint8 * pciprogif, - uint8 * pciheader) { - uint16 vendor = 0xffff, device = 0xffff; - uint8 class, subclass, progif = 0; - uint8 header = PCI_HEADER_NORMAL; - uint32 core = sb_coreid(sbh); - - /* Verify whether the function exists for the core */ - if (func >= (uint) (core == SB_USB20H ? 2 : 1)) - return -1; - - /* Known vendor translations */ - switch (sb_corevendor(sbh)) { - case SB_VEND_BCM: - vendor = VENDOR_BROADCOM; - break; - default: - return -1; - } - - /* Determine class based on known core codes */ - switch (core) { - case SB_ILINE20: - class = PCI_CLASS_NET; - subclass = PCI_NET_ETHER; - device = BCM47XX_ILINE_ID; - break; - case SB_ENET: - class = PCI_CLASS_NET; - subclass = PCI_NET_ETHER; - device = BCM47XX_ENET_ID; - break; - case SB_GIGETH: - class = PCI_CLASS_NET; - subclass = PCI_NET_ETHER; - device = BCM47XX_GIGETH_ID; - break; - case SB_SDRAM: - case SB_MEMC: - class = PCI_CLASS_MEMORY; - subclass = PCI_MEMORY_RAM; - device = (uint16) core; - break; - case SB_PCI: - case SB_PCIE: - class = PCI_CLASS_BRIDGE; - subclass = PCI_BRIDGE_PCI; - device = (uint16) core; - header = PCI_HEADER_BRIDGE; - break; - case SB_MIPS: - case SB_MIPS33: - class = PCI_CLASS_CPU; - subclass = PCI_CPU_MIPS; - device = (uint16) core; - break; - case SB_CODEC: - class = PCI_CLASS_COMM; - subclass = PCI_COMM_MODEM; - device = BCM47XX_V90_ID; - break; - case SB_USB: - class = PCI_CLASS_SERIAL; - subclass = PCI_SERIAL_USB; - progif = 0x10; /* OHCI */ - device = BCM47XX_USB_ID; - break; - case SB_USB11H: - class = PCI_CLASS_SERIAL; - subclass = PCI_SERIAL_USB; - progif = 0x10; /* OHCI */ - device = BCM47XX_USBH_ID; - break; - case SB_USB20H: - class = PCI_CLASS_SERIAL; - subclass = PCI_SERIAL_USB; - progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */ - device = BCM47XX_USB20H_ID; - header = 0x80; /* multifunction */ - break; - case SB_IPSEC: - class = PCI_CLASS_CRYPT; - subclass = PCI_CRYPT_NETWORK; - device = BCM47XX_IPSEC_ID; - break; - case SB_ROBO: - class = PCI_CLASS_NET; - subclass = PCI_NET_OTHER; - device = BCM47XX_ROBO_ID; - break; - case SB_EXTIF: - case SB_CC: - class = PCI_CLASS_MEMORY; - subclass = PCI_MEMORY_FLASH; - device = (uint16) core; - break; - case SB_SATAXOR: - class = PCI_CLASS_XOR; - subclass = PCI_XOR_QDMA; - device = BCM47XX_SATAXOR_ID; - break; - case SB_ATA100: - class = PCI_CLASS_DASDI; - subclass = PCI_DASDI_IDE; - device = BCM47XX_ATA100_ID; - break; - case SB_USB11D: - class = PCI_CLASS_SERIAL; - subclass = PCI_SERIAL_USB; - device = BCM47XX_USBD_ID; - break; - case SB_USB20D: - class = PCI_CLASS_SERIAL; - subclass = PCI_SERIAL_USB; - device = BCM47XX_USB20D_ID; - break; - case SB_D11: - class = PCI_CLASS_NET; - subclass = PCI_NET_OTHER; - device = sb_d11_devid(sbh); - break; - - default: - class = subclass = progif = 0xff; - device = (uint16) core; - break; - } - - *pcivendor = vendor; - *pcidevice = device; - *pciclass = class; - *pcisubclass = subclass; - *pciprogif = progif; - *pciheader = header; - - return 0; -} - -/* use the mdio interface to read from mdio slaves */ -static int -sb_pcie_mdioread(sb_info_t * si, uint physmedia, uint regaddr, uint * regval) -{ - uint mdiodata; - uint i = 0; - sbpcieregs_t *pcieregs; - - pcieregs = (sbpcieregs_t *) sb_setcoreidx(&si->sb, si->sb.buscoreidx); - ASSERT(pcieregs); - - /* enable mdio access to SERDES */ - W_REG(si->osh, (&pcieregs->mdiocontrol), - MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL); - - mdiodata = MDIODATA_START | MDIODATA_READ | - (physmedia << MDIODATA_DEVADDR_SHF) | - (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA; - - W_REG(si->osh, &pcieregs->mdiodata, mdiodata); - - PR28829_DELAY(); - - /* retry till the transaction is complete */ - while (i < 10) { - if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & - MDIOCTL_ACCESS_DONE) { - PR28829_DELAY(); - *regval = - (R_REG(si->osh, &(pcieregs->mdiodata)) & - MDIODATA_MASK); - /* Disable mdio access to SERDES */ - W_REG(si->osh, (&pcieregs->mdiocontrol), 0); - return 0; - } - OSL_DELAY(1000); - i++; - } - - SB_ERROR(("sb_pcie_mdioread: timed out\n")); - /* Disable mdio access to SERDES */ - W_REG(si->osh, (&pcieregs->mdiocontrol), 0); - return 1; -} - -/* use the mdio interface to write to mdio slaves */ -static int -sb_pcie_mdiowrite(sb_info_t * si, uint physmedia, uint regaddr, uint val) -{ - uint mdiodata; - uint i = 0; - sbpcieregs_t *pcieregs; - - pcieregs = (sbpcieregs_t *) sb_setcoreidx(&si->sb, si->sb.buscoreidx); - ASSERT(pcieregs); - - /* enable mdio access to SERDES */ - W_REG(si->osh, (&pcieregs->mdiocontrol), - MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL); - - mdiodata = MDIODATA_START | MDIODATA_WRITE | - (physmedia << MDIODATA_DEVADDR_SHF) | - (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val; - - W_REG(si->osh, (&pcieregs->mdiodata), mdiodata); - - PR28829_DELAY(); - - /* retry till the transaction is complete */ - while (i < 10) { - if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & - MDIOCTL_ACCESS_DONE) { - /* Disable mdio access to SERDES */ - W_REG(si->osh, (&pcieregs->mdiocontrol), 0); - return 0; - } - OSL_DELAY(1000); - i++; - } - - SB_ERROR(("sb_pcie_mdiowrite: timed out\n")); - /* Disable mdio access to SERDES */ - W_REG(si->osh, (&pcieregs->mdiocontrol), 0); - return 1; - -} - -/* indirect way to read pcie config regs */ -uint sb_pcie_readreg(void *sb, void *arg1, uint offset) -{ - sb_info_t *si; - sb_t *sbh; - uint retval = 0xFFFFFFFF; - sbpcieregs_t *pcieregs; - uint addrtype; - - sbh = (sb_t *) sb; - si = SB_INFO(sbh); - ASSERT(PCIE(si)); - - pcieregs = (sbpcieregs_t *) sb_setcore(sbh, SB_PCIE, 0); - ASSERT(pcieregs); - - addrtype = (uint) ((uintptr) arg1); - switch (addrtype) { - case PCIE_CONFIGREGS: - W_REG(si->osh, (&pcieregs->configaddr), offset); - retval = R_REG(si->osh, &(pcieregs->configdata)); - break; - case PCIE_PCIEREGS: - W_REG(si->osh, &(pcieregs->pcieindaddr), offset); - retval = R_REG(si->osh, &(pcieregs->pcieinddata)); - break; - default: - ASSERT(0); - break; - } - return retval; -} - -/* indirect way to write pcie config/mdio/pciecore regs */ -uint sb_pcie_writereg(sb_t * sbh, void *arg1, uint offset, uint val) -{ - sb_info_t *si; - sbpcieregs_t *pcieregs; - uint addrtype; - - si = SB_INFO(sbh); - ASSERT(PCIE(si)); - - pcieregs = (sbpcieregs_t *) sb_setcore(sbh, SB_PCIE, 0); - ASSERT(pcieregs); - - addrtype = (uint) ((uintptr) arg1); - - switch (addrtype) { - case PCIE_CONFIGREGS: - W_REG(si->osh, (&pcieregs->configaddr), offset); - W_REG(si->osh, (&pcieregs->configdata), val); - break; - case PCIE_PCIEREGS: - W_REG(si->osh, (&pcieregs->pcieindaddr), offset); - W_REG(si->osh, (&pcieregs->pcieinddata), val); - break; - default: - ASSERT(0); - break; - } - return 0; -} - -/* Build device path. Support SB, PCI, and JTAG for now. */ -int BCMINITFN(sb_devpath) (sb_t * sbh, char *path, int size) { - int slen; - ASSERT(path); - ASSERT(size >= SB_DEVPATH_BUFSZ); - - if (!path || size <= 0) - return -1; - - switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) { - case SB_BUS: - case JTAG_BUS: - slen = snprintf(path, (size_t) size, "sb/%u/", sb_coreidx(sbh)); - break; - case PCI_BUS: - ASSERT((SB_INFO(sbh))->osh); - slen = snprintf(path, (size_t) size, "pci/%u/%u/", - OSL_PCI_BUS((SB_INFO(sbh))->osh), - OSL_PCI_SLOT((SB_INFO(sbh))->osh)); - break; - case PCMCIA_BUS: - SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n")); - SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n")); - slen = snprintf(path, (size_t) size, "pc/1/1/"); - break; - default: - slen = -1; - ASSERT(0); - break; - } - - if (slen < 0 || slen >= size) { - path[0] = '\0'; - return -1; - } - - return 0; -} - -/* Get a variable, but only if it has a devpath prefix */ -char *BCMINITFN(sb_getdevpathvar) (sb_t * sbh, const char *name) { - char varname[SB_DEVPATH_BUFSZ + 32]; - - sb_devpathvar(sbh, varname, sizeof(varname), name); - - return (getvar(NULL, varname)); -} - -/* Get a variable, but only if it has a devpath prefix */ -int BCMINITFN(sb_getdevpathintvar) (sb_t * sbh, const char *name) { - char varname[SB_DEVPATH_BUFSZ + 32]; - - sb_devpathvar(sbh, varname, sizeof(varname), name); - - return (getintvar(NULL, varname)); -} - -/* Concatenate the dev path with a varname into the given 'var' buffer - * and return the 'var' pointer. - * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned. - * On overflow, the first char will be set to '\0'. - */ -static char *BCMINITFN(sb_devpathvar) (sb_t * sbh, char *var, int len, - const char *name) { - uint path_len; - - if (!var || len <= 0) - return var; - - if (sb_devpath(sbh, var, len) == 0) { - path_len = strlen(var); - - if (strlen(name) + 1 > (uint) (len - path_len)) - var[0] = '\0'; - else - strncpy(var + path_len, name, len - path_len - 1); - } - - return var; -} - -/* - * Fixup SROMless PCI device's configuration. - * The current core may be changed upon return. - */ -static int sb_pci_fixcfg(sb_info_t * si) -{ - uint origidx, pciidx; - sbpciregs_t *pciregs; - sbpcieregs_t *pcieregs = NULL; - uint16 val16, *reg16; - uint32 w; - - ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS); - - /* Fixup PI in SROM shadow area to enable the correct PCI core access */ - /* save the current index */ - origidx = sb_coreidx(&si->sb); - - /* check 'pi' is correct and fix it if not */ - if (si->sb.buscoretype == SB_PCIE) { - pcieregs = (sbpcieregs_t *) sb_setcore(&si->sb, SB_PCIE, 0); - ASSERT(pcieregs); - reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; - } else if (si->sb.buscoretype == SB_PCI) { - pciregs = (sbpciregs_t *) sb_setcore(&si->sb, SB_PCI, 0); - ASSERT(pciregs); - reg16 = &pciregs->sprom[SRSH_PI_OFFSET]; - } else { - ASSERT(0); - return -1; - } - pciidx = sb_coreidx(&si->sb); - val16 = R_REG(si->osh, reg16); - if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16) pciidx) { - val16 = - (uint16) (pciidx << SRSH_PI_SHIFT) | (val16 & - ~SRSH_PI_MASK); - W_REG(si->osh, reg16, val16); - } - - if (PCIE_ASPMWARS(si)) { - w = sb_pcie_readreg((void *)(uintptr) & si->sb, - (void *)PCIE_PCIEREGS, PCIE_PLP_STATUSREG); - - /* Detect the current polarity at attach and force that polarity and - * disable changing the polarity - */ - if ((w & PCIE_PLP_POLARITYINV_STAT) == 0) { - si->pcie_polarity = (SERDES_RX_CTRL_FORCE); - } else { - si->pcie_polarity = (SERDES_RX_CTRL_FORCE | - SERDES_RX_CTRL_POLARITY); - } - - w = OSL_PCI_READ_CONFIG(si->osh, si->pciecap_lcreg_offset, - sizeof(uint32)); - if (w & PCIE_CLKREQ_ENAB) { - reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET]; - val16 = R_REG(si->osh, reg16); - /* if clockreq is not advertized clkreq should not be enabled */ - if (!(val16 & SRSH_CLKREQ_ENB)) - SB_ERROR(("WARNING: CLK REQ enabled already 0x%x\n", w)); - } - - sb_war43448(&si->sb); - - sb_war42767(&si->sb); - - } - - /* restore the original index */ - sb_setcoreidx(&si->sb, origidx); - - return 0; -} - -/* Return ADDR64 capability of the backplane */ -bool sb_backplane64(sb_t * sbh) -{ - sb_info_t *si; - - si = SB_INFO(sbh); - return ((si->sb.cccaps & CC_CAP_BKPLN64) != 0); -} - -void sb_btcgpiowar(sb_t * sbh) -{ - sb_info_t *si; - uint origidx; - uint intr_val = 0; - chipcregs_t *cc; - si = SB_INFO(sbh); - - /* Make sure that there is ChipCommon core present && - * UART_TX is strapped to 1 - */ - if (!(si->sb.cccaps & CC_CAP_UARTGPIO)) - return; - - /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */ - INTR_OFF(si, intr_val); - - origidx = sb_coreidx(sbh); - - cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0); - ASSERT(cc); - - W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04); - - /* restore the original index */ - sb_setcoreidx(sbh, origidx); - - INTR_RESTORE(si, intr_val); -} - -/* check if the device is removed */ -bool sb_deviceremoved(sb_t * sbh) -{ - uint32 w; - sb_info_t *si; - - si = SB_INFO(sbh); - - switch (BUSTYPE(si->sb.bustype)) { - case PCI_BUS: - ASSERT(si->osh); - w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32)); - if ((w & 0xFFFF) != VENDOR_BROADCOM) - return TRUE; - else - return FALSE; - default: - return FALSE; - } - return FALSE; -} - -#if 0 -/* Return the RAM size of the SOCRAM core */ -uint32 BCMINITFN(sb_socram_size) (sb_t * sbh) { - sb_info_t *si; - uint origidx; - uint intr_val = 0; - - sbsocramregs_t *regs; - bool wasup; - uint corerev; - uint32 coreinfo; - uint memsize = 0; - - si = SB_INFO(sbh); - ASSERT(si); - - /* Block ints and save current core */ - INTR_OFF(si, intr_val); - origidx = sb_coreidx(sbh); - - /* Switch to SOCRAM core */ - if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0))) - goto done; - - /* Get info for determining size */ - if (!(wasup = sb_iscoreup(sbh))) - sb_core_reset(sbh, 0, 0); - corerev = sb_corerev(sbh); - coreinfo = R_REG(si->osh, ®s->coreinfo); - - /* Calculate size from coreinfo based on rev */ - if (corerev == 0) - memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK)); - else if (corerev < 3) { - memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK)); - memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; - } else { - uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; - uint bsz = (coreinfo & SRCI_SRBSZ_MASK); - uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT; - if (lss != 0) - nb--; - memsize = nb * (1 << (bsz + SR_BSZ_BASE)); - if (lss != 0) - memsize += (1 << ((lss - 1) + SR_BSZ_BASE)); - } - /* Return to previous state and core */ - if (!wasup) - sb_core_disable(sbh, 0); - sb_setcoreidx(sbh, origidx); - - done: - INTR_RESTORE(si, intr_val); - return memsize; -} - -#endif diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/setup.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/setup.c deleted file mode 100644 index 89e48236b0..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/setup.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Generic setup routines for Broadcom MIPS boards - * - * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - * Copyright 2005, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/serialP.h> -#include <linux/ide.h> -#include <asm/bootinfo.h> -#include <asm/cpu.h> -#include <asm/time.h> -#include <asm/reboot.h> - -#include <typedefs.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmnvram.h> -#include <bcmdevs.h> -#include <sbhndmips.h> -#include <hndmips.h> -#include <trxhdr.h> - -/* Virtual IRQ base, after last hw IRQ */ -#define SBMIPS_VIRTIRQ_BASE 6 - -/* # IRQs, hw and sw IRQs */ -#define SBMIPS_NUMIRQS 8 - -/* Global SB handle */ -sb_t *bcm947xx_sbh = NULL; -spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED; - -/* Convenience */ -#define sbh bcm947xx_sbh -#define sbh_lock bcm947xx_sbh_lock - -extern void bcm947xx_time_init(void); -extern void bcm947xx_timer_setup(struct irqaction *irq); - -#ifdef CONFIG_REMOTE_DEBUG -extern void set_debug_traps(void); -extern void rs_kgdb_hook(struct serial_state *); -extern void breakpoint(void); -#endif - -#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) -extern struct ide_ops std_ide_ops; -#endif - -/* Kernel command line */ -char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE; -extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift)); - -void -bcm947xx_machine_restart(char *command) -{ - printk("Please stand by while rebooting the system...\n"); - - if (sb_chip(sbh) == BCM4785_CHIP_ID) - MTC0(C0_BROADCOM, 4, (1 << 22)); - - /* Set the watchdog timer to reset immediately */ - __cli(); - sb_watchdog(sbh, 1); - - if (sb_chip(sbh) == BCM4785_CHIP_ID) { - __asm__ __volatile__( - ".set\tmips3\n\t" - "sync\n\t" - "wait\n\t" - ".set\tmips0"); - } - - while (1); -} - -void -bcm947xx_machine_halt(void) -{ - printk("System halted\n"); - - /* Disable interrupts and watchdog and spin forever */ - __cli(); - sb_watchdog(sbh, 0); - while (1); -} - -#ifdef CONFIG_SERIAL - -static int ser_line = 0; - -typedef struct { - void *regs; - uint irq; - uint baud_base; - uint reg_shift; -} serial_port; - -static serial_port ports[4]; -static int num_ports = 0; - -static void -serial_add(void *regs, uint irq, uint baud_base, uint reg_shift) -{ - ports[num_ports].regs = regs; - ports[num_ports].irq = irq; - ports[num_ports].baud_base = baud_base; - ports[num_ports].reg_shift = reg_shift; - num_ports++; -} - -static void -do_serial_add(serial_port *port) -{ - void *regs; - uint irq; - uint baud_base; - uint reg_shift; - struct serial_struct s; - - regs = port->regs; - irq = port->irq; - baud_base = port->baud_base; - reg_shift = port->reg_shift; - - memset(&s, 0, sizeof(s)); - - s.line = ser_line++; - s.iomem_base = regs; - s.irq = irq + 2; - s.baud_base = baud_base / 16; - s.flags = ASYNC_BOOT_AUTOCONF; - s.io_type = SERIAL_IO_MEM; - s.iomem_reg_shift = reg_shift; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } -} - -#endif /* CONFIG_SERIAL */ - -void __init -brcm_setup(void) -{ - char *s; - int i; - char *value; - - /* Get global SB handle */ - sbh = sb_kattach(SB_OSH); - - /* Initialize clocks and interrupts */ - sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE); - - if (BCM330X(current_cpu_data.processor_id) && - (read_c0_diag() & BRCM_PFC_AVAIL)) { - /* - * Now that the sbh is inited set the proper PFC value - */ - printk("Setting the PFC to its default value\n"); - enable_pfc(PFC_AUTO); - } - - -#ifdef CONFIG_SERIAL - sb_serial_init(sbh, serial_add); - - /* reverse serial ports if nvram variable starts with console=ttyS1 */ - /* Initialize UARTs */ - s = nvram_get("kernel_args"); - if (!s) s = ""; - if (!strncmp(s, "console=ttyS1", 13)) { - for (i = num_ports; i; i--) - do_serial_add(&ports[i - 1]); - } else { - for (i = 0; i < num_ports; i++) - do_serial_add(&ports[i]); - } -#endif - -#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) - ide_ops = &std_ide_ops; -#endif - - /* Override default command line arguments */ - value = nvram_get("kernel_cmdline"); - if (value && strlen(value) && strncmp(value, "empty", 5)) - strncpy(arcs_cmdline, value, sizeof(arcs_cmdline)); - - - /* Generic setup */ - _machine_restart = bcm947xx_machine_restart; - _machine_halt = bcm947xx_machine_halt; - _machine_power_off = bcm947xx_machine_halt; - - board_time_init = bcm947xx_time_init; - board_timer_setup = bcm947xx_timer_setup; -} - -const char * -get_system_type(void) -{ - static char s[32]; - - if (bcm947xx_sbh) { - sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh), - sb_chiprev(bcm947xx_sbh)); - return s; - } - else - return "Broadcom BCM947XX"; -} - -void __init -bus_error_init(void) -{ -} - diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sflash.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sflash.c deleted file mode 100644 index 9bfb8b42a2..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/sflash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Broadcom SiliconBackplane chipcommon serial flash interface - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - * $Id$ - */ - -#include <typedefs.h> -#include <osl.h> -#include "include/bcmutils.h" -#include <sbutils.h> -#include <sbconfig.h> -#include <sbchipc.h> -#include <bcmdevs.h> -#include <sflash.h> - -/* Private global state */ -static struct sflash sflash; - -/* Issue a serial flash command */ -static INLINE void -sflash_cmd(osl_t *osh, chipcregs_t *cc, uint opcode) -{ - W_REG(osh, &cc->flashcontrol, SFLASH_START | opcode); - while (R_REG(osh, &cc->flashcontrol) & SFLASH_BUSY); -} - -/* Initialize serial flash access */ -struct sflash * -sflash_init(sb_t *sbh, chipcregs_t *cc) -{ - uint32 id, id2; - osl_t *osh; - - ASSERT(sbh); - - osh = sb_osh(sbh); - - bzero(&sflash, sizeof(sflash)); - - sflash.type = sbh->cccaps & CC_CAP_FLASH_MASK; - - switch (sflash.type) { - case SFLASH_ST: - /* Probe for ST chips */ - sflash_cmd(osh, cc, SFLASH_ST_DP); - sflash_cmd(osh, cc, SFLASH_ST_RES); - id = R_REG(osh, &cc->flashdata); - switch (id) { - case 0x11: - /* ST M25P20 2 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 4; - break; - case 0x12: - /* ST M25P40 4 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 8; - break; - case 0x13: - /* ST M25P80 8 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 16; - break; - case 0x14: - /* ST M25P16 16 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 32; - break; - case 0x15: - /* ST M25P32 32 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 64; - break; - case 0x16: - /* ST M25P64 64 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 128; - break; - case 0xbf: - W_REG(osh, &cc->flashaddress, 1); - sflash_cmd(osh, cc, SFLASH_ST_RES); - id2 = R_REG(osh, &cc->flashdata); - if (id2 == 0x44) { - /* SST M25VF80 4 Mbit Serial Flash */ - sflash.blocksize = 64 * 1024; - sflash.numblocks = 8; - } - break; - } - break; - - case SFLASH_AT: - /* Probe for Atmel chips */ - sflash_cmd(osh, cc, SFLASH_AT_STATUS); - id = R_REG(osh, &cc->flashdata) & 0x3c; - switch (id) { - case 0xc: - /* Atmel AT45DB011 1Mbit Serial Flash */ - sflash.blocksize = 256; - sflash.numblocks = 512; - break; - case 0x14: - /* Atmel AT45DB021 2Mbit Serial Flash */ - sflash.blocksize = 256; - sflash.numblocks = 1024; - break; - case 0x1c: - /* Atmel AT45DB041 4Mbit Serial Flash */ - sflash.blocksize = 256; - sflash.numblocks = 2048; - break; - case 0x24: - /* Atmel AT45DB081 8Mbit Serial Flash */ - sflash.blocksize = 256; - sflash.numblocks = 4096; - break; - case 0x2c: - /* Atmel AT45DB161 16Mbit Serial Flash */ - sflash.blocksize = 512; - sflash.numblocks = 4096; - break; - case 0x34: - /* Atmel AT45DB321 32Mbit Serial Flash */ - sflash.blocksize = 512; - sflash.numblocks = 8192; - break; - case 0x3c: - /* Atmel AT45DB642 64Mbit Serial Flash */ - sflash.blocksize = 1024; - sflash.numblocks = 8192; - break; - } - break; - } - - sflash.size = sflash.blocksize * sflash.numblocks; - return sflash.size ? &sflash : NULL; -} - -/* Read len bytes starting at offset into buf. Returns number of bytes read. */ -int -sflash_read(sb_t *sbh, chipcregs_t *cc, uint offset, uint len, uchar *buf) -{ - uint8 *from, *to; - int cnt, i; - osl_t *osh; - - ASSERT(sbh); - - if (!len) - return 0; - - if ((offset + len) > sflash.size) - return -22; - - if ((len >= 4) && (offset & 3)) - cnt = 4 - (offset & 3); - else if ((len >= 4) && ((uintptr)buf & 3)) - cnt = 4 - ((uintptr)buf & 3); - else - cnt = len; - - osh = sb_osh(sbh); - - from = (uint8 *)(uintptr)OSL_UNCACHED(SB_FLASH2 + offset); - to = (uint8 *)buf; - - if (cnt < 4) { - for (i = 0; i < cnt; i ++) { - *to = R_REG(osh, from); - from ++; - to ++; - } - return cnt; - } - - while (cnt >= 4) { - *(uint32 *)to = R_REG(osh, (uint32 *)from); - from += 4; - to += 4; - cnt -= 4; - } - - return (len - cnt); -} - -/* Poll for command completion. Returns zero when complete. */ -int -sflash_poll(sb_t *sbh, chipcregs_t *cc, uint offset) -{ - osl_t *osh; - - ASSERT(sbh); - - osh = sb_osh(sbh); - - if (offset >= sflash.size) - return -22; - - switch (sflash.type) { - case SFLASH_ST: - /* Check for ST Write In Progress bit */ - sflash_cmd(osh, cc, SFLASH_ST_RDSR); - return R_REG(osh, &cc->flashdata) & SFLASH_ST_WIP; - case SFLASH_AT: - /* Check for Atmel Ready bit */ - sflash_cmd(osh, cc, SFLASH_AT_STATUS); - return !(R_REG(osh, &cc->flashdata) & SFLASH_AT_READY); - } - - return 0; -} - -/* Write len bytes starting at offset into buf. Returns number of bytes - * written. Caller should poll for completion. - */ -int -sflash_write(sb_t *sbh, chipcregs_t *cc, uint offset, uint len, const uchar *buf) -{ - struct sflash *sfl; - int ret = 0; - bool is4712b0; - uint32 page, byte, mask; - osl_t *osh; - - ASSERT(sbh); - - osh = sb_osh(sbh); - - if (!len) - return 0; - - if ((offset + len) > sflash.size) - return -22; - - sfl = &sflash; - switch (sfl->type) { - case SFLASH_ST: - is4712b0 = (sbh->chip == BCM4712_CHIP_ID) && (sbh->chiprev == 3); - /* Enable writes */ - sflash_cmd(osh, cc, SFLASH_ST_WREN); - if (is4712b0) { - mask = 1 << 14; - W_REG(osh, &cc->flashaddress, offset); - W_REG(osh, &cc->flashdata, *buf++); - /* Set chip select */ - OR_REG(osh, &cc->gpioout, mask); - /* Issue a page program with the first byte */ - sflash_cmd(osh, cc, SFLASH_ST_PP); - ret = 1; - offset++; - len--; - while (len > 0) { - if ((offset & 255) == 0) { - /* Page boundary, drop cs and return */ - AND_REG(osh, &cc->gpioout, ~mask); - if (!sflash_poll(sbh, cc, offset)) { - /* Flash rejected command */ - return -11; - } - return ret; - } else { - /* Write single byte */ - sflash_cmd(osh, cc, *buf++); - } - ret++; - offset++; - len--; - } - /* All done, drop cs if needed */ - if ((offset & 255) != 1) { - /* Drop cs */ - AND_REG(osh, &cc->gpioout, ~mask); - if (!sflash_poll(sbh, cc, offset)) { - /* Flash rejected command */ - return -12; - } - } - } else if ( (sbh->ccrev >= 20) && (len != 1) ) { - //} else if ( sbh->ccrev >= 20 ) { /* foxconn modified by EricHuang, 05/24/2007 */ - W_REG(NULL, &cc->flashaddress, offset); - W_REG(NULL, &cc->flashdata, *buf++); - /* Issue a page program with CSA bit set */ - sflash_cmd(osh, cc, SFLASH_ST_CSA | SFLASH_ST_PP); - ret = 1; - offset++; - len--; - while (len > 0) { - if ((offset & 255) == 0) { - /* Page boundary, poll droping cs and return */ - W_REG(NULL, &cc->flashcontrol, 0); - /* wklin added start, 06/08/2007 */ - W_REG(NULL, &cc->flashcontrol, 0); - OSL_DELAY(1); - /* wklin added end, 06/08/2007 */ - /* wklin rmeoved start, 06/08/2007 */ -#if 0 - if (!sflash_poll(sbh, cc, offset)) { - /* Flash rejected command */ - return -11; - } -#endif - /* wklin removed end, 06/08/2007 */ - return ret; - } else { - /* Write single byte */ - sflash_cmd(osh, cc, SFLASH_ST_CSA | *buf++); - } - ret++; - offset++; - len--; - } - /* All done, drop cs if needed */ - if ((offset & 255) != 1) { - /* Drop cs, poll */ - W_REG(NULL, &cc->flashcontrol, 0); - /* wklin added start, 06/08/2007 */ - W_REG(NULL, &cc->flashcontrol, 0); - OSL_DELAY(1); - /* wklin added end, 06/08/2007 */ - /* wklin removed start, 06/08/2007 */ -#if 0 - if (!sflash_poll(sbh, cc, offset)) { - /* Flash rejected command */ - return -12; - } -#endif - /* wklin removed end, 06/08/2007 */ - } - } else { - ret = 1; - W_REG(osh, &cc->flashaddress, offset); - W_REG(osh, &cc->flashdata, *buf); - /* Page program */ - sflash_cmd(osh, cc, SFLASH_ST_PP); - } - break; - case SFLASH_AT: - mask = sfl->blocksize - 1; - page = (offset & ~mask) << 1; - byte = offset & mask; - /* Read main memory page into buffer 1 */ - if (byte || (len < sfl->blocksize)) { - W_REG(osh, &cc->flashaddress, page); - sflash_cmd(osh, cc, SFLASH_AT_BUF1_LOAD); - /* 250 us for AT45DB321B */ - SPINWAIT(sflash_poll(sbh, cc, offset), 1000); - ASSERT(!sflash_poll(sbh, cc, offset)); - } - /* Write into buffer 1 */ - for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) { - W_REG(osh, &cc->flashaddress, byte++); - W_REG(osh, &cc->flashdata, *buf++); - sflash_cmd(osh, cc, SFLASH_AT_BUF1_WRITE); - } - /* Write buffer 1 into main memory page */ - W_REG(osh, &cc->flashaddress, page); - sflash_cmd(osh, cc, SFLASH_AT_BUF1_PROGRAM); - break; - } - - return ret; -} - -/* Erase a region. Returns number of bytes scheduled for erasure. - * Caller should poll for completion. - */ -int -sflash_erase(sb_t *sbh, chipcregs_t *cc, uint offset) -{ - struct sflash *sfl; - osl_t *osh; - - ASSERT(sbh); - - osh = sb_osh(sbh); - - if (offset >= sflash.size) - return -22; - - sfl = &sflash; - switch (sfl->type) { - case SFLASH_ST: - sflash_cmd(osh, cc, SFLASH_ST_WREN); - W_REG(osh, &cc->flashaddress, offset); - sflash_cmd(osh, cc, SFLASH_ST_SE); - return sfl->blocksize; - case SFLASH_AT: - W_REG(osh, &cc->flashaddress, offset << 1); - sflash_cmd(osh, cc, SFLASH_AT_PAGE_ERASE); - return sfl->blocksize; - } - - return 0; -} - -/* - * writes the appropriate range of flash, a NULL buf simply erases - * the region of flash - */ -int -sflash_commit(sb_t *sbh, chipcregs_t *cc, uint offset, uint len, const uchar *buf) -{ - struct sflash *sfl; - uchar *block = NULL, *cur_ptr, *blk_ptr; - uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder; - uint blk_offset, blk_len, copied; - int bytes, ret = 0; - osl_t *osh; - - ASSERT(sbh); - - osh = sb_osh(sbh); - - /* Check address range */ - if (len <= 0) - return 0; - - sfl = &sflash; - if ((offset + len) > sfl->size) - return -1; - - blocksize = sfl->blocksize; - mask = blocksize - 1; - - /* Allocate a block of mem */ - if (!(block = MALLOC(osh, blocksize))) - return -1; - - while (len) { - /* Align offset */ - cur_offset = offset & ~mask; - cur_length = blocksize; - cur_ptr = block; - - remainder = blocksize - (offset & mask); - if (len < remainder) - cur_retlen = len; - else - cur_retlen = remainder; - - /* buf == NULL means erase only */ - if (buf) { - /* Copy existing data into holding block if necessary */ - if ((offset & mask) || (len < blocksize)) { - blk_offset = cur_offset; - blk_len = cur_length; - blk_ptr = cur_ptr; - - /* Copy entire block */ - while (blk_len) { - copied = sflash_read(sbh, cc, blk_offset, blk_len, blk_ptr); - blk_offset += copied; - blk_len -= copied; - blk_ptr += copied; - } - } - - /* Copy input data into holding block */ - memcpy(cur_ptr + (offset & mask), buf, cur_retlen); - } - - /* Erase block */ - if ((ret = sflash_erase(sbh, cc, (uint) cur_offset)) < 0) - goto done; - while (sflash_poll(sbh, cc, (uint) cur_offset)); - - /* buf == NULL means erase only */ - if (!buf) { - offset += cur_retlen; - len -= cur_retlen; - continue; - } - - /* Write holding block */ - while (cur_length > 0) { - if ((bytes = sflash_write(sbh, cc, - (uint) cur_offset, - (uint) cur_length, - (uchar *) cur_ptr)) < 0) { - ret = bytes; - goto done; - } - while (sflash_poll(sbh, cc, (uint) cur_offset)); - cur_offset += bytes; - cur_length -= bytes; - cur_ptr += bytes; - } - - offset += cur_retlen; - len -= cur_retlen; - buf += cur_retlen; - } - - ret = len; -done: - if (block) - MFREE(osh, block, blocksize); - return ret; -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/time.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/time.c deleted file mode 100644 index 95df5a6b25..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/time.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2006, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - * - */ -#include <linux/config.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/serial_reg.h> -#include <linux/interrupt.h> -#include <asm/addrspace.h> -#include <asm/io.h> -#include <asm/time.h> - -#include <typedefs.h> -#include <osl.h> -#include <bcmnvram.h> -#include <sbconfig.h> -#include <sbutils.h> -#include <sbchipc.h> -#include <hndmips.h> -#include <mipsinc.h> -#include <hndcpu.h> -#include <bcmdevs.h> - -/* Global SB handle */ -extern void *bcm947xx_sbh; -extern spinlock_t bcm947xx_sbh_lock; - -/* Convenience */ -#define sbh bcm947xx_sbh -#define sbh_lock bcm947xx_sbh_lock - -extern int panic_timeout; -static int watchdog = 0; - -void __init -bcm947xx_time_init(void) -{ - unsigned int hz; - - /* - * Use deterministic values for initial counter interrupt - * so that calibrate delay avoids encountering a counter wrap. - */ - write_c0_count(0); - write_c0_compare(0xffff); - - if (!(hz = sb_cpu_clock(sbh))) - hz = 100000000; - - printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh), - (hz + 500000) / 1000000); - - /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */ - mips_hpt_frequency = hz / 2; - - /* Set watchdog interval in ms */ - watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0); - - /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */ - if (watchdog > 0) { - if (watchdog < 3000) - watchdog = 3000; - } - - /* Set panic timeout in seconds */ - panic_timeout = watchdog / 1000; -} - -static void -bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Generic MIPS timer code */ - timer_interrupt(irq, dev_id, regs); - - /* Set the watchdog timer to reset after the specified number of ms */ - if (watchdog > 0) { - if (sb_chip(sbh) == BCM5354_CHIP_ID) - sb_watchdog(sbh, WATCHDOG_CLOCK_5354 / 1000 * watchdog); - else - sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog); - } - -} - -static struct irqaction bcm947xx_timer_irqaction = { - bcm947xx_timer_interrupt, - SA_INTERRUPT, - 0, - "timer", - NULL, - NULL -}; - -void __init -bcm947xx_timer_setup(struct irqaction *irq) -{ - int x; - - /* Enable the timer interrupt */ - setup_irq(7, &bcm947xx_timer_irqaction); - - sti(); - - for (x=0; x<5; x++) { - unsigned long ticks; - ticks = jiffies; - while (ticks == jiffies) - /* do nothing */; - } -} diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.c deleted file mode 100644 index fcb9341a15..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Driver O/S-independent utility routines - * - * Copyright 2007, Broadcom Corporation - * All Rights Reserved. - * - * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY - * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM - * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. - */ - -#include <typedefs.h> -#include <bcmdefs.h> -#include <stdarg.h> -#include <osl.h> -#include <sbutils.h> -#include <bcmendian.h> -#include "utils.h" - -/******************************************************************************* - * crc8 - * - * Computes a crc8 over the input data using the polynomial: - * - * x^8 + x^7 +x^6 + x^4 + x^2 + 1 - * - * The caller provides the initial value (either CRC8_INIT_VALUE - * or the previous returned value) to allow for processing of - * discontiguous blocks of data. When generating the CRC the - * caller is responsible for complementing the final return value - * and inserting it into the byte stream. When checking, a final - * return value of CRC8_GOOD_VALUE indicates a valid CRC. - * - * Reference: Dallas Semiconductor Application Note 27 - * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms", - * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd., - * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt - * - * **************************************************************************** - */ - -static const uint8 crc8_table[256] = { - 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B, - 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21, - 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF, - 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5, - 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14, - 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E, - 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80, - 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA, - 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95, - 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF, - 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01, - 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B, - 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA, - 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0, - 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E, - 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34, - 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0, - 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A, - 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54, - 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E, - 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF, - 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5, - 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B, - 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61, - 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E, - 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74, - 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA, - 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0, - 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41, - 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B, - 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5, - 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F -}; - -#define CRC_INNER_LOOP(n, c, x) \ - (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff] - - -uint8 hndcrc8 (uint8 * pdata, /* pointer to array of data to process */ - uint nbytes, /* number of input data bytes to process */ - uint8 crc /* either CRC8_INIT_VALUE or previous return value */ - ) -{ - /* hard code the crc loop instead of using CRC_INNER_LOOP macro - * to avoid the undefined and unnecessary (uint8 >> 8) operation. - */ - while (nbytes-- > 0) - crc = crc8_table[(crc ^ *pdata++) & 0xff]; - - return crc; -} - -char * -bcm_ether_ntoa (struct ether_addr *ea, char *buf) -{ - snprintf (buf, 18, "%02x:%02x:%02x:%02x:%02x:%02x", - ea->octet[0] & 0xff, ea->octet[1] & 0xff, ea->octet[2] & 0xff, - ea->octet[3] & 0xff, ea->octet[4] & 0xff, ea->octet[5] & 0xff); - return (buf); -} - diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.h deleted file mode 100644 index 907c82c70d..0000000000 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/utils.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __bcm_utils_h -#define __bcm_utils_h - -#define BCME_STRLEN 64 /* Max string length for BCM errors */ -#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST)) - -/* - * error codes could be added but the defined ones shouldn't be changed/deleted - * these error codes are exposed to the user code - * when ever a new error code is added to this list - * please update errorstring table with the related error string and - * update osl files with os specific errorcode map -*/ - -#define BCME_OK 0 /* Success */ -#define BCME_ERROR -1 /* Error generic */ -#define BCME_BADARG -2 /* Bad Argument */ -#define BCME_BADOPTION -3 /* Bad option */ -#define BCME_NOTUP -4 /* Not up */ -#define BCME_NOTDOWN -5 /* Not down */ -#define BCME_NOTAP -6 /* Not AP */ -#define BCME_NOTSTA -7 /* Not STA */ -#define BCME_BADKEYIDX -8 /* BAD Key Index */ -#define BCME_RADIOOFF -9 /* Radio Off */ -#define BCME_NOTBANDLOCKED -10 /* Not band locked */ -#define BCME_NOCLK -11 /* No Clock */ -#define BCME_BADRATESET -12 /* BAD Rate valueset */ -#define BCME_BADBAND -13 /* BAD Band */ -#define BCME_BUFTOOSHORT -14 /* Buffer too short */ -#define BCME_BUFTOOLONG -15 /* Buffer too long */ -#define BCME_BUSY -16 /* Busy */ -#define BCME_NOTASSOCIATED -17 /* Not Associated */ -#define BCME_BADSSIDLEN -18 /* Bad SSID len */ -#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */ -#define BCME_BADCHAN -20 /* Bad Channel */ -#define BCME_BADADDR -21 /* Bad Address */ -#define BCME_NORESOURCE -22 /* Not Enough Resources */ -#define BCME_UNSUPPORTED -23 /* Unsupported */ -#define BCME_BADLEN -24 /* Bad length */ -#define BCME_NOTREADY -25 /* Not Ready */ -#define BCME_EPERM -26 /* Not Permitted */ -#define BCME_NOMEM -27 /* No Memory */ -#define BCME_ASSOCIATED -28 /* Associated */ -#define BCME_RANGE -29 /* Not In Range */ -#define BCME_NOTFOUND -30 /* Not Found */ -#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */ -#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */ -#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */ -#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */ -#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */ -#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */ -#define BCME_VERSION -37 /* Incorrect version */ -#define BCME_LAST BCME_VERSION - -/* buffer length for ethernet address from bcm_ether_ntoa() */ -#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */ - -struct ether_addr { - unsigned char octet[6]; -}; - -extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc); - -#endif /* __bcm_utils_h */ - |