diff options
Diffstat (limited to 'target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h')
| -rw-r--r-- | target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h | 51 |
1 files changed, 36 insertions, 15 deletions
diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h index 7a44e5fbaa..f609f3c2eb 100644 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h +++ b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h @@ -1,7 +1,7 @@ /* * Broadcom SiliconBackplane hardware register definitions. * - * Copyright 2006, Broadcom Corporation + * Copyright 2007, Broadcom Corporation * All Rights Reserved. * * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY @@ -9,11 +9,12 @@ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. * - * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $ + * $Id$ */ #ifndef _SBCONFIG_H #define _SBCONFIG_H +#include "linuxver.h" /* cpp contortions to concatenate w/arg prescan */ #ifndef PAD @@ -36,13 +37,13 @@ #define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ #define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ - #define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */ +#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ #define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ #define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ - -#define SB_ROM 0x20000000 /* ARM ROM */ -#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */ +#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ +#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ +#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ #define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ #define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ @@ -196,7 +197,7 @@ typedef volatile struct _sbconfig { #define SBTMH_INT 0x2 /* interrupt */ #define SBTMH_BUSY 0x4 /* busy */ #define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */ -#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */ +#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */ #define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */ #define SBTMH_GCR 0x20000000 /* gated clock request */ #define SBTMH_BISTF 0x40000000 /* bist failed */ @@ -323,7 +324,6 @@ typedef volatile struct _sbconfig { #define SB_ILINE100 0x80a /* iline100 core */ #define SB_IPSEC 0x80b /* ipsec core */ #define SB_PCMCIA 0x80d /* pcmcia core */ -#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */ #define SB_SOCRAM 0x80e /* internal memory core */ #define SB_MEMC 0x80f /* memc sdram core */ #define SB_EXTIF 0x811 /* external interface core */ @@ -342,11 +342,32 @@ typedef volatile struct _sbconfig { #define SB_MIMO 0x821 /* MIMO phy core */ #define SB_SRAMC 0x822 /* SRAM controller core */ #define SB_MINIMAC 0x823 /* MINI MAC/phy core */ -#define SB_ARM11 0x824 /* ARM 1176 core */ -#define SB_ARM7 0x825 /* ARM 7tdmi core */ +#define SB_ARM7S 0x825 /* ARM7tdmi-s core */ +#define SB_SDIOD 0x829 /* SDIO device core */ +#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */ +#define SB_OCP 0x830 /* OCP2OCP bridge core */ +#define SB_SC 0x831 /* shared common core */ +#define SB_AHB 0x832 /* OCP2AHB bridge core */ #define SB_CC_IDX 0 /* chipc, when present, is always core 0 */ +/* Not an enumeration space register, but common to all cores to + * communicate w/PMU regarding Silicon Backplane clocking. + */ +#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */ + +/* clk_ctl_st register */ +#define CCS_FORCEALP 0x00000001 /* force ALP request */ +#define CCS_FORCEHT 0x00000002 /* force HT request */ +#define CCS_FORCEILP 0x00000004 /* force ILP request */ +#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ +#define CCS_HTAREQ 0x00000010 /* HT Avail Request */ +#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ +#define CCS_ALPAVAIL 0x00010000 /* ALP is available */ +#define CCS_HTAVAIL 0x00020000 /* HT is available */ +#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ +#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ + /* Not really related to Silicon Backplane, but a couple of software * conventions for the use the flash space: */ @@ -359,11 +380,11 @@ typedef volatile struct _sbconfig { #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ #define BISZ_TXTST_IDX 1 /* 1: text start */ -#define BISZ_TXTEND_IDX 2 /* 2: text start */ -#define BISZ_DATAST_IDX 3 /* 3: text start */ -#define BISZ_DATAEND_IDX 4 /* 4: text start */ -#define BISZ_BSSST_IDX 5 /* 5: text start */ -#define BISZ_BSSEND_IDX 6 /* 6: text start */ +#define BISZ_TXTEND_IDX 2 /* 2: text end */ +#define BISZ_DATAST_IDX 3 /* 3: data start */ +#define BISZ_DATAEND_IDX 4 /* 4: data end */ +#define BISZ_BSSST_IDX 5 /* 5: bss start */ +#define BISZ_BSSEND_IDX 6 /* 6: bss end */ #define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */ #endif /* _SBCONFIG_H */ |