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diff --git a/target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch b/target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch
new file mode 100644
index 0000000000..db0952211e
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+++ b/target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch
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+From 7ca989eafbd6ce1c216a775556c4893baab1959b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Wed, 24 Mar 2021 09:19:13 +0100
+Subject: [PATCH 12/22] dt-bindings: add BCM6362 GPIO sysctl binding
+ documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add binding documentation for the GPIO sysctl found in BCM6362 SoCs.
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20210324081923.20379-13-noltari@gmail.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ .../mfd/brcm,bcm6362-gpio-sysctl.yaml | 236 ++++++++++++++++++
+ 1 file changed, 236 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
+@@ -0,0 +1,236 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings
++
++maintainers:
++ - Álvaro Fernández Rojas <noltari@gmail.com>
++ - Jonas Gorski <jonas.gorski@gmail.com>
++
++description:
++ Broadcom BCM6362 SoC GPIO system controller which provides a register map
++ for controlling the GPIO and pins of the SoC.
++
++properties:
++ "#address-cells": true
++
++ "#size-cells": true
++
++ compatible:
++ items:
++ - const: brcm,bcm6362-gpio-sysctl
++ - const: syscon
++ - const: simple-mfd
++
++ ranges:
++ maxItems: 1
++
++ reg:
++ maxItems: 1
++
++patternProperties:
++ "^gpio@[0-9a-f]+$":
++ # Child node
++ type: object
++ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
++ description:
++ GPIO controller for the SoC GPIOs. This child node definition
++ should follow the bindings specified in
++ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
++
++ "^pinctrl@[0-9a-f]+$":
++ # Child node
++ type: object
++ $ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml"
++ description:
++ Pin controller for the SoC pins. This child node definition
++ should follow the bindings specified in
++ Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.
++
++required:
++ - "#address-cells"
++ - compatible
++ - ranges
++ - reg
++ - "#size-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ syscon@10000080 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd";
++ reg = <0x10000080 0x80>;
++ ranges = <0 0x10000080 0x80>;
++
++ gpio@0 {
++ compatible = "brcm,bcm6362-gpio";
++ reg-names = "dirout", "dat";
++ reg = <0x0 0x8>, <0x8 0x8>;
++
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 0 48>;
++ #gpio-cells = <2>;
++ };
++
++ pinctrl: pinctrl@18 {
++ compatible = "brcm,bcm6362-pinctrl";
++ reg = <0x18 0x10>, <0x38 0x4>;
++
++ pinctrl_usb_device_led: usb_device_led-pins {
++ function = "usb_device_led";
++ pins = "gpio0";
++ };
++
++ pinctrl_sys_irq: sys_irq-pins {
++ function = "sys_irq";
++ pins = "gpio1";
++ };
++
++ pinctrl_serial_led: serial_led-pins {
++ pinctrl_serial_led_clk: serial_led_clk-pins {
++ function = "serial_led_clk";
++ pins = "gpio2";
++ };
++
++ pinctrl_serial_led_data: serial_led_data-pins {
++ function = "serial_led_data";
++ pins = "gpio3";
++ };
++ };
++
++ pinctrl_robosw_led_data: robosw_led_data-pins {
++ function = "robosw_led_data";
++ pins = "gpio4";
++ };
++
++ pinctrl_robosw_led_clk: robosw_led_clk-pins {
++ function = "robosw_led_clk";
++ pins = "gpio5";
++ };
++
++ pinctrl_robosw_led0: robosw_led0-pins {
++ function = "robosw_led0";
++ pins = "gpio6";
++ };
++
++ pinctrl_robosw_led1: robosw_led1-pins {
++ function = "robosw_led1";
++ pins = "gpio7";
++ };
++
++ pinctrl_inet_led: inet_led-pins {
++ function = "inet_led";
++ pins = "gpio8";
++ };
++
++ pinctrl_spi_cs2: spi_cs2-pins {
++ function = "spi_cs2";
++ pins = "gpio9";
++ };
++
++ pinctrl_spi_cs3: spi_cs3-pins {
++ function = "spi_cs3";
++ pins = "gpio10";
++ };
++
++ pinctrl_ntr_pulse: ntr_pulse-pins {
++ function = "ntr_pulse";
++ pins = "gpio11";
++ };
++
++ pinctrl_uart1_scts: uart1_scts-pins {
++ function = "uart1_scts";
++ pins = "gpio12";
++ };
++
++ pinctrl_uart1_srts: uart1_srts-pins {
++ function = "uart1_srts";
++ pins = "gpio13";
++ };
++
++ pinctrl_uart1: uart1-pins {
++ pinctrl_uart1_sdin: uart1_sdin-pins {
++ function = "uart1_sdin";
++ pins = "gpio14";
++ };
++
++ pinctrl_uart1_sdout: uart1_sdout-pins {
++ function = "uart1_sdout";
++ pins = "gpio15";
++ };
++ };
++
++ pinctrl_adsl_spi: adsl_spi-pins {
++ pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
++ function = "adsl_spi_miso";
++ pins = "gpio16";
++ };
++
++ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
++ function = "adsl_spi_mosi";
++ pins = "gpio17";
++ };
++
++ pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
++ function = "adsl_spi_clk";
++ pins = "gpio18";
++ };
++
++ pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
++ function = "adsl_spi_cs";
++ pins = "gpio19";
++ };
++ };
++
++ pinctrl_ephy0_led: ephy0_led-pins {
++ function = "ephy0_led";
++ pins = "gpio20";
++ };
++
++ pinctrl_ephy1_led: ephy1_led-pins {
++ function = "ephy1_led";
++ pins = "gpio21";
++ };
++
++ pinctrl_ephy2_led: ephy2_led-pins {
++ function = "ephy2_led";
++ pins = "gpio22";
++ };
++
++ pinctrl_ephy3_led: ephy3_led-pins {
++ function = "ephy3_led";
++ pins = "gpio23";
++ };
++
++ pinctrl_ext_irq0: ext_irq0-pins {
++ function = "ext_irq0";
++ pins = "gpio24";
++ };
++
++ pinctrl_ext_irq1: ext_irq1-pins {
++ function = "ext_irq1";
++ pins = "gpio25";
++ };
++
++ pinctrl_ext_irq2: ext_irq2-pins {
++ function = "ext_irq2";
++ pins = "gpio26";
++ };
++
++ pinctrl_ext_irq3: ext_irq3-pins {
++ function = "ext_irq3";
++ pins = "gpio27";
++ };
++
++ pinctrl_nand: nand-pins {
++ function = "nand";
++ group = "nand_grp";
++ };
++ };
++ };
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 22:18:51 +0000