diff options
Diffstat (limited to 'target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch')
| -rw-r--r-- | target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch b/target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch new file mode 100644 index 0000000000..b508190b91 --- /dev/null +++ b/target/linux/bmips/patches-5.10/008-v5.12-mips-bmips-dts-add-BCM63268-reset-controller-support.patch @@ -0,0 +1,64 @@ +From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> +Date: Wed, 17 Jun 2020 12:50:40 +0200 +Subject: [PATCH 8/9] mips: bmips: dts: add BCM63268 reset controller support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM63268 SoCs have a reset controller for certain components. + +Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> +Acked-by: Florian Fainelli <f.fainelli@gmail.com> +Reviewed-by: Rob Herring <robh@kernel.org> +Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> +--- + arch/mips/boot/dts/brcm/bcm63268.dtsi | 6 +++++ + include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++ + 2 files changed, 32 insertions(+) + create mode 100644 include/dt-bindings/reset/bcm63268-reset.h + +--- a/arch/mips/boot/dts/brcm/bcm63268.dtsi ++++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi +@@ -70,6 +70,12 @@ + mask = <0x1>; + }; + ++ periph_rst: reset-controller@10000010 { ++ compatible = "brcm,bcm6345-reset"; ++ reg = <0x10000010 0x4>; ++ #reset-cells = <1>; ++ }; ++ + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x20>, +--- /dev/null ++++ b/include/dt-bindings/reset/bcm63268-reset.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __DT_BINDINGS_RESET_BCM63268_H ++#define __DT_BINDINGS_RESET_BCM63268_H ++ ++#define BCM63268_RST_SPI 0 ++#define BCM63268_RST_IPSEC 1 ++#define BCM63268_RST_EPHY 2 ++#define BCM63268_RST_SAR 3 ++#define BCM63268_RST_ENETSW 4 ++#define BCM63268_RST_USBS 5 ++#define BCM63268_RST_USBH 6 ++#define BCM63268_RST_PCM 7 ++#define BCM63268_RST_PCIE_CORE 8 ++#define BCM63268_RST_PCIE 9 ++#define BCM63268_RST_PCIE_EXT 10 ++#define BCM63268_RST_WLAN_SHIM 11 ++#define BCM63268_RST_DDR_PHY 12 ++#define BCM63268_RST_FAP0 13 ++#define BCM63268_RST_WLAN_UBUS 14 ++#define BCM63268_RST_DECT 15 ++#define BCM63268_RST_FAP1 16 ++#define BCM63268_RST_PCIE_HARD 17 ++#define BCM63268_RST_GPHY 18 ++ ++#endif /* __DT_BINDINGS_RESET_BCM63268_H */ |