diff options
Diffstat (limited to 'target/linux/bmips/dts/bcm6328.dtsi')
| -rw-r--r-- | target/linux/bmips/dts/bcm6328.dtsi | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/target/linux/bmips/dts/bcm6328.dtsi b/target/linux/bmips/dts/bcm6328.dtsi index aa90cc2a9b..64fd04142c 100644 --- a/target/linux/bmips/dts/bcm6328.dtsi +++ b/target/linux/bmips/dts/bcm6328.dtsi @@ -368,5 +368,99 @@ status = "disabled"; }; + + ethernet: ethernet@1000d800 { + compatible = "brcm,bcm6328-enetsw"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + + interrupt-parent = <&periph_intc>; + interrupts = <BCM6328_IRQ_ENETSW_RX_DMA0>, + <BCM6328_IRQ_ENETSW_TX_DMA0>; + interrupt-names = "rx", + "tx"; + + clocks = <&periph_clk BCM6328_CLK_ROBOSW>; + + resets = <&periph_rst BCM6328_RST_ENETSW>, + <&periph_rst BCM6328_RST_EPHY>; + + power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_ROBOSW>, + <&periph_pwr BCM6328_POWER_DOMAIN_EPHY>; + + dma-rx = <0>; + dma-tx = <1>; + + status = "disabled"; + }; + + switch0: switch@10e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-switch"; + reg = <0x10e00000 0x8000>; + big-endian; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + label = "cpu"; + + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@10e000b0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6368-mdio-mux"; + reg = <0x10e000b0 0x8>; + + mdio_int: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + mdio_ext: mdio@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; }; |