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Diffstat (limited to 'target/linux/bcm53xx/patches-4.1/040-0003-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch')
-rw-r--r--target/linux/bcm53xx/patches-4.1/040-0003-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch68
1 files changed, 0 insertions, 68 deletions
diff --git a/target/linux/bcm53xx/patches-4.1/040-0003-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch b/target/linux/bcm53xx/patches-4.1/040-0003-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch
deleted file mode 100644
index b02b121cb0..0000000000
--- a/target/linux/bcm53xx/patches-4.1/040-0003-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From c7bd48195377435ecaf38869b936be8e7abe3489 Mon Sep 17 00:00:00 2001
-From: Ray Jui <rjui@broadcom.com>
-Date: Fri, 4 Dec 2015 09:35:00 -0800
-Subject: [PATCH 3/5] PCI: iproc: Add iProc PCIe MSI device tree binding
-
-Update the iProc PCIe device tree bindings with added binding information
-for MSI.
-
-Signed-off-by: Ray Jui <rjui@broadcom.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Anup Patel <anup.patel@broadcom.com>
-Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
-Reviewed-by: Scott Branden <sbranden@broadcom.com>
----
- .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 35 ++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
-+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
-@@ -35,6 +35,28 @@ Optional:
- - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
- increase the outbound window size
-
-+MSI support (optional):
-+
-+For older platforms without MSI integrated in the GIC, iProc PCIe core provides
-+an event queue based MSI support. The iProc MSI uses host memories to store
-+MSI posted writes in the event queues
-+
-+- msi-parent: Link to the device node of the MSI controller. On newer iProc
-+platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
-+platforms without MSI support in its interrupt controller, one may use the
-+event queue based MSI support integrated within the iProc PCIe core.
-+
-+When the iProc event queue based MSI is used, one needs to define the
-+following properties in the MSI device node:
-+- compatible: Must be "brcm,iproc-msi"
-+- msi-controller: claims itself as an MSI controller
-+- interrupt-parent: Link to its parent interrupt device
-+- interrupts: List of interrupt IDs from its parent interrupt device
-+
-+Optional properties:
-+- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
-+require the interrupt enable registers to be set explicitly to enable MSI
-+
- Example:
- pcie0: pcie@18012000 {
- compatible = "brcm,iproc-pcie";
-@@ -61,6 +83,19 @@ Example:
- brcm,pcie-ob-oarr-size;
- brcm,pcie-ob-axi-offset = <0x00000000>;
- brcm,pcie-ob-window-size = <256>;
-+
-+ msi-parent = <&msi0>;
-+
-+ /* iProc event queue based MSI */
-+ msi0: msi@18012000 {
-+ compatible = "brcm,iproc-msi";
-+ msi-controller;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
-+ <GIC_SPI 97 IRQ_TYPE_NONE>,
-+ <GIC_SPI 98 IRQ_TYPE_NONE>,
-+ <GIC_SPI 99 IRQ_TYPE_NONE>,
-+ };
- };
-
- pcie1: pcie@18013000 {