diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0554-drm-vc4-crtc-Enable-and-disable-the-PV-in-atomic_ena.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.4/950-0554-drm-vc4-crtc-Enable-and-disable-the-PV-in-atomic_ena.patch | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0554-drm-vc4-crtc-Enable-and-disable-the-PV-in-atomic_ena.patch b/target/linux/bcm27xx/patches-5.4/950-0554-drm-vc4-crtc-Enable-and-disable-the-PV-in-atomic_ena.patch deleted file mode 100644 index c5f06f20ea..0000000000 --- a/target/linux/bcm27xx/patches-5.4/950-0554-drm-vc4-crtc-Enable-and-disable-the-PV-in-atomic_ena.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 7bbbfef1c98e832cbd55e66ac2d7f13ec0a2b11e Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <maxime@cerno.tech> -Date: Fri, 21 Feb 2020 14:34:31 +0100 -Subject: [PATCH] drm/vc4: crtc: Enable and disable the PV in - atomic_enable / disable - -The VIDEN bit in the pixelvalve currently being used to enable or disable -the pixelvalve seems to not be enough in some situations, which whill end -up with the pixelvalve stalling. - -In such a case, even re-enabling VIDEN doesn't bring it back and we need to -clear the FIFO. This can only be done if the pixelvalve is disabled though. - -In order to overcome this, we can configure the pixelvalve during -mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO -there, and in atomic_disable disable the pixelvalve again. - -Signed-off-by: Maxime Ripard <maxime@cerno.tech> ---- - drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/gpu/drm/vc4/vc4_crtc.c -+++ b/drivers/gpu/drm/vc4/vc4_crtc.c -@@ -374,9 +374,7 @@ static void vc4_crtc_config_pv(struct dr - PV_CONTROL_TRIGGER_UNDERFLOW | - PV_CONTROL_WAIT_HSTART | - VC4_SET_FIELD(vc4_encoder->clock_select, -- PV_CONTROL_CLK_SELECT) | -- PV_CONTROL_FIFO_CLR | -- PV_CONTROL_EN); -+ PV_CONTROL_CLK_SELECT)); - } - - static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) -@@ -467,6 +465,8 @@ static void vc4_crtc_atomic_disable(stru - ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); - WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); - -+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); -+ - if (HVS_READ(SCALER_DISPCTRLX(chan)) & - SCALER_DISPCTRLX_ENABLE) { - HVS_WRITE(SCALER_DISPCTRLX(chan), -@@ -554,6 +554,10 @@ static void vc4_crtc_atomic_enable(struc - - require_hvs_enabled(dev); - -+ /* Reset the PV fifo. */ -+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | -+ PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); -+ - /* Enable vblank irq handling before crtc is started otherwise - * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). - */ |