1 files changed, 0 insertions, 86 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0548-drm-vc4-crtc-Deal-with-different-number-of-pixel-per.patch b/target/linux/bcm27xx/patches-5.4/950-0548-drm-vc4-crtc-Deal-with-different-number-of-pixel-per.patch
deleted file mode 100644
index 5949e616f9..0000000000
--- a/target/linux/bcm27xx/patches-5.4/950-0548-drm-vc4-crtc-Deal-with-different-number-of-pixel-per.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From b8714036be64c86a274ea49ba0066af0a81c6b98 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime@cerno.tech>
-Date: Thu, 26 Dec 2019 11:36:50 +0100
-Subject: [PATCH] drm/vc4: crtc: Deal with different number of pixel
- per clock
-
-Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle.
-Let's put the number of pixel output per clock cycle in the CRTC data and
-update the various calculations to reflect that.
-
-Signed-off-by: Maxime Ripard <maxime@cerno.tech>
----
- drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++++++++++-------
- drivers/gpu/drm/vc4/vc4_drv.h  |  3 +++
- 2 files changed, 13 insertions(+), 7 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -281,6 +281,7 @@ static void vc4_crtc_config_pv(struct dr
- 	bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
- 		       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
- 	u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
-+	u8 ppc = vc4_crtc->data->pixels_per_clock;
- 
- 	/* Reset the PV fifo. */
- 	CRTC_WRITE(PV_CONTROL, 0);
-@@ -288,17 +289,16 @@ static void vc4_crtc_config_pv(struct dr
- 	CRTC_WRITE(PV_CONTROL, 0);
- 
- 	CRTC_WRITE(PV_HORZA,
--		   VC4_SET_FIELD((mode->htotal -
--				  mode->hsync_end) * pixel_rep,
-+		   VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
- 				 PV_HORZA_HBP) |
--		   VC4_SET_FIELD((mode->hsync_end -
--				  mode->hsync_start) * pixel_rep,
-+		   VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
- 				 PV_HORZA_HSYNC));
-+
- 	CRTC_WRITE(PV_HORZB,
--		   VC4_SET_FIELD((mode->hsync_start -
--				  mode->hdisplay) * pixel_rep,
-+		   VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
- 				 PV_HORZB_HFP) |
--		   VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
-+		   VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
-+				 PV_HORZB_HACTIVE));
- 
- 	CRTC_WRITE(PV_VERTA,
- 		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-@@ -1038,6 +1038,7 @@ static const struct drm_crtc_helper_func
- static const struct vc4_crtc_data bcm2835_pv0_data = {
- 	.hvs_channel = 0,
- 	.debugfs_name = "crtc0_regs",
-+	.pixels_per_clock = 1,
- 	.encoder_types = {
- 		[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
- 		[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
-@@ -1047,6 +1048,7 @@ static const struct vc4_crtc_data bcm283
- static const struct vc4_crtc_data bcm2835_pv1_data = {
- 	.hvs_channel = 2,
- 	.debugfs_name = "crtc1_regs",
-+	.pixels_per_clock = 1,
- 	.encoder_types = {
- 		[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
- 		[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
-@@ -1056,6 +1058,7 @@ static const struct vc4_crtc_data bcm283
- static const struct vc4_crtc_data bcm2835_pv2_data = {
- 	.hvs_channel = 1,
- 	.debugfs_name = "crtc2_regs",
-+	.pixels_per_clock = 1,
- 	.encoder_types = {
- 		[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
- 		[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
---- a/drivers/gpu/drm/vc4/vc4_drv.h
-+++ b/drivers/gpu/drm/vc4/vc4_drv.h
-@@ -455,6 +455,9 @@ struct vc4_crtc_data {
- 	/* Which channel of the HVS this pixelvalve sources from. */
- 	int hvs_channel;
- 
-+	/* Number of pixels output per clock period */
-+	u8 pixels_per_clock;
-+
- 	enum vc4_encoder_type encoder_types[4];
- 	const char *debugfs_name;
- };