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Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0539-drm-vc4-drv-Add-support-for-the-BCM2711-HVS5.patch')
-rw-r--r--target/linux/bcm27xx/patches-5.4/950-0539-drm-vc4-drv-Add-support-for-the-BCM2711-HVS5.patch497
1 files changed, 0 insertions, 497 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0539-drm-vc4-drv-Add-support-for-the-BCM2711-HVS5.patch b/target/linux/bcm27xx/patches-5.4/950-0539-drm-vc4-drv-Add-support-for-the-BCM2711-HVS5.patch
deleted file mode 100644
index a02663ac8b..0000000000
--- a/target/linux/bcm27xx/patches-5.4/950-0539-drm-vc4-drv-Add-support-for-the-BCM2711-HVS5.patch
+++ /dev/null
@@ -1,497 +0,0 @@
-From 354d70a82947041b3d7b87f69641a6741febfc95 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.com>
-Date: Thu, 8 Aug 2019 17:51:07 +0100
-Subject: [PATCH] drm/vc4: drv: Add support for the BCM2711 HVS5
-
-The HVS found in the BCM2711 is slightly different from the previous
-generations.
-
-Most notably, the display list layout changes a bit, the LBM doesn't have
-the same size and the formats ordering for some formats is swapped.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
-Signed-off-by: Maxime Ripard <maxime@cerno.tech>
----
- drivers/gpu/drm/vc4/vc4_crtc.c | 24 +++-
- drivers/gpu/drm/vc4/vc4_drv.h | 4 +
- drivers/gpu/drm/vc4/vc4_hvs.c | 17 ++-
- drivers/gpu/drm/vc4/vc4_plane.c | 194 +++++++++++++++++++++++---------
- drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++
- 5 files changed, 247 insertions(+), 59 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -550,6 +550,7 @@ static void vc4_crtc_atomic_enable(struc
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- struct drm_display_mode *mode = &crtc->state->adjusted_mode;
-+ u32 dispctrl;
-
- require_hvs_enabled(dev);
-
-@@ -564,11 +565,24 @@ static void vc4_crtc_atomic_enable(struc
- * When feeding the transposer, we should operate in oneshot
- * mode.
- */
-- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
-- VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
-- VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
-- SCALER_DISPCTRLX_ENABLE |
-- (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
-+ dispctrl = SCALER_DISPCTRLX_ENABLE;
-+
-+ if (!vc4->hvs->hvs5)
-+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
-+ SCALER_DISPCTRLX_WIDTH) |
-+ VC4_SET_FIELD(mode->vdisplay,
-+ SCALER_DISPCTRLX_HEIGHT) |
-+ (vc4_state->feed_txp ?
-+ SCALER_DISPCTRLX_ONESHOT : 0);
-+ else
-+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
-+ SCALER5_DISPCTRLX_WIDTH) |
-+ VC4_SET_FIELD(mode->vdisplay,
-+ SCALER5_DISPCTRLX_HEIGHT) |
-+ (vc4_state->feed_txp ?
-+ SCALER5_DISPCTRLX_ONESHOT : 0);
-+
-+ HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
-
- /* When feeding the transposer block the pixelvalve is unneeded and
- * should not be enabled.
---- a/drivers/gpu/drm/vc4/vc4_drv.h
-+++ b/drivers/gpu/drm/vc4/vc4_drv.h
-@@ -336,7 +336,11 @@ struct vc4_hvs {
- spinlock_t mm_lock;
-
- struct drm_mm_node mitchell_netravali_filter;
-+
- struct debugfs_regset32 regset;
-+
-+ /* HVS version 5 flag, therefore requires updated dlist structures */
-+ bool hvs5;
- };
-
- struct vc4_plane {
---- a/drivers/gpu/drm/vc4/vc4_hvs.c
-+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
-@@ -223,6 +223,7 @@ static int vc4_hvs_bind(struct device *d
- struct vc4_hvs *hvs = NULL;
- int ret;
- u32 dispctrl;
-+ unsigned int hvs_version;
-
- hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
- if (!hvs)
-@@ -238,7 +239,14 @@ static int vc4_hvs_bind(struct device *d
- hvs->regset.regs = hvs_regs;
- hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
-
-- hvs->dlist = hvs->regs + SCALER_DLIST_START;
-+ hvs_version = readl(hvs->regs + SCALER_DISPLSTAT) >> 24;
-+ if (hvs_version >= 0x40)
-+ hvs->hvs5 = true;
-+
-+ if (!hvs->hvs5)
-+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
-+ else
-+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
-
- spin_lock_init(&hvs->mm_lock);
-
-@@ -256,7 +264,12 @@ static int vc4_hvs_bind(struct device *d
- * between planes when they don't overlap on the screen, but
- * for now we just allocate globally.
- */
-- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
-+ if (!hvs->hvs5)
-+ /* 96kB */
-+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
-+ else
-+ /* 70k words */
-+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
-
- /* Upload filter kernels. We only have the one for now, so we
- * keep it around for the lifetime of the driver.
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -32,45 +32,60 @@ static const struct hvs_format {
- u32 drm; /* DRM_FORMAT_* */
- u32 hvs; /* HVS_FORMAT_* */
- u32 pixel_order;
-+ u32 pixel_order_hvs5;
- } hvs_formats[] = {
- {
-- .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
-+ .drm = DRM_FORMAT_XRGB8888,
-+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
- .pixel_order = HVS_PIXEL_ORDER_ABGR,
-+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
- },
- {
-- .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
-+ .drm = DRM_FORMAT_ARGB8888,
-+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
- .pixel_order = HVS_PIXEL_ORDER_ABGR,
-+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
- },
- {
-- .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
-+ .drm = DRM_FORMAT_ABGR8888,
-+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
- .pixel_order = HVS_PIXEL_ORDER_ARGB,
-+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
- },
- {
-- .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
-+ .drm = DRM_FORMAT_XBGR8888,
-+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
- .pixel_order = HVS_PIXEL_ORDER_ARGB,
-+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
- },
- {
-- .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
-+ .drm = DRM_FORMAT_RGB565,
-+ .hvs = HVS_PIXEL_FORMAT_RGB565,
- .pixel_order = HVS_PIXEL_ORDER_XRGB,
- },
- {
-- .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
-+ .drm = DRM_FORMAT_BGR565,
-+ .hvs = HVS_PIXEL_FORMAT_RGB565,
- .pixel_order = HVS_PIXEL_ORDER_XBGR,
- },
- {
-- .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
-+ .drm = DRM_FORMAT_ARGB1555,
-+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
- .pixel_order = HVS_PIXEL_ORDER_ABGR,
- },
- {
-- .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
-+ .drm = DRM_FORMAT_XRGB1555,
-+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
- .pixel_order = HVS_PIXEL_ORDER_ABGR,
- },
- {
-- .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
-+ .drm = DRM_FORMAT_RGB888,
-+ .hvs = HVS_PIXEL_FORMAT_RGB888,
- .pixel_order = HVS_PIXEL_ORDER_XRGB,
- },
- {
-- .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
-+ .drm = DRM_FORMAT_BGR888,
-+ .hvs = HVS_PIXEL_FORMAT_RGB888,
- .pixel_order = HVS_PIXEL_ORDER_XBGR,
- },
- {
-@@ -836,35 +851,6 @@ static int vc4_plane_mode_set(struct drm
- return -EINVAL;
- }
-
-- /* Control word */
-- vc4_dlist_write(vc4_state,
-- SCALER_CTL0_VALID |
-- (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
-- (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
-- VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
-- (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
-- (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
-- VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
-- (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
-- VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
-- VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
--
-- /* Position Word 0: Image Positions and Alpha Value */
-- vc4_state->pos0_offset = vc4_state->dlist_count;
-- vc4_dlist_write(vc4_state,
-- VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
-- VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
-- VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
--
-- /* Position Word 1: Scaled Image Dimensions. */
-- if (!vc4_state->is_unity) {
-- vc4_dlist_write(vc4_state,
-- VC4_SET_FIELD(vc4_state->crtc_w,
-- SCALER_POS1_SCL_WIDTH) |
-- VC4_SET_FIELD(vc4_state->crtc_h,
-- SCALER_POS1_SCL_HEIGHT));
-- }
--
- /* Don't waste cycles mixing with plane alpha if the set alpha
- * is opaque or there is no per-pixel alpha information.
- * In any case we use the alpha property value as the fixed alpha.
-@@ -872,20 +858,120 @@ static int vc4_plane_mode_set(struct drm
- mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
- fb->format->has_alpha;
-
-- /* Position Word 2: Source Image Size, Alpha */
-- vc4_state->pos2_offset = vc4_state->dlist_count;
-- vc4_dlist_write(vc4_state,
-- VC4_SET_FIELD(fb->format->has_alpha ?
-- SCALER_POS2_ALPHA_MODE_PIPELINE :
-- SCALER_POS2_ALPHA_MODE_FIXED,
-- SCALER_POS2_ALPHA_MODE) |
-- (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
-- (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
-- VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
-- VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
-+ if (!vc4->hvs->hvs5) {
-+ /* Control word */
-+ vc4_dlist_write(vc4_state,
-+ SCALER_CTL0_VALID |
-+ (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
-+ (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
-+ VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
-+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
-+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
-+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
-+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
-+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
-+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
-+
-+ /* Position Word 0: Image Positions and Alpha Value */
-+ vc4_state->pos0_offset = vc4_state->dlist_count;
-+ vc4_dlist_write(vc4_state,
-+ VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
-+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
-+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
-+
-+ /* Position Word 1: Scaled Image Dimensions. */
-+ if (!vc4_state->is_unity) {
-+ vc4_dlist_write(vc4_state,
-+ VC4_SET_FIELD(vc4_state->crtc_w,
-+ SCALER_POS1_SCL_WIDTH) |
-+ VC4_SET_FIELD(vc4_state->crtc_h,
-+ SCALER_POS1_SCL_HEIGHT));
-+ }
-+
-+ /* Position Word 2: Source Image Size, Alpha */
-+ vc4_state->pos2_offset = vc4_state->dlist_count;
-+ vc4_dlist_write(vc4_state,
-+ VC4_SET_FIELD(fb->format->has_alpha ?
-+ SCALER_POS2_ALPHA_MODE_PIPELINE :
-+ SCALER_POS2_ALPHA_MODE_FIXED,
-+ SCALER_POS2_ALPHA_MODE) |
-+ (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
-+ (fb->format->has_alpha ?
-+ SCALER_POS2_ALPHA_PREMULT : 0) |
-+ VC4_SET_FIELD(vc4_state->src_w[0],
-+ SCALER_POS2_WIDTH) |
-+ VC4_SET_FIELD(vc4_state->src_h[0],
-+ SCALER_POS2_HEIGHT));
-
-- /* Position Word 3: Context. Written by the HVS. */
-- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
-+ /* Position Word 3: Context. Written by the HVS. */
-+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
-+
-+ } else {
-+ u32 hvs_pixel_order = format->pixel_order;
-+
-+ if (format->pixel_order_hvs5)
-+ hvs_pixel_order = format->pixel_order_hvs5;
-+
-+ /* Control word */
-+ vc4_dlist_write(vc4_state,
-+ SCALER_CTL0_VALID |
-+ (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
-+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
-+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
-+ (vc4_state->is_unity ?
-+ SCALER5_CTL0_UNITY : 0) |
-+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
-+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
-+ SCALER5_CTL0_ALPHA_EXPAND |
-+ SCALER5_CTL0_RGB_EXPAND);
-+
-+ /* Position Word 0: Image Positions and Alpha Value */
-+ vc4_state->pos0_offset = vc4_state->dlist_count;
-+ vc4_dlist_write(vc4_state,
-+ (rotation & DRM_MODE_REFLECT_Y ?
-+ SCALER5_POS0_VFLIP : 0) |
-+ VC4_SET_FIELD(vc4_state->crtc_x,
-+ SCALER_POS0_START_X) |
-+ (rotation & DRM_MODE_REFLECT_X ?
-+ SCALER5_POS0_HFLIP : 0) |
-+ VC4_SET_FIELD(vc4_state->crtc_y,
-+ SCALER5_POS0_START_Y)
-+ );
-+
-+ /* Control Word 2 */
-+ vc4_dlist_write(vc4_state,
-+ VC4_SET_FIELD(state->alpha >> 4,
-+ SCALER5_CTL2_ALPHA) |
-+ fb->format->has_alpha ?
-+ SCALER5_CTL2_ALPHA_PREMULT : 0 |
-+ (mix_plane_alpha ?
-+ SCALER5_CTL2_ALPHA_MIX : 0) |
-+ VC4_SET_FIELD(fb->format->has_alpha ?
-+ SCALER5_CTL2_ALPHA_MODE_PIPELINE :
-+ SCALER5_CTL2_ALPHA_MODE_FIXED,
-+ SCALER5_CTL2_ALPHA_MODE)
-+ );
-+
-+ /* Position Word 1: Scaled Image Dimensions. */
-+ if (!vc4_state->is_unity) {
-+ vc4_dlist_write(vc4_state,
-+ VC4_SET_FIELD(vc4_state->crtc_w,
-+ SCALER_POS1_SCL_WIDTH) |
-+ VC4_SET_FIELD(vc4_state->crtc_h,
-+ SCALER_POS1_SCL_HEIGHT));
-+ }
-+
-+ /* Position Word 2: Source Image Size */
-+ vc4_state->pos2_offset = vc4_state->dlist_count;
-+ vc4_dlist_write(vc4_state,
-+ VC4_SET_FIELD(vc4_state->src_w[0],
-+ SCALER5_POS2_WIDTH) |
-+ VC4_SET_FIELD(vc4_state->src_h[0],
-+ SCALER5_POS2_HEIGHT));
-+
-+ /* Position Word 3: Context. Written by the HVS. */
-+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
-+ }
-
-
- /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
-@@ -1276,6 +1362,10 @@ static bool vc4_format_mod_supported(str
- default:
- return false;
- }
-+ case DRM_FORMAT_RGBX1010102:
-+ case DRM_FORMAT_BGRX1010102:
-+ case DRM_FORMAT_RGBA1010102:
-+ case DRM_FORMAT_BGRA1010102:
- case DRM_FORMAT_YUV422:
- case DRM_FORMAT_YVU422:
- case DRM_FORMAT_YUV420:
---- a/drivers/gpu/drm/vc4/vc4_regs.h
-+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -328,6 +328,20 @@
- # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
- # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
-
-+# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
-+# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
-+/* Generates a single frame when VSTART is seen and stops at the last
-+ * pixel read from the FIFO.
-+ */
-+# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
-+/* Processes a single context in the dlist and then task switch,
-+ * instead of an entire line.
-+ */
-+# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
-+# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
-+# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
-+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
-+
- #define SCALER_DISPBKGND0 0x00000044
- # define SCALER_DISPBKGND_AUTOHS BIT(31)
- # define SCALER_DISPBKGND_INTERLACE BIT(30)
-@@ -461,6 +475,8 @@
- #define SCALER_DLIST_START 0x00002000
- #define SCALER_DLIST_SIZE 0x00004000
-
-+#define SCALER5_DLIST_START 0x00004000
-+
- #define VC4_HDMI_CORE_REV 0x000
-
- #define VC4_HDMI_SW_RESET_CONTROL 0x004
-@@ -826,6 +842,8 @@ enum hvs_pixel_format {
- HVS_PIXEL_FORMAT_PALETTE = 13,
- HVS_PIXEL_FORMAT_YUV444_RGB = 14,
- HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
-+ HVS_PIXEL_FORMAT_RGBA1010102 = 16,
-+ HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
- };
-
- /* Note: the LSB is the rightmost character shown. Only valid for
-@@ -880,6 +898,10 @@ enum hvs_pixel_format {
- #define SCALER_CTL0_RGBA_EXPAND_MSB 2
- #define SCALER_CTL0_RGBA_EXPAND_ROUND 3
-
-+#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
-+
-+#define SCALER5_CTL0_RGB_EXPAND BIT(11)
-+
- #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
- #define SCALER_CTL0_SCL1_SHIFT 8
-
-@@ -897,10 +919,13 @@ enum hvs_pixel_format {
-
- /* Set to indicate no scaling. */
- #define SCALER_CTL0_UNITY BIT(4)
-+#define SCALER5_CTL0_UNITY BIT(15)
-
- #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
- #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
-
-+#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
-+
- #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
- #define SCALER_POS0_FIXED_ALPHA_SHIFT 24
-
-@@ -910,12 +935,48 @@ enum hvs_pixel_format {
- #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
- #define SCALER_POS0_START_X_SHIFT 0
-
-+#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
-+#define SCALER5_POS0_START_Y_SHIFT 16
-+
-+#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
-+#define SCALER5_POS0_START_X_SHIFT 0
-+
-+#define SCALER5_POS0_VFLIP BIT(31)
-+#define SCALER5_POS0_HFLIP BIT(15)
-+
-+#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
-+#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
-+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
-+#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
-+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
-+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
-+
-+#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
-+
-+#define SCALER5_CTL2_ALPHA_MIX BIT(28)
-+
-+#define SCALER5_CTL2_ALPHA_LOC BIT(25)
-+
-+#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
-+#define SCALER5_CTL2_MAP_SEL_SHIFT 17
-+
-+#define SCALER5_CTL2_GAMMA BIT(16)
-+
-+#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
-+#define SCALER5_CTL2_ALPHA_SHIFT 4
-+
- #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
- #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
-
- #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
- #define SCALER_POS1_SCL_WIDTH_SHIFT 0
-
-+#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
-+#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
-+
-+#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
-+#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
-+
- #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
- #define SCALER_POS2_ALPHA_MODE_SHIFT 30
- #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
-@@ -931,6 +992,12 @@ enum hvs_pixel_format {
- #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
- #define SCALER_POS2_WIDTH_SHIFT 0
-
-+#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
-+#define SCALER5_POS2_HEIGHT_SHIFT 16
-+
-+#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
-+#define SCALER5_POS2_WIDTH_SHIFT 0
-+
- /* Color Space Conversion words. Some values are S2.8 signed
- * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
- * 0x2: 2, 0x3: -1}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-23 03:59:19 +0000