diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0522-clk-bcm-rpi-Split-pllb-clock-hooks.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.4/950-0522-clk-bcm-rpi-Split-pllb-clock-hooks.patch | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0522-clk-bcm-rpi-Split-pllb-clock-hooks.patch b/target/linux/bcm27xx/patches-5.4/950-0522-clk-bcm-rpi-Split-pllb-clock-hooks.patch new file mode 100644 index 0000000000..38720b89bd --- /dev/null +++ b/target/linux/bcm27xx/patches-5.4/950-0522-clk-bcm-rpi-Split-pllb-clock-hooks.patch @@ -0,0 +1,80 @@ +From e2537b383e247198347e7124876b9ead531dbeef Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime@cerno.tech> +Date: Fri, 7 Feb 2020 16:14:18 +0100 +Subject: [PATCH] clk: bcm: rpi: Split pllb clock hooks + +The driver only supports the pllb for now and all the clock framework hooks +are a mix of the generic firmware interface and the specifics of the pllb. +Since we will support more clocks in the future let's split the generic and +specific hooks + +Cc: Michael Turquette <mturquette@baylibre.com> +Cc: linux-clk@vger.kernel.org +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Signed-off-by: Maxime Ripard <maxime@cerno.tech> +--- + drivers/clk/bcm/clk-raspberrypi.c | 30 ++++++++++++++++++++++-------- + 1 file changed, 22 insertions(+), 8 deletions(-) + +--- a/drivers/clk/bcm/clk-raspberrypi.c ++++ b/drivers/clk/bcm/clk-raspberrypi.c +@@ -104,8 +104,8 @@ static int raspberrypi_fw_is_prepared(st + } + + +-static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw, +- unsigned long parent_rate) ++static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw, ++ unsigned long parent_rate) + { + struct raspberrypi_clk_data *data = + container_of(hw, struct raspberrypi_clk_data, hw); +@@ -118,21 +118,27 @@ static unsigned long raspberrypi_fw_pll_ + if (ret) + return ret; + +- return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE; ++ return val; + } + +-static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate, +- unsigned long parent_rate) ++static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ return raspberrypi_fw_get_rate(hw, parent_rate) * ++ RPI_FIRMWARE_PLLB_ARM_DIV_RATE; ++} ++ ++static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) + { + struct raspberrypi_clk_data *data = + container_of(hw, struct raspberrypi_clk_data, hw); + struct raspberrypi_clk *rpi = data->rpi; +- u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE; ++ u32 _rate = rate; + int ret; + + ret = raspberrypi_clock_property(rpi->firmware, data, +- RPI_FIRMWARE_SET_CLOCK_RATE, +- &new_rate); ++ RPI_FIRMWARE_SET_CLOCK_RATE, &_rate); + if (ret) + dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d", + clk_hw_get_name(hw), ret); +@@ -140,6 +146,14 @@ static int raspberrypi_fw_pll_set_rate(s + return ret; + } + ++static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE; ++ ++ return raspberrypi_fw_set_rate(hw, new_rate, parent_rate); ++} ++ + /* + * Sadly there is no firmware rate rounding interface. We borrowed it from + * clk-bcm2835. |