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Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0455-PCI-brcmstb-Fix-build-on-32bit-ARM-platforms-with-ol.patch')
-rw-r--r--target/linux/bcm27xx/patches-5.4/950-0455-PCI-brcmstb-Fix-build-on-32bit-ARM-platforms-with-ol.patch38
1 files changed, 38 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0455-PCI-brcmstb-Fix-build-on-32bit-ARM-platforms-with-ol.patch b/target/linux/bcm27xx/patches-5.4/950-0455-PCI-brcmstb-Fix-build-on-32bit-ARM-platforms-with-ol.patch
new file mode 100644
index 0000000000..6bb45ccb1f
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.4/950-0455-PCI-brcmstb-Fix-build-on-32bit-ARM-platforms-with-ol.patch
@@ -0,0 +1,38 @@
+From 39192141aa16809323c24d8910e3a63488f7f55d Mon Sep 17 00:00:00 2001
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Thu, 27 Feb 2020 12:51:46 +0100
+Subject: [PATCH] PCI: brcmstb: Fix build on 32bit ARM platforms with
+ older compilers
+
+commit 73a7a271b3eee7b83f29b13866163776f1cbef89 upstream.
+
+Some older compilers have no implementation for the helper for 64-bit
+unsigned division/modulo, so linking pcie-brcmstb driver causes the
+"undefined reference to `__aeabi_uldivmod'" error.
+
+*rc_bar2_size is always a power of two, because it is calculated as:
+"1ULL << fls64(entry->res->end - entry->res->start)", so the modulo
+operation in the subsequent check can be replaced by a simple logical
+AND with a proper mask.
+
+Link: https://lore.kernel.org/r/20200227115146.24515-1-m.szyprowski@samsung.com
+Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+---
+ drivers/pci/controller/pcie-brcmstb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-brcmstb.c
++++ b/drivers/pci/controller/pcie-brcmstb.c
+@@ -670,7 +670,7 @@ static inline int brcm_pcie_get_rc_bar2_
+ * outbound memory @ 3GB). So instead it will start at the 1x
+ * multiple of its size
+ */
+- if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
++ if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
+ (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
+ dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
+ *rc_bar2_size, *rc_bar2_offset);