diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0441-bcm2835-dma-Correct-SoC-name.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.4/950-0441-bcm2835-dma-Correct-SoC-name.patch | 489 |
1 files changed, 0 insertions, 489 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0441-bcm2835-dma-Correct-SoC-name.patch b/target/linux/bcm27xx/patches-5.4/950-0441-bcm2835-dma-Correct-SoC-name.patch deleted file mode 100644 index fe33168a4d..0000000000 --- a/target/linux/bcm27xx/patches-5.4/950-0441-bcm2835-dma-Correct-SoC-name.patch +++ /dev/null @@ -1,489 +0,0 @@ -From f498861a16d0b9a189a329080da1aa64d6e9bda7 Mon Sep 17 00:00:00 2001 -From: Phil Elwell <phil@raspberrypi.com> -Date: Fri, 31 Jan 2020 09:28:57 +0000 -Subject: [PATCH] bcm2835-dma: Correct SoC name - -The Pi 4 SoC is called BCM2711, not BCM2838. - -Fixes: "bcm2835-dma: Add proper 40-bit DMA support" ---- - drivers/dma/bcm2835-dma.c | 274 +++++++++++++++++++------------------- - 1 file changed, 137 insertions(+), 137 deletions(-) - ---- a/drivers/dma/bcm2835-dma.c -+++ b/drivers/dma/bcm2835-dma.c -@@ -38,7 +38,7 @@ - #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 - #define BCM2835_DMA_CHAN_NAME_SIZE 8 - #define BCM2835_DMA_BULK_MASK BIT(0) --#define BCM2838_DMA_MEMCPY_CHAN 14 -+#define BCM2711_DMA_MEMCPY_CHAN 14 - - struct bcm2835_dma_cfg_data { - u32 chan_40bit_mask; -@@ -70,7 +70,7 @@ struct bcm2835_dma_cb { - uint32_t pad[2]; - }; - --struct bcm2838_dma40_scb { -+struct bcm2711_dma40_scb { - uint32_t ti; - uint32_t src; - uint32_t srci; -@@ -200,98 +200,98 @@ struct bcm2835_desc { - #define MAX_LITE_DMA_LEN (SZ_64K - 4) - - /* 40-bit DMA support */ --#define BCM2838_DMA40_CS 0x00 --#define BCM2838_DMA40_CB 0x04 --#define BCM2838_DMA40_DEBUG 0x0c --#define BCM2838_DMA40_TI 0x10 --#define BCM2838_DMA40_SRC 0x14 --#define BCM2838_DMA40_SRCI 0x18 --#define BCM2838_DMA40_DEST 0x1c --#define BCM2838_DMA40_DESTI 0x20 --#define BCM2838_DMA40_LEN 0x24 --#define BCM2838_DMA40_NEXT_CB 0x28 --#define BCM2838_DMA40_DEBUG2 0x2c -- --#define BCM2838_DMA40_ACTIVE BIT(0) --#define BCM2838_DMA40_END BIT(1) --#define BCM2838_DMA40_INT BIT(2) --#define BCM2838_DMA40_DREQ BIT(3) /* DREQ state */ --#define BCM2838_DMA40_RD_PAUSED BIT(4) /* Reading is paused */ --#define BCM2838_DMA40_WR_PAUSED BIT(5) /* Writing is paused */ --#define BCM2838_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */ --#define BCM2838_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */ --#define BCM2838_DMA40_ERR BIT(10) --#define BCM2838_DMA40_QOS(x) (((x) & 0x1f) << 16) --#define BCM2838_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20) --#define BCM2838_DMA40_WAIT_FOR_WRITES BIT(28) --#define BCM2838_DMA40_DISDEBUG BIT(29) --#define BCM2838_DMA40_ABORT BIT(30) --#define BCM2838_DMA40_HALT BIT(31) --#define BCM2838_DMA40_CS_FLAGS(x) (x & (BCM2838_DMA40_QOS(15) | \ -- BCM2838_DMA40_PANIC_QOS(15) | \ -- BCM2838_DMA40_WAIT_FOR_WRITES | \ -- BCM2838_DMA40_DISDEBUG)) -+#define BCM2711_DMA40_CS 0x00 -+#define BCM2711_DMA40_CB 0x04 -+#define BCM2711_DMA40_DEBUG 0x0c -+#define BCM2711_DMA40_TI 0x10 -+#define BCM2711_DMA40_SRC 0x14 -+#define BCM2711_DMA40_SRCI 0x18 -+#define BCM2711_DMA40_DEST 0x1c -+#define BCM2711_DMA40_DESTI 0x20 -+#define BCM2711_DMA40_LEN 0x24 -+#define BCM2711_DMA40_NEXT_CB 0x28 -+#define BCM2711_DMA40_DEBUG2 0x2c -+ -+#define BCM2711_DMA40_ACTIVE BIT(0) -+#define BCM2711_DMA40_END BIT(1) -+#define BCM2711_DMA40_INT BIT(2) -+#define BCM2711_DMA40_DREQ BIT(3) /* DREQ state */ -+#define BCM2711_DMA40_RD_PAUSED BIT(4) /* Reading is paused */ -+#define BCM2711_DMA40_WR_PAUSED BIT(5) /* Writing is paused */ -+#define BCM2711_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */ -+#define BCM2711_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */ -+#define BCM2711_DMA40_ERR BIT(10) -+#define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16) -+#define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20) -+#define BCM2711_DMA40_WAIT_FOR_WRITES BIT(28) -+#define BCM2711_DMA40_DISDEBUG BIT(29) -+#define BCM2711_DMA40_ABORT BIT(30) -+#define BCM2711_DMA40_HALT BIT(31) -+#define BCM2711_DMA40_CS_FLAGS(x) (x & (BCM2711_DMA40_QOS(15) | \ -+ BCM2711_DMA40_PANIC_QOS(15) | \ -+ BCM2711_DMA40_WAIT_FOR_WRITES | \ -+ BCM2711_DMA40_DISDEBUG)) - - /* Transfer information bits */ --#define BCM2838_DMA40_INTEN BIT(0) --#define BCM2838_DMA40_TDMODE BIT(1) /* 2D-Mode */ --#define BCM2838_DMA40_WAIT_RESP BIT(2) /* wait for AXI write to be acked */ --#define BCM2838_DMA40_WAIT_RD_RESP BIT(3) /* wait for AXI read to complete */ --#define BCM2838_DMA40_PER_MAP(x) ((x & 31) << 9) /* REQ source */ --#define BCM2838_DMA40_S_DREQ BIT(14) /* enable SREQ for source */ --#define BCM2838_DMA40_D_DREQ BIT(15) /* enable DREQ for destination */ --#define BCM2838_DMA40_S_WAIT(x) ((x & 0xff) << 16) /* add DMA read-wait cycles */ --#define BCM2838_DMA40_D_WAIT(x) ((x & 0xff) << 24) /* add DMA write-wait cycles */ -+#define BCM2711_DMA40_INTEN BIT(0) -+#define BCM2711_DMA40_TDMODE BIT(1) /* 2D-Mode */ -+#define BCM2711_DMA40_WAIT_RESP BIT(2) /* wait for AXI write to be acked */ -+#define BCM2711_DMA40_WAIT_RD_RESP BIT(3) /* wait for AXI read to complete */ -+#define BCM2711_DMA40_PER_MAP(x) ((x & 31) << 9) /* REQ source */ -+#define BCM2711_DMA40_S_DREQ BIT(14) /* enable SREQ for source */ -+#define BCM2711_DMA40_D_DREQ BIT(15) /* enable DREQ for destination */ -+#define BCM2711_DMA40_S_WAIT(x) ((x & 0xff) << 16) /* add DMA read-wait cycles */ -+#define BCM2711_DMA40_D_WAIT(x) ((x & 0xff) << 24) /* add DMA write-wait cycles */ - - /* debug register bits */ --#define BCM2838_DMA40_DEBUG_WRITE_ERR BIT(0) --#define BCM2838_DMA40_DEBUG_FIFO_ERR BIT(1) --#define BCM2838_DMA40_DEBUG_READ_ERR BIT(2) --#define BCM2838_DMA40_DEBUG_READ_CB_ERR BIT(3) --#define BCM2838_DMA40_DEBUG_IN_ON_ERR BIT(8) --#define BCM2838_DMA40_DEBUG_ABORT_ON_ERR BIT(9) --#define BCM2838_DMA40_DEBUG_HALT_ON_ERR BIT(10) --#define BCM2838_DMA40_DEBUG_DISABLE_CLK_GATE BIT(11) --#define BCM2838_DMA40_DEBUG_RSTATE_SHIFT 14 --#define BCM2838_DMA40_DEBUG_RSTATE_BITS 4 --#define BCM2838_DMA40_DEBUG_WSTATE_SHIFT 18 --#define BCM2838_DMA40_DEBUG_WSTATE_BITS 4 --#define BCM2838_DMA40_DEBUG_RESET BIT(23) --#define BCM2838_DMA40_DEBUG_ID_SHIFT 24 --#define BCM2838_DMA40_DEBUG_ID_BITS 4 --#define BCM2838_DMA40_DEBUG_VERSION_SHIFT 28 --#define BCM2838_DMA40_DEBUG_VERSION_BITS 4 -+#define BCM2711_DMA40_DEBUG_WRITE_ERR BIT(0) -+#define BCM2711_DMA40_DEBUG_FIFO_ERR BIT(1) -+#define BCM2711_DMA40_DEBUG_READ_ERR BIT(2) -+#define BCM2711_DMA40_DEBUG_READ_CB_ERR BIT(3) -+#define BCM2711_DMA40_DEBUG_IN_ON_ERR BIT(8) -+#define BCM2711_DMA40_DEBUG_ABORT_ON_ERR BIT(9) -+#define BCM2711_DMA40_DEBUG_HALT_ON_ERR BIT(10) -+#define BCM2711_DMA40_DEBUG_DISABLE_CLK_GATE BIT(11) -+#define BCM2711_DMA40_DEBUG_RSTATE_SHIFT 14 -+#define BCM2711_DMA40_DEBUG_RSTATE_BITS 4 -+#define BCM2711_DMA40_DEBUG_WSTATE_SHIFT 18 -+#define BCM2711_DMA40_DEBUG_WSTATE_BITS 4 -+#define BCM2711_DMA40_DEBUG_RESET BIT(23) -+#define BCM2711_DMA40_DEBUG_ID_SHIFT 24 -+#define BCM2711_DMA40_DEBUG_ID_BITS 4 -+#define BCM2711_DMA40_DEBUG_VERSION_SHIFT 28 -+#define BCM2711_DMA40_DEBUG_VERSION_BITS 4 - - /* Valid only for channels 0 - 3 (11 - 14) */ --#define BCM2838_DMA40_CHAN(n) (((n) + 11) << 8) /* Base address */ --#define BCM2838_DMA40_CHANIO(base, n) ((base) + BCM2838_DMA_CHAN(n)) -+#define BCM2711_DMA40_CHAN(n) (((n) + 11) << 8) /* Base address */ -+#define BCM2711_DMA40_CHANIO(base, n) ((base) + BCM2711_DMA_CHAN(n)) - - /* the max dma length for different channels */ - #define MAX_DMA40_LEN SZ_1G - --#define BCM2838_DMA40_BURST_LEN(x) ((min(x,16) - 1) << 8) --#define BCM2838_DMA40_INC BIT(12) --#define BCM2838_DMA40_SIZE_32 (0 << 13) --#define BCM2838_DMA40_SIZE_64 (1 << 13) --#define BCM2838_DMA40_SIZE_128 (2 << 13) --#define BCM2838_DMA40_SIZE_256 (3 << 13) --#define BCM2838_DMA40_IGNORE BIT(15) --#define BCM2838_DMA40_STRIDE(x) ((x) << 16) /* For 2D mode */ -- --#define BCM2838_DMA40_MEMCPY_FLAGS \ -- (BCM2838_DMA40_QOS(0) | \ -- BCM2838_DMA40_PANIC_QOS(0) | \ -- BCM2838_DMA40_WAIT_FOR_WRITES | \ -- BCM2838_DMA40_DISDEBUG) -- --#define BCM2838_DMA40_MEMCPY_XFER_INFO \ -- (BCM2838_DMA40_SIZE_128 | \ -- BCM2838_DMA40_INC | \ -- BCM2838_DMA40_BURST_LEN(16)) -+#define BCM2711_DMA40_BURST_LEN(x) ((min(x,16) - 1) << 8) -+#define BCM2711_DMA40_INC BIT(12) -+#define BCM2711_DMA40_SIZE_32 (0 << 13) -+#define BCM2711_DMA40_SIZE_64 (1 << 13) -+#define BCM2711_DMA40_SIZE_128 (2 << 13) -+#define BCM2711_DMA40_SIZE_256 (3 << 13) -+#define BCM2711_DMA40_IGNORE BIT(15) -+#define BCM2711_DMA40_STRIDE(x) ((x) << 16) /* For 2D mode */ -+ -+#define BCM2711_DMA40_MEMCPY_FLAGS \ -+ (BCM2711_DMA40_QOS(0) | \ -+ BCM2711_DMA40_PANIC_QOS(0) | \ -+ BCM2711_DMA40_WAIT_FOR_WRITES | \ -+ BCM2711_DMA40_DISDEBUG) -+ -+#define BCM2711_DMA40_MEMCPY_XFER_INFO \ -+ (BCM2711_DMA40_SIZE_128 | \ -+ BCM2711_DMA40_INC | \ -+ BCM2711_DMA40_BURST_LEN(16)) - - struct bcm2835_dmadev *memcpy_parent; - static void __iomem *memcpy_chan; --static struct bcm2838_dma40_scb *memcpy_scb; -+static struct bcm2711_dma40_scb *memcpy_scb; - static dma_addr_t memcpy_scb_dma; - DEFINE_SPINLOCK(memcpy_lock); - -@@ -299,7 +299,7 @@ static const struct bcm2835_dma_cfg_data - .chan_40bit_mask = 0, - }; - --static const struct bcm2835_dma_cfg_data bcm2838_dma_cfg = { -+static const struct bcm2835_dma_cfg_data bcm2711_dma_cfg = { - .chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), - }; - -@@ -332,27 +332,27 @@ static inline struct bcm2835_desc *to_bc - return container_of(t, struct bcm2835_desc, vd.tx); - } - --static inline uint32_t to_bcm2838_ti(uint32_t info) -+static inline uint32_t to_bcm2711_ti(uint32_t info) - { -- return ((info & BCM2835_DMA_INT_EN) ? BCM2838_DMA40_INTEN : 0) | -- ((info & BCM2835_DMA_WAIT_RESP) ? BCM2838_DMA40_WAIT_RESP : 0) | -+ return ((info & BCM2835_DMA_INT_EN) ? BCM2711_DMA40_INTEN : 0) | -+ ((info & BCM2835_DMA_WAIT_RESP) ? BCM2711_DMA40_WAIT_RESP : 0) | - ((info & BCM2835_DMA_S_DREQ) ? -- (BCM2838_DMA40_S_DREQ | BCM2838_DMA40_WAIT_RD_RESP) : 0) | -- ((info & BCM2835_DMA_D_DREQ) ? BCM2838_DMA40_D_DREQ : 0) | -- BCM2838_DMA40_PER_MAP((info >> 16) & 0x1f); -+ (BCM2711_DMA40_S_DREQ | BCM2711_DMA40_WAIT_RD_RESP) : 0) | -+ ((info & BCM2835_DMA_D_DREQ) ? BCM2711_DMA40_D_DREQ : 0) | -+ BCM2711_DMA40_PER_MAP((info >> 16) & 0x1f); - } - --static inline uint32_t to_bcm2838_srci(uint32_t info) -+static inline uint32_t to_bcm2711_srci(uint32_t info) - { -- return ((info & BCM2835_DMA_S_INC) ? BCM2838_DMA40_INC : 0); -+ return ((info & BCM2835_DMA_S_INC) ? BCM2711_DMA40_INC : 0); - } - --static inline uint32_t to_bcm2838_dsti(uint32_t info) -+static inline uint32_t to_bcm2711_dsti(uint32_t info) - { -- return ((info & BCM2835_DMA_D_INC) ? BCM2838_DMA40_INC : 0); -+ return ((info & BCM2835_DMA_D_INC) ? BCM2711_DMA40_INC : 0); - } - --static inline uint32_t to_bcm2838_cbaddr(dma_addr_t addr) -+static inline uint32_t to_bcm2711_cbaddr(dma_addr_t addr) - { - BUG_ON(addr & 0x1f); - return (addr >> 5); -@@ -412,12 +412,12 @@ static void bcm2835_dma_create_cb_set_le - } - - if (c->is_40bit_channel) { -- struct bcm2838_dma40_scb *scb = -- (struct bcm2838_dma40_scb *)control_block; -+ struct bcm2711_dma40_scb *scb = -+ (struct bcm2711_dma40_scb *)control_block; - - scb->len = cb_len; - /* add extrainfo bits to ti */ -- scb->ti |= to_bcm2838_ti(finalextrainfo); -+ scb->ti |= to_bcm2711_ti(finalextrainfo); - } else { - control_block->length = cb_len; - /* add extrainfo bits to info */ -@@ -500,13 +500,13 @@ static struct bcm2835_desc *bcm2835_dma_ - /* fill in the control block */ - control_block = cb_entry->cb; - if (c->is_40bit_channel) { -- struct bcm2838_dma40_scb *scb = -- (struct bcm2838_dma40_scb *)control_block; -- scb->ti = to_bcm2838_ti(info); -+ struct bcm2711_dma40_scb *scb = -+ (struct bcm2711_dma40_scb *)control_block; -+ scb->ti = to_bcm2711_ti(info); - scb->src = lower_32_bits(src); -- scb->srci= upper_32_bits(src) | to_bcm2838_srci(info); -+ scb->srci= upper_32_bits(src) | to_bcm2711_srci(info); - scb->dst = lower_32_bits(dst); -- scb->dsti = upper_32_bits(dst) | to_bcm2838_dsti(info); -+ scb->dsti = upper_32_bits(dst) | to_bcm2711_dsti(info); - scb->next_cb = 0; - } else { - control_block->info = info; -@@ -531,7 +531,7 @@ static struct bcm2835_desc *bcm2835_dma_ - /* link this the last controlblock */ - if (frame && c->is_40bit_channel) - d->cb_list[frame - 1].cb->next = -- to_bcm2838_cbaddr(cb_entry->paddr); -+ to_bcm2711_cbaddr(cb_entry->paddr); - if (frame && !c->is_40bit_channel) - d->cb_list[frame - 1].cb->next = cb_entry->paddr; - -@@ -547,10 +547,10 @@ static struct bcm2835_desc *bcm2835_dma_ - - /* the last frame requires extra flags */ - if (c->is_40bit_channel) { -- struct bcm2838_dma40_scb *scb = -- (struct bcm2838_dma40_scb *)d->cb_list[d->frames-1].cb; -+ struct bcm2711_dma40_scb *scb = -+ (struct bcm2711_dma40_scb *)d->cb_list[d->frames-1].cb; - -- scb->ti |= to_bcm2838_ti(finalextrainfo); -+ scb->ti |= to_bcm2711_ti(finalextrainfo); - } else { - d->cb_list[d->frames - 1].cb->info |= finalextrainfo; - } -@@ -581,18 +581,18 @@ static void bcm2835_dma_fill_cb_chain_wi - max_len = bcm2835_dma_max_frame_length(c); - for_each_sg(sgl, sgent, sg_len, i) { - if (c->is_40bit_channel) { -- struct bcm2838_dma40_scb *scb = -- (struct bcm2838_dma40_scb *)cb->cb; -+ struct bcm2711_dma40_scb *scb = -+ (struct bcm2711_dma40_scb *)cb->cb; - for (addr = sg_dma_address(sgent), - len = sg_dma_len(sgent); - len > 0; - addr += scb->len, len -= scb->len, scb++) { - if (direction == DMA_DEV_TO_MEM) { - scb->dst = lower_32_bits(addr); -- scb->dsti = upper_32_bits(addr) | BCM2838_DMA40_INC; -+ scb->dsti = upper_32_bits(addr) | BCM2711_DMA40_INC; - } else { - scb->src = lower_32_bits(addr); -- scb->srci = upper_32_bits(addr) | BCM2838_DMA40_INC; -+ scb->srci = upper_32_bits(addr) | BCM2711_DMA40_INC; - } - scb->len = min(len, max_len); - } -@@ -619,7 +619,7 @@ static void bcm2835_dma_abort(struct bcm - u32 wait_mask = BCM2835_DMA_WAITING_FOR_WRITES; - - if (c->is_40bit_channel) -- wait_mask = BCM2838_DMA40_WAITING_FOR_WRITES; -+ wait_mask = BCM2711_DMA40_WAITING_FOR_WRITES; - - /* - * A zero control block address means the channel is idle. -@@ -658,10 +658,10 @@ static void bcm2835_dma_start_desc(struc - c->desc = d = to_bcm2835_dma_desc(&vd->tx); - - if (c->is_40bit_channel) { -- writel(to_bcm2838_cbaddr(d->cb_list[0].paddr), -- c->chan_base + BCM2838_DMA40_CB); -- writel(BCM2838_DMA40_ACTIVE | BCM2838_DMA40_CS_FLAGS(c->dreq), -- c->chan_base + BCM2838_DMA40_CS); -+ writel(to_bcm2711_cbaddr(d->cb_list[0].paddr), -+ c->chan_base + BCM2711_DMA40_CB); -+ writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_CS_FLAGS(c->dreq), -+ c->chan_base + BCM2711_DMA40_CS); - } else { - writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); - writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), -@@ -694,7 +694,7 @@ static irqreturn_t bcm2835_dma_callback( - * will remain idle despite the ACTIVE flag being set. - */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | -- (c->is_40bit_channel ? BCM2838_DMA40_CS_FLAGS(c->dreq) : -+ (c->is_40bit_channel ? BCM2711_DMA40_CS_FLAGS(c->dreq) : - BCM2835_DMA_CS_FLAGS(c->dreq)), - c->chan_base + BCM2835_DMA_CS); - -@@ -799,14 +799,14 @@ static enum dma_status bcm2835_dma_tx_st - dma_addr_t pos; - - if (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel) -- pos = readl(c->chan_base + BCM2838_DMA40_SRC) + -- ((readl(c->chan_base + BCM2838_DMA40_SRCI) & -+ pos = readl(c->chan_base + BCM2711_DMA40_SRC) + -+ ((readl(c->chan_base + BCM2711_DMA40_SRCI) & - 0xff) << 8); - else if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel) - pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); - else if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel) -- pos = readl(c->chan_base + BCM2838_DMA40_DEST) + -- ((readl(c->chan_base + BCM2838_DMA40_DESTI) & -+ pos = readl(c->chan_base + BCM2711_DMA40_DEST) + -+ ((readl(c->chan_base + BCM2711_DMA40_DESTI) & - 0xff) << 8); - else if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel) - pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); -@@ -1007,7 +1007,7 @@ static struct dma_async_tx_descriptor *b - - /* wrap around into a loop */ - d->cb_list[d->frames - 1].cb->next = c->is_40bit_channel ? -- to_bcm2838_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr; -+ to_bcm2711_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr; - - return vchan_tx_prep(&c->vc, &d->vd, flags); - } -@@ -1095,7 +1095,7 @@ static void bcm2835_dma_free(struct bcm2 - DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); - } - --int bcm2838_dma40_memcpy_init(void) -+int bcm2711_dma40_memcpy_init(void) - { - if (!memcpy_parent) - return -EPROBE_DEFER; -@@ -1108,15 +1108,15 @@ int bcm2838_dma40_memcpy_init(void) - - return 0; - } --EXPORT_SYMBOL(bcm2838_dma40_memcpy_init); -+EXPORT_SYMBOL(bcm2711_dma40_memcpy_init); - --void bcm2838_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size) -+void bcm2711_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size) - { -- struct bcm2838_dma40_scb *scb = memcpy_scb; -+ struct bcm2711_dma40_scb *scb = memcpy_scb; - unsigned long flags; - - if (!scb) { -- pr_err("bcm2838_dma40_memcpy not initialised!\n"); -+ pr_err("bcm2711_dma40_memcpy not initialised!\n"); - return; - } - -@@ -1124,29 +1124,29 @@ void bcm2838_dma40_memcpy(dma_addr_t dst - - scb->ti = 0; - scb->src = lower_32_bits(src); -- scb->srci = upper_32_bits(src) | BCM2838_DMA40_MEMCPY_XFER_INFO; -+ scb->srci = upper_32_bits(src) | BCM2711_DMA40_MEMCPY_XFER_INFO; - scb->dst = lower_32_bits(dst); -- scb->dsti = upper_32_bits(dst) | BCM2838_DMA40_MEMCPY_XFER_INFO; -+ scb->dsti = upper_32_bits(dst) | BCM2711_DMA40_MEMCPY_XFER_INFO; - scb->len = size; - scb->next_cb = 0; - -- writel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2838_DMA40_CB); -- writel(BCM2838_DMA40_MEMCPY_FLAGS + BCM2838_DMA40_ACTIVE, -- memcpy_chan + BCM2838_DMA40_CS); -+ writel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2711_DMA40_CB); -+ writel(BCM2711_DMA40_MEMCPY_FLAGS + BCM2711_DMA40_ACTIVE, -+ memcpy_chan + BCM2711_DMA40_CS); - - /* Poll for completion */ -- while (!(readl(memcpy_chan + BCM2838_DMA40_CS) & BCM2838_DMA40_END)) -+ while (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END)) - cpu_relax(); - -- writel(BCM2838_DMA40_END, memcpy_chan + BCM2838_DMA40_CS); -+ writel(BCM2711_DMA40_END, memcpy_chan + BCM2711_DMA40_CS); - - spin_unlock_irqrestore(&memcpy_lock, flags); - } --EXPORT_SYMBOL(bcm2838_dma40_memcpy); -+EXPORT_SYMBOL(bcm2711_dma40_memcpy); - - static const struct of_device_id bcm2835_dma_of_match[] = { - { .compatible = "brcm,bcm2835-dma", .data = &bcm2835_dma_cfg }, -- { .compatible = "brcm,bcm2838-dma", .data = &bcm2838_dma_cfg }, -+ { .compatible = "brcm,bcm2711-dma", .data = &bcm2711_dma_cfg }, - {}, - }; - MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); -@@ -1274,9 +1274,9 @@ static int bcm2835_dma_probe(struct plat - - /* And possibly one for the 40-bit DMA memcpy API */ - if (chans_available & od->cfg_data->chan_40bit_mask & -- BIT(BCM2838_DMA_MEMCPY_CHAN)) { -+ BIT(BCM2711_DMA_MEMCPY_CHAN)) { - memcpy_parent = od; -- memcpy_chan = BCM2835_DMA_CHANIO(base, BCM2838_DMA_MEMCPY_CHAN); -+ memcpy_chan = BCM2835_DMA_CHANIO(base, BCM2711_DMA_MEMCPY_CHAN); - memcpy_scb = dma_alloc_coherent(memcpy_parent->ddev.dev, - sizeof(*memcpy_scb), - &memcpy_scb_dma, GFP_KERNEL); -@@ -1284,7 +1284,7 @@ static int bcm2835_dma_probe(struct plat - dev_warn(&pdev->dev, - "Failed to allocated memcpy scb\n"); - -- chans_available &= ~BIT(BCM2838_DMA_MEMCPY_CHAN); -+ chans_available &= ~BIT(BCM2711_DMA_MEMCPY_CHAN); - } - - /* get irqs for each channel that we support */ |