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Diffstat (limited to 'target/linux/bcm27xx/patches-5.15/950-0745-overlays-Overlays-for-WaveShare-2-Chan-CAN-FD-HAT.patch')
-rw-r--r--target/linux/bcm27xx/patches-5.15/950-0745-overlays-Overlays-for-WaveShare-2-Chan-CAN-FD-HAT.patch321
1 files changed, 321 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.15/950-0745-overlays-Overlays-for-WaveShare-2-Chan-CAN-FD-HAT.patch b/target/linux/bcm27xx/patches-5.15/950-0745-overlays-Overlays-for-WaveShare-2-Chan-CAN-FD-HAT.patch
new file mode 100644
index 0000000000..4697be295e
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.15/950-0745-overlays-Overlays-for-WaveShare-2-Chan-CAN-FD-HAT.patch
@@ -0,0 +1,321 @@
+From dadc749c5ccc320127871d7c3ace51a7fae479a7 Mon Sep 17 00:00:00 2001
+From: nmbath <mark@baggywrinkle.co.uk>
+Date: Thu, 24 Feb 2022 13:10:01 +0000
+Subject: [PATCH] overlays: Overlays for WaveShare 2-Chan CAN FD HAT
+
+This patch adds the overlays for the Waveshare 2-Channel Isolated
+CAN FD Expansion HAT for Raspberry Pi, Multi Protections. This HAT
+is based on the mcp2518fd chip and can be run in two modes
+
+Mode A: can0 on spi0.0 and can1 on spi1.0 (cs = pin 26)
+Mode B: can1 on spi0.0 and can1 in spi0.1
+
+Interupts: can0 pin 25 / can1 pin 16
+
+https://www.waveshare.com/2-ch-can-fd-hat.htm
+
+Overlays generated by:
+Mode A: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false \
+ mcp251xfd-overlay.dts,spi0-0,interrupt=25 \
+ mcp251xfd-overlay.dts,spi1-0,interrupt=16
+
+Mode B: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 \
+ mcp251xfd-overlay.dts,spi0-1,interrupt=16
+---
+ arch/arm/boot/dts/overlays/Makefile | 2 +
+ arch/arm/boot/dts/overlays/README | 20 +++
+ .../waveshare-can-fd-hat-mode-a-overlay.dts | 140 ++++++++++++++++++
+ .../waveshare-can-fd-hat-mode-b-overlay.dts | 103 +++++++++++++
+ 4 files changed, 265 insertions(+)
+ create mode 100644 arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts
+ create mode 100644 arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts
+
+--- a/arch/arm/boot/dts/overlays/Makefile
++++ b/arch/arm/boot/dts/overlays/Makefile
+@@ -251,6 +251,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
+ w1-gpio.dtbo \
+ w1-gpio-pullup.dtbo \
+ w5500.dtbo \
++ waveshare-can-fd-hat-mode-a.dtbo \
++ waveshare-can-fd-hat-mode-b.dtbo \
+ wittypi.dtbo \
+ wm8960-soundcard.dtbo
+
+--- a/arch/arm/boot/dts/overlays/README
++++ b/arch/arm/boot/dts/overlays/README
+@@ -3879,6 +3879,26 @@ Params: int_pin GPIO use
+ cs SPI bus Chip Select (default 0)
+
+
++Name: waveshare-can-fd-hat-mode-a
++Info: Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT
++ for Raspberry Pi, Multi Protections. Use this overlay when the
++ HAT is configured in Mode A (Default), with can0 on spi0.0
++ and can1 on spi1.0.
++ https://www.waveshare.com/2-ch-can-fd-hat.htm
++Load: dtoverlay=waveshare-can-fd-hat-mode-a
++Params: <None>
++
++
++Name: waveshare-can-fd-hat-mode-b
++Info: Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT
++ for Raspberry Pi, Multi Protections. Use this overlay when the
++ HAT is configured in Mode B (requires hardware modification), with
++ can0 on spi0.0 and can1 on spi0.1.
++ https://www.waveshare.com/2-ch-can-fd-hat.htm
++Load: dtoverlay=waveshare-can-fd-hat-mode-b
++Params: <None>
++
++
+ Name: wittypi
+ Info: Configures the wittypi RTC module.
+ Load: dtoverlay=wittypi,<param>=<val>
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts
+@@ -0,0 +1,140 @@
++// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=16
++
++// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm
++// in "Mode A" (default) configuration
++// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT
++
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/pinctrl/bcm2835.h>
++
++/ {
++ compatible = "brcm,bcm2835";
++ fragment@0 {
++ target = <&gpio>;
++ __overlay__ {
++ spi1_pins: spi1_pins {
++ brcm,pins = <19 20 21>;
++ brcm,function = <3>;
++ };
++ spi1_cs_pins: spi1_cs_pins {
++ brcm,pins = <26>;
++ brcm,function = <1>;
++ };
++ };
++ };
++ fragment@1 {
++ target = <&spi1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
++ cs-gpios = <&gpio 26 1>;
++ status = "okay";
++ spidev@0 {
++ compatible = "spidev";
++ reg = <0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi-max-frequency = <125000000>;
++ status = "disabled";
++ };
++ };
++ };
++ fragment@2 {
++ target = <&aux>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++ fragment@3 {
++ target = <&spidev0>;
++ __overlay__ {
++ status = "disabled";
++ };
++ };
++ fragment@4 {
++ target = <&gpio>;
++ __overlay__ {
++ mcp251xfd_pins: mcp251xfd_spi0_0_pins {
++ brcm,pins = <25>;
++ brcm,function = <BCM2835_FSEL_GPIO_IN>;
++ };
++ };
++ };
++ fragment@5 {
++ target-path = "/clocks";
++ __overlay__ {
++ clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <40000000>;
++ };
++ };
++ };
++ fragment@6 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mcp251xfd@0 {
++ compatible = "microchip,mcp251xfd";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&mcp251xfd_pins>;
++ spi-max-frequency = <20000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&clk_mcp251xfd_osc>;
++ };
++ };
++ };
++ fragment@7 {
++ target-path = "spi1/spidev@0";
++ __overlay__ {
++ status = "disabled";
++ };
++ };
++ fragment@8 {
++ target = <&gpio>;
++ __overlay__ {
++ mcp251xfd_pins_1: mcp251xfd_spi1_0_pins {
++ brcm,pins = <16>;
++ brcm,function = <BCM2835_FSEL_GPIO_IN>;
++ };
++ };
++ };
++ fragment@9 {
++ target-path = "/clocks";
++ __overlay__ {
++ clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <40000000>;
++ };
++ };
++ };
++ fragment@10 {
++ target = <&spi1>;
++ __overlay__ {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mcp251xfd@0 {
++ compatible = "microchip,mcp251xfd";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&mcp251xfd_pins_1>;
++ spi-max-frequency = <20000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&clk_mcp251xfd_osc_1>;
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts
+@@ -0,0 +1,103 @@
++// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=16
++
++// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm
++// in "Mode B" (requried hardware modification) configuration
++// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT
++
++
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/pinctrl/bcm2835.h>
++
++/ {
++ compatible = "brcm,bcm2835";
++ fragment@0 {
++ target = <&spidev0>;
++ __overlay__ {
++ status = "disabled";
++ };
++ };
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ mcp251xfd_pins: mcp251xfd_spi0_0_pins {
++ brcm,pins = <25>;
++ brcm,function = <BCM2835_FSEL_GPIO_IN>;
++ };
++ };
++ };
++ fragment@2 {
++ target-path = "/clocks";
++ __overlay__ {
++ clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <40000000>;
++ };
++ };
++ };
++ fragment@3 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mcp251xfd@0 {
++ compatible = "microchip,mcp251xfd";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&mcp251xfd_pins>;
++ spi-max-frequency = <20000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&clk_mcp251xfd_osc>;
++ };
++ };
++ };
++ fragment@4 {
++ target = <&spidev1>;
++ __overlay__ {
++ status = "disabled";
++ };
++ };
++ fragment@5 {
++ target = <&gpio>;
++ __overlay__ {
++ mcp251xfd_pins_1: mcp251xfd_spi0_1_pins {
++ brcm,pins = <16>;
++ brcm,function = <BCM2835_FSEL_GPIO_IN>;
++ };
++ };
++ };
++ fragment@6 {
++ target-path = "/clocks";
++ __overlay__ {
++ clk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <40000000>;
++ };
++ };
++ };
++ fragment@7 {
++ target = <&spi0>;
++ __overlay__ {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mcp251xfd@1 {
++ compatible = "microchip,mcp251xfd";
++ reg = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&mcp251xfd_pins_1>;
++ spi-max-frequency = <20000000>;
++ interrupt-parent = <&gpio>;
++ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&clk_mcp251xfd_osc_1>;
++ };
++ };
++ };
++};
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