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Diffstat (limited to 'target/linux/bcm27xx/patches-5.15/950-0740-drm-vc4-hvs-Fix-frame-count-register-readout.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.15/950-0740-drm-vc4-hvs-Fix-frame-count-register-readout.patch | 114 |
1 files changed, 0 insertions, 114 deletions
diff --git a/target/linux/bcm27xx/patches-5.15/950-0740-drm-vc4-hvs-Fix-frame-count-register-readout.patch b/target/linux/bcm27xx/patches-5.15/950-0740-drm-vc4-hvs-Fix-frame-count-register-readout.patch deleted file mode 100644 index 1e7717af01..0000000000 --- a/target/linux/bcm27xx/patches-5.15/950-0740-drm-vc4-hvs-Fix-frame-count-register-readout.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 77579d5ba35bf6e13f0ed09097c475f178d3c270 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <maxime@cerno.tech> -Date: Thu, 17 Feb 2022 10:55:26 +0100 -Subject: [PATCH] drm/vc4: hvs: Fix frame count register readout - -In order to get the field currently being output, the driver has been -using the display FIFO frame count in the HVS, reading a 6-bit field at -the offset 12 in the DISPSTATx register. - -While that field is indeed at that location for the FIFO 1 and 2, the -one for the FIFO0 is actually in the DISPSTAT1 register, at the offset -18. - -Fixes: e538092cb15c ("drm/vc4: Enable precise vblank timestamping for interlaced modes.") -Signed-off-by: Maxime Ripard <maxime@cerno.tech> ---- - drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- - drivers/gpu/drm/vc4/vc4_drv.h | 1 + - drivers/gpu/drm/vc4/vc4_hvs.c | 23 +++++++++++++++++++++++ - drivers/gpu/drm/vc4/vc4_regs.h | 12 ++++++++++-- - 4 files changed, 35 insertions(+), 3 deletions(-) - ---- a/drivers/gpu/drm/vc4/vc4_crtc.c -+++ b/drivers/gpu/drm/vc4/vc4_crtc.c -@@ -123,7 +123,7 @@ static bool vc4_crtc_get_scanout_positio - *vpos /= 2; - - /* Use hpos to correct for field offset in interlaced mode. */ -- if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) -+ if (vc4_hvs_get_fifo_frame_count(dev, vc4_crtc_state->assigned_channel) % 2) - *hpos += mode->crtc_htotal / 2; - } - ---- a/drivers/gpu/drm/vc4/vc4_drv.h -+++ b/drivers/gpu/drm/vc4/vc4_drv.h -@@ -967,6 +967,7 @@ void vc4_irq_reset(struct drm_device *de - extern struct platform_driver vc4_hvs_driver; - void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output); - int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output); -+u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo); - int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state); - void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state); - void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state); ---- a/drivers/gpu/drm/vc4/vc4_hvs.c -+++ b/drivers/gpu/drm/vc4/vc4_hvs.c -@@ -388,6 +388,29 @@ static void vc5_hvs_update_gamma_lut(str - vc5_hvs_lut_load(crtc); - } - -+u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo) -+{ -+ struct vc4_dev *vc4 = to_vc4_dev(dev); -+ u8 field = 0; -+ -+ switch (fifo) { -+ case 0: -+ field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), -+ SCALER_DISPSTAT1_FRCNT0); -+ break; -+ case 1: -+ field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), -+ SCALER_DISPSTAT1_FRCNT1); -+ break; -+ case 2: -+ field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), -+ SCALER_DISPSTAT2_FRCNT2); -+ break; -+ } -+ -+ return field; -+} -+ - int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output) - { - struct vc4_dev *vc4 = to_vc4_dev(dev); ---- a/drivers/gpu/drm/vc4/vc4_regs.h -+++ b/drivers/gpu/drm/vc4/vc4_regs.h -@@ -379,8 +379,6 @@ - # define SCALER_DISPSTATX_MODE_EOF 3 - # define SCALER_DISPSTATX_FULL BIT(29) - # define SCALER_DISPSTATX_EMPTY BIT(28) --# define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12) --# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 - # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) - # define SCALER_DISPSTATX_LINE_SHIFT 0 - -@@ -403,9 +401,15 @@ - (x) * (SCALER_DISPBKGND1 - \ - SCALER_DISPBKGND0)) - #define SCALER_DISPSTAT1 0x00000058 -+# define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18) -+# define SCALER_DISPSTAT1_FRCNT0_SHIFT 18 -+# define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12) -+# define SCALER_DISPSTAT1_FRCNT1_SHIFT 12 -+ - #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ - (x) * (SCALER_DISPSTAT1 - \ - SCALER_DISPSTAT0)) -+ - #define SCALER_DISPBASE1 0x0000005c - #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ - (x) * (SCALER_DISPBASE1 - \ -@@ -415,7 +419,11 @@ - (x) * (SCALER_DISPCTRL1 - \ - SCALER_DISPCTRL0)) - #define SCALER_DISPBKGND2 0x00000064 -+ - #define SCALER_DISPSTAT2 0x00000068 -+# define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12) -+# define SCALER_DISPSTAT2_FRCNT2_SHIFT 12 -+ - #define SCALER_DISPBASE2 0x0000006c - #define SCALER_DISPALPHA2 0x00000070 - #define SCALER_GAMADDR 0x00000078 |