1 files changed, 0 insertions, 83 deletions
diff --git a/target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch b/target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch
deleted file mode 100644
index 62a4ea3d37..0000000000
--- a/target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 5afb722d255335954c6b67470e0d261ea5d5ab7a Mon Sep 17 00:00:00 2001
-From: kFYatek <4499762+kFYatek@users.noreply.github.com>
-Date: Wed, 23 Jun 2021 01:11:26 +0200
-Subject: [PATCH] drm/vc4: Fix timings for interlaced modes
-
-Increase the number of post-sync blanking lines on odd fields instead of
-decreasing it on even fields. This makes the total number of lines
-properly match the modelines.
-
-Additionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take
-pixels_per_clock into account, causing some displays to invert the
-fields when driven by bcm2711.
-
-Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
----
- drivers/gpu/drm/vc4/vc4_crtc.c |  7 ++++---
- drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++------
- 2 files changed, 10 insertions(+), 9 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -342,7 +342,8 @@ static void vc4_crtc_config_pv(struct dr
- 				 PV_HORZB_HACTIVE));
- 
- 	CRTC_WRITE(PV_VERTA,
--		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-+		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-+				 interlace,
- 				 PV_VERTA_VBP) |
- 		   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
- 				 PV_VERTA_VSYNC));
-@@ -354,7 +355,7 @@ static void vc4_crtc_config_pv(struct dr
- 	if (interlace) {
- 		CRTC_WRITE(PV_VERTA_EVEN,
- 			   VC4_SET_FIELD(mode->crtc_vtotal -
--					 mode->crtc_vsync_end - 1,
-+					 mode->crtc_vsync_end,
- 					 PV_VERTA_VBP) |
- 			   VC4_SET_FIELD(mode->crtc_vsync_end -
- 					 mode->crtc_vsync_start,
-@@ -374,7 +375,7 @@ static void vc4_crtc_config_pv(struct dr
- 			   PV_VCONTROL_CONTINUOUS |
- 			   (is_dsi ? PV_VCONTROL_DSI : 0) |
- 			   PV_VCONTROL_INTERLACE |
--			   VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
-+			   VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
- 					 PV_VCONTROL_ODD_DELAY));
- 		CRTC_WRITE(PV_VSYNCD_EVEN, 0);
- 	} else {
---- a/drivers/gpu/drm/vc4/vc4_hdmi.c
-+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -736,12 +736,12 @@ static void vc4_hdmi_set_timings(struct
- 				   VC4_HDMI_VERTA_VFP) |
- 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
- 	u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
--		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-+		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-+				   interlaced,
- 				   VC4_HDMI_VERTB_VBP));
- 	u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
- 			  VC4_SET_FIELD(mode->crtc_vtotal -
--					mode->crtc_vsync_end -
--					interlaced,
-+					mode->crtc_vsync_end,
- 					VC4_HDMI_VERTB_VBP));
- 
- 	HDMI_WRITE(HDMI_HORZA,
-@@ -782,12 +782,12 @@ static void vc5_hdmi_set_timings(struct
- 				   VC5_HDMI_VERTA_VFP) |
- 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
- 	u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
--		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-+		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-+				   interlaced,
- 				   VC4_HDMI_VERTB_VBP));
- 	u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
- 			  VC4_SET_FIELD(mode->crtc_vtotal -
--					mode->crtc_vsync_end -
--					interlaced,
-+					mode->crtc_vsync_end,
- 					VC4_HDMI_VERTB_VBP));
- 	unsigned char gcp;
- 	bool gcp_en;