diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch b/target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch new file mode 100644 index 0000000000..455042783a --- /dev/null +++ b/target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch @@ -0,0 +1,42 @@ +From 9f7c0728efb0036f6f197126aa62da40cdf4713a Mon Sep 17 00:00:00 2001 +From: Dave Stevenson <dave.stevenson@raspberrypi.com> +Date: Wed, 28 Apr 2021 16:14:21 +0100 +Subject: [PATCH] drm/vc4: Allow DBLCLK modes even if horz timing is + odd. + +The 2711 pixel valve can't produce odd horizontal timings, and +checks were added to vc4_hdmi_encoder_atomic_check and +vc4_hdmi_encoder_mode_valid to filter out/block selection of +such modes. + +Modes with DRM_MODE_FLAG_DBLCLK double all the horizontal timing +values before programming them into the PV. The PV values, +therefore, can not be odd, and so the modes can be supported. + +Amend the filtering appropriately. + +See https://github.com/raspberrypi/linux/issues/4307 + +Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> +--- + drivers/gpu/drm/vc4/vc4_hdmi.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/vc4/vc4_hdmi.c ++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c +@@ -1066,6 +1066,7 @@ static int vc4_hdmi_encoder_atomic_check + unsigned long long tmds_rate; + + if (vc4_hdmi->variant->unsupported_odd_h_timings && ++ !(mode->flags & DRM_MODE_FLAG_DBLCLK) && + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || + (mode->hsync_end % 2) || (mode->htotal % 2))) + return -EINVAL; +@@ -1110,6 +1111,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e + struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); + + if (vc4_hdmi->variant->unsupported_odd_h_timings && ++ !(mode->flags & DRM_MODE_FLAG_DBLCLK) && + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || + (mode->hsync_end % 2) || (mode->htotal % 2))) + return MODE_H_ILLEGAL; |