diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch b/target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch new file mode 100644 index 0000000000..a94405150a --- /dev/null +++ b/target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch @@ -0,0 +1,27 @@ +From 59938610a705283fef63447c7e777781358610e2 Mon Sep 17 00:00:00 2001 +From: Dave Stevenson <dave.stevenson@raspberrypi.com> +Date: Thu, 11 Feb 2021 18:37:04 +0000 +Subject: [PATCH] drm/vc4: Correct pixel order for DSI0 + +For slightly unknown reasons, dsi0 takes a different pixel format +to dsi1, and that has to be set in the pixel valve. + +Amend the setup accordingly. + +Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> +--- + drivers/gpu/drm/vc4/vc4_crtc.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/vc4/vc4_crtc.c ++++ b/drivers/gpu/drm/vc4/vc4_crtc.c +@@ -319,7 +319,8 @@ static void vc4_crtc_config_pv(struct dr + u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; + bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || + vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); +- u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; ++ bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1; ++ u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; + u8 ppc = pv_data->pixels_per_clock; + bool debug_dump_regs = false; + |