diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch b/target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch new file mode 100644 index 0000000000..f8a2a69354 --- /dev/null +++ b/target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch @@ -0,0 +1,34 @@ +From 264515dcb2a318072530a2171c084dc207006399 Mon Sep 17 00:00:00 2001 +From: Dave Stevenson <dave.stevenson@raspberrypi.com> +Date: Mon, 30 Nov 2020 16:16:03 +0000 +Subject: [PATCH] drm/vc4: Correct DSI register definition + +The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register +definitions were swapped, so trying to use more than a single data +lane failed as lane 1 would get powered down. +(In theory a 4 lane device would work as all lanes would remain +powered). + +Correct the definitions. + +Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> +--- + drivers/gpu/drm/vc4/vc4_dsi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/vc4/vc4_dsi.c ++++ b/drivers/gpu/drm/vc4/vc4_dsi.c +@@ -306,11 +306,11 @@ + # define DSI0_PHY_AFEC0_RESET BIT(11) + # define DSI1_PHY_AFEC0_PD_BG BIT(11) + # define DSI0_PHY_AFEC0_PD BIT(10) +-# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10) ++# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10) + # define DSI0_PHY_AFEC0_PD_BG BIT(9) + # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) + # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) +-# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8) ++# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8) + # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) + # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 + # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) |