diff options
Diffstat (limited to 'target/linux/atheros/patches-3.14/105-ar2315_pci.patch')
| -rw-r--r-- | target/linux/atheros/patches-3.14/105-ar2315_pci.patch | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/target/linux/atheros/patches-3.14/105-ar2315_pci.patch b/target/linux/atheros/patches-3.14/105-ar2315_pci.patch index 0ce670febf..53222a1af2 100644 --- a/target/linux/atheros/patches-3.14/105-ar2315_pci.patch +++ b/target/linux/atheros/patches-3.14/105-ar2315_pci.patch @@ -61,7 +61,7 @@ + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); + mb(); + -+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; ++ addr = (u32)configspace + (1 << (13 + dev)) + (func << 8) + where; + if (size == 1) + addr ^= 0x3; + else if (size == 2) @@ -189,10 +189,10 @@ + return -ENODEV; + + /* Remap PCI config space */ -+ configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, -+ 1*1024*1024); ++ configspace = (unsigned long)ioremap_nocache(AR2315_PCIEXT, ++ 1 * 1024 * 1024); + ar231x_pci_controller.io_map_base = -+ (unsigned long) ioremap_nocache(AR2315_MEM_BASE + ++ (unsigned long)ioremap_nocache(AR2315_MEM_BASE + + AR2315_MEM_SIZE, AR2315_IO_SIZE); + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/ + @@ -204,29 +204,29 @@ + msleep(20); + + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, -+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); ++ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); + + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | -+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, -+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | -+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); ++ AR2315_IF_PCI | AR2315_IF_PCI_HOST | ++ AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK << ++ AR2315_IF_PCI_CLK_SHIFT)); + + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_LOW); ++ AR2315_PCIRST_LOW); + msleep(100); + + /* Bring the PCI out of reset */ + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); ++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); + + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, -+ 0x1E | /* 1GB uncached */ -+ (1 << 5) | /* Enable uncached */ -+ (0x2 << 30) /* Base: 0x80000000 */ -+ ); ++ 0x1E | /* 1GB uncached */ ++ (1 << 5) | /* Enable uncached */ ++ (0x2 << 30) /* Base: 0x80000000 */); + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); + + msleep(500); |