aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch')
-rw-r--r--target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch54
1 files changed, 0 insertions, 54 deletions
diff --git a/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch b/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch
deleted file mode 100644
index 6530344ce3..0000000000
--- a/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:27:28 +0100
-Subject: [PATCH] MIPS: ath79: export switch MDIO reference clock
-
-On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
-clock. If that feature is not used, it defaults to the main reference clock,
-like on all other SoC.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -41,6 +41,7 @@ static const char * const clk_names[ATH7
- [ATH79_CLK_DDR] = "ddr",
- [ATH79_CLK_AHB] = "ahb",
- [ATH79_CLK_REF] = "ref",
-+ [ATH79_CLK_MDIO] = "mdio",
- };
-
- static const char * __init ath79_clk_name(int type)
-@@ -341,6 +342,10 @@ static void __init ar934x_clocks_init(vo
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
-+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
-+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
-+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
-+
- iounmap(dpll_base);
- }
-
-@@ -687,6 +692,9 @@ static void __init ath79_clocks_init_dt(
- else if (of_device_is_compatible(np, "qca,qca9560-pll"))
- qca956x_clocks_init(pll_base);
-
-+ if (!clks[ATH79_CLK_MDIO])
-+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
-+
- if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
- pr_err("%pOF: could not register clk provider\n", np);
- goto err_iounmap;
---- a/include/dt-bindings/clock/ath79-clk.h
-+++ b/include/dt-bindings/clock/ath79-clk.h
-@@ -14,7 +14,8 @@
- #define ATH79_CLK_DDR 1
- #define ATH79_CLK_AHB 2
- #define ATH79_CLK_REF 3
-+#define ATH79_CLK_MDIO 4
-
--#define ATH79_CLK_END 4
-+#define ATH79_CLK_END 5
-
- #endif /* __DT_BINDINGS_ATH79_CLK_H */