diff options
Diffstat (limited to 'target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch')
| -rw-r--r-- | target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch | 346 |
1 files changed, 346 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch b/target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch new file mode 100644 index 0000000000..738f239af0 --- /dev/null +++ b/target/linux/ath79/patches-4.14/0025-MIPS-ath79-drop-irq.c.patch @@ -0,0 +1,346 @@ +From 08b9cad7da5d981d595fe6d76e9675f85e23e688 Mon Sep 17 00:00:00 2001 +From: John Crispin <john@phrozen.org> +Date: Tue, 6 Mar 2018 09:57:15 +0100 +Subject: [PATCH 25/27] MIPS: ath79: drop irq.c + +all IRQ init code will flow via OF based irq chips. + +Signed-off-by: John Crispin <john@phrozen.org> +--- + arch/mips/ath79/Makefile | 2 +- + arch/mips/ath79/irq.c | 285 ----------------------------------------------- + arch/mips/ath79/setup.c | 6 + + 3 files changed, 7 insertions(+), 286 deletions(-) + delete mode 100644 arch/mips/ath79/irq.c + +diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile +index 783369bc1c5b..bd0c9b8b1b5b 100644 +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -8,7 +8,7 @@ + # under the terms of the GNU General Public License version 2 as published + # by the Free Software Foundation. + +-obj-y := prom.o setup.o irq.o common.o clock.o ++obj-y := prom.o setup.o common.o clock.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c +deleted file mode 100644 +index 58d17ef6f58f..000000000000 +--- a/arch/mips/ath79/irq.c ++++ /dev/null +@@ -1,285 +0,0 @@ +-/* +- * Atheros AR71xx/AR724x/AR913x specific interrupt handling +- * +- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> +- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> +- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> +- * +- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irqchip.h> +-#include <linux/of_irq.h> +- +-#include <asm/irq_cpu.h> +-#include <asm/mipsregs.h> +- +-#include <asm/mach-ath79/ath79.h> +-#include <asm/mach-ath79/ar71xx_regs.h> +-#include "common.h" +-#include "machtypes.h" +- +- +-static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) +-{ +- u32 status; +- +- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); +- +- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { +- ath79_ddr_wb_flush(3); +- generic_handle_irq(ATH79_IP2_IRQ(0)); +- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { +- ath79_ddr_wb_flush(4); +- generic_handle_irq(ATH79_IP2_IRQ(1)); +- } else { +- spurious_interrupt(); +- } +-} +- +-static void ar934x_ip2_irq_init(void) +-{ +- int i; +- +- for (i = ATH79_IP2_IRQ_BASE; +- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); +- +- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); +-} +- +-static void qca953x_ip2_irq_dispatch(struct irq_desc *desc) +-{ +- u32 status; +- +- status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); +- +- if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { +- ath79_ddr_wb_flush(3); +- generic_handle_irq(ATH79_IP2_IRQ(0)); +- } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { +- ath79_ddr_wb_flush(4); +- generic_handle_irq(ATH79_IP2_IRQ(1)); +- } else { +- spurious_interrupt(); +- } +-} +- +-static void qca953x_irq_init(void) +-{ +- int i; +- +- for (i = ATH79_IP2_IRQ_BASE; +- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); +- +- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); +-} +- +-static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) +-{ +- u32 status; +- +- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); +- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; +- +- if (status == 0) { +- spurious_interrupt(); +- return; +- } +- +- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP2_IRQ(0)); +- } +- +- if (status & QCA955X_EXT_INT_WMAC_ALL) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP2_IRQ(1)); +- } +-} +- +-static void qca955x_ip3_irq_dispatch(struct irq_desc *desc) +-{ +- u32 status; +- +- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); +- status &= QCA955X_EXT_INT_PCIE_RC2_ALL | +- QCA955X_EXT_INT_USB1 | +- QCA955X_EXT_INT_USB2; +- +- if (status == 0) { +- spurious_interrupt(); +- return; +- } +- +- if (status & QCA955X_EXT_INT_USB1) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP3_IRQ(0)); +- } +- +- if (status & QCA955X_EXT_INT_USB2) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP3_IRQ(1)); +- } +- +- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP3_IRQ(2)); +- } +-} +- +-static void qca955x_irq_init(void) +-{ +- int i; +- +- for (i = ATH79_IP2_IRQ_BASE; +- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); +- +- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); +- +- for (i = ATH79_IP3_IRQ_BASE; +- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); +- +- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); +-} +- +-static void qca956x_ip2_irq_dispatch(struct irq_desc *desc) +-{ +- u32 status; +- +- status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); +- status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL; +- +- if (status == 0) { +- spurious_interrupt(); +- return; +- } +- +- if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP2_IRQ(0)); +- } +- +- if (status & QCA956X_EXT_INT_WMAC_ALL) { +- /* TODO: flsuh DDR? */ +- generic_handle_irq(ATH79_IP2_IRQ(1)); +- } +-} +- +-static void qca956x_ip3_irq_dispatch(struct irq_desc *desc) +-{ +- u32 status; +- +- status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); +- status &= QCA956X_EXT_INT_PCIE_RC2_ALL | +- QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2; +- +- if (status == 0) { +- spurious_interrupt(); +- return; +- } +- +- if (status & QCA956X_EXT_INT_USB1) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP3_IRQ(0)); +- } +- +- if (status & QCA956X_EXT_INT_USB2) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP3_IRQ(1)); +- } +- +- if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) { +- /* TODO: flush DDR? */ +- generic_handle_irq(ATH79_IP3_IRQ(2)); +- } +-} +- +-static void qca956x_enable_timer_cb(void) { +- u32 misc; +- +- misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); +- misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; +- ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); +-} +- +-static void qca956x_irq_init(void) +-{ +- int i; +- +- for (i = ATH79_IP2_IRQ_BASE; +- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); +- +- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); +- +- for (i = ATH79_IP3_IRQ_BASE; +- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); +- +- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); +- +- /* QCA956x timer init workaround has to be applied right before setting +- * up the clock. Else, there will be no jiffies */ +- late_time_init = &qca956x_enable_timer_cb; +-} +- +-void __init arch_init_irq(void) +-{ +- unsigned irq_wb_chan2 = -1; +- unsigned irq_wb_chan3 = -1; +- bool misc_is_ar71xx; +- +- if (mips_machtype == ATH79_MACH_GENERIC_OF) { +- irqchip_init(); +- return; +- } +- +- if (soc_is_ar71xx() || soc_is_ar724x() || +- soc_is_ar913x() || soc_is_ar933x()) { +- irq_wb_chan2 = 3; +- irq_wb_chan3 = 2; +- } else if (soc_is_ar934x() || soc_is_qca953x()) { +- irq_wb_chan3 = 2; +- } +- +- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3); +- +- if (soc_is_ar71xx() || soc_is_ar913x()) +- misc_is_ar71xx = true; +- else if (soc_is_ar724x() || +- soc_is_ar933x() || +- soc_is_ar934x() || +- soc_is_qca953x() || +- soc_is_qca955x() || +- soc_is_qca956x() || +- soc_is_tp9343()) +- misc_is_ar71xx = false; +- else +- BUG(); +- ath79_misc_irq_init( +- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS, +- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx); +- +- if (soc_is_ar934x()) +- ar934x_ip2_irq_init(); +- else if (soc_is_qca953x()) +- qca953x_irq_init(); +- else if (soc_is_qca955x()) +- qca955x_irq_init(); +- else if (soc_is_qca956x() || soc_is_tp9343()) +- qca956x_irq_init(); +-} +diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c +index 8d7ffa2e8265..7b089c07d2fa 100644 +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -19,6 +19,7 @@ + #include <linux/clk.h> + #include <linux/clk-provider.h> + #include <linux/of_fdt.h> ++#include <linux/irqchip.h> + + #include <asm/bootinfo.h> + #include <asm/idle.h> +@@ -310,6 +311,11 @@ void __init plat_time_init(void) + mips_hpt_frequency = cpu_clk_rate / 2; + } + ++void __init arch_init_irq(void) ++{ ++ irqchip_init(); ++} ++ + static int __init ath79_setup(void) + { + if (mips_machtype == ATH79_MACH_GENERIC_OF) +-- +2.11.0 + |