aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts')
-rw-r--r--target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts168
1 files changed, 168 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
new file mode 100644
index 0000000000..59344917ad
--- /dev/null
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca953x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ compatible = "glinet,gl-xe300", "qca,qca9531";
+ model = "GL.iNet GL-XE300";
+
+ gpio-export {
+ compatible = "gpio-export";
+
+ gpio_lte_power {
+ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+ gpio-export,name = "lte_power";
+ gpio-export,output = <1>;
+ };
+
+ gpio_sd_detect {
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ gpio-export,name = "sd_detect";
+ gpio-export,output = <0>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&jtag_disable_pins>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ lan {
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ label = "green:lan";
+ };
+
+ wan {
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ label = "green:wan";
+ };
+
+ wlan {
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ label = "green:wlan";
+ linux,default-trigger = "phy0tpt";
+ };
+
+ lte {
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ label = "green:lte";
+ };
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x10000>;
+ };
+
+ art: partition@50000 {
+ label = "art";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "kernel";
+ reg = <0x60000 0x400000>;
+ };
+
+ partition@460000 {
+ label = "nor_reserved";
+ reg = <0x460000 0xba0000>;
+ };
+ };
+ };
+
+ flash@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <25000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ubi";
+ reg = <0x0 0x8000000>;
+ };
+ };
+ };
+};
+
+&eth0 {
+ status = "okay";
+
+ phy-handle = <&swphy4>;
+
+ nvmem-cells = <&macaddr_art_0>;
+ nvmem-cell-names = "mac-address";
+ mtd-mac-address-increment = <1>;
+};
+
+&eth1 {
+ nvmem-cells = <&macaddr_art_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&wmac {
+ status = "okay";
+
+ mtd-cal-data = <&art 0x1000>;
+};
+
+&art {
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_art_0: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+};