diff options
Diffstat (limited to 'target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch')
| -rw-r--r-- | target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch b/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch new file mode 100644 index 0000000000..9b59d9521f --- /dev/null +++ b/target/linux/at91/patches-5.15/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch @@ -0,0 +1,85 @@ +From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea <claudiu.beznea@microchip.com> +Date: Wed, 15 Sep 2021 10:48:35 +0300 +Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate + settings for GMACs + +Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain +GMAC's MDIO pins should be configured with slew-rate enabled, while the +data + signaling pins should be configured with slew-rate disabled when +GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets +the slew-rate as enabled for all pins. Adapt the device tree to comply +with these. + +Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") +Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> +Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com +--- + arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------ + 1 file changed, 22 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/at91-sama7g5ek.dts ++++ b/arch/arm/boot/dts/at91-sama7g5ek.dts +@@ -355,7 +355,10 @@ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; ++ pinctrl-0 = <&pinctrl_gmac0_default ++ &pinctrl_gmac0_mdio_default ++ &pinctrl_gmac0_txck_default ++ &pinctrl_gmac0_phy_irq>; + phy-mode = "rgmii-id"; + status = "okay"; + +@@ -370,7 +373,9 @@ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; ++ pinctrl-0 = <&pinctrl_gmac1_default ++ &pinctrl_gmac1_mdio_default ++ &pinctrl_gmac1_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + +@@ -425,14 +430,20 @@ + <PIN_PA15__G0_TXEN>, + <PIN_PA30__G0_RXCK>, + <PIN_PA18__G0_RXDV>, +- <PIN_PA22__G0_MDC>, +- <PIN_PA23__G0_MDIO>, + <PIN_PA25__G0_125CK>; ++ slew-rate = <0>; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac0_mdio_default: gmac0_mdio_default { ++ pinmux = <PIN_PA22__G0_MDC>, ++ <PIN_PA23__G0_MDIO>; + bias-disable; + }; + + pinctrl_gmac0_txck_default: gmac0_txck_default { + pinmux = <PIN_PA24__G0_TXCK>; ++ slew-rate = <0>; + bias-pull-up; + }; + +@@ -449,8 +460,13 @@ + <PIN_PD25__G1_RX0>, + <PIN_PD26__G1_RX1>, + <PIN_PD27__G1_RXER>, +- <PIN_PD24__G1_RXDV>, +- <PIN_PD28__G1_MDC>, ++ <PIN_PD24__G1_RXDV>; ++ slew-rate = <0>; ++ bias-disable; ++ }; ++ ++ pinctrl_gmac1_mdio_default: gmac1_mdio_default { ++ pinmux = <PIN_PD28__G1_MDC>, + <PIN_PD29__G1_MDIO>; + bias-disable; + }; |