diff options
Diffstat (limited to 'target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch')
| -rw-r--r-- | target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch b/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch new file mode 100644 index 0000000000..3828835196 --- /dev/null +++ b/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch @@ -0,0 +1,104 @@ +From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev <eugen.hristev@microchip.com> +Date: Tue, 13 Apr 2021 12:57:15 +0200 +Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for + additional modules + +Add register description for additional pipeline modules: the +Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS) + +Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> +Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> +Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> +--- + drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++ + 1 file changed, 67 insertions(+) + +diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h +index a15c13e1a833..457eed74cda9 100644 +--- a/drivers/media/platform/atmel/atmel-isc-regs.h ++++ b/drivers/media/platform/atmel/atmel-isc-regs.h +@@ -90,6 +90,46 @@ + #define ISC_INT_DDONE BIT(8) + #define ISC_INT_HISDONE BIT(12) + ++/* ISC DPC Control Register */ ++#define ISC_DPC_CTRL 0x40 ++ ++#define ISC_DPC_CTRL_DPCEN BIT(0) ++#define ISC_DPC_CTRL_GDCEN BIT(1) ++#define ISC_DPC_CTRL_BLCEN BIT(2) ++ ++/* ISC DPC Config Register */ ++#define ISC_DPC_CFG 0x44 ++ ++#define ISC_DPC_CFG_BAYSEL_SHIFT 0 ++ ++#define ISC_DPC_CFG_EITPOL BIT(4) ++ ++#define ISC_DPC_CFG_TA_ENABLE BIT(14) ++#define ISC_DPC_CFG_TC_ENABLE BIT(13) ++#define ISC_DPC_CFG_TM_ENABLE BIT(12) ++ ++#define ISC_DPC_CFG_RE_MODE BIT(17) ++ ++#define ISC_DPC_CFG_GDCCLP_SHIFT 20 ++#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) ++ ++#define ISC_DPC_CFG_BLOFF_SHIFT 24 ++#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) ++ ++#define ISC_DPC_CFG_BAYCFG_SHIFT 0 ++#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) ++/* ISC DPC Threshold Median Register */ ++#define ISC_DPC_THRESHM 0x48 ++ ++/* ISC DPC Threshold Closest Register */ ++#define ISC_DPC_THRESHC 0x4C ++ ++/* ISC DPC Threshold Average Register */ ++#define ISC_DPC_THRESHA 0x50 ++ ++/* ISC DPC STatus Register */ ++#define ISC_DPC_SR 0x54 ++ + /* ISC White Balance Control Register */ + #define ISC_WB_CTRL 0x00000058 + +@@ -153,6 +193,33 @@ + /* ISC_Gamma Correction Green Entry Register */ + #define ISC_GAM_RENTRY 0x00000298 + ++/* ISC VHXS Control Register */ ++#define ISC_VHXS_CTRL 0x398 ++ ++/* ISC VHXS Source Size Register */ ++#define ISC_VHXS_SS 0x39C ++ ++/* ISC VHXS Destination Size Register */ ++#define ISC_VHXS_DS 0x3A0 ++ ++/* ISC Vertical Factor Register */ ++#define ISC_VXS_FACT 0x3a4 ++ ++/* ISC Horizontal Factor Register */ ++#define ISC_HXS_FACT 0x3a8 ++ ++/* ISC Vertical Config Register */ ++#define ISC_VXS_CFG 0x3ac ++ ++/* ISC Horizontal Config Register */ ++#define ISC_HXS_CFG 0x3b0 ++ ++/* ISC Vertical Tap Register */ ++#define ISC_VXS_TAP 0x3b4 ++ ++/* ISC Horizontal Tap Register */ ++#define ISC_HXS_TAP 0x434 ++ + /* Offset for CSC register specific to sama5d2 product */ + #define ISC_SAMA5D2_CSC_OFFSET 0 + +-- +2.32.0 + |