diff options
Diffstat (limited to 'target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch')
| -rw-r--r-- | target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch b/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch new file mode 100644 index 0000000000..312e6466cc --- /dev/null +++ b/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch @@ -0,0 +1,46 @@ +From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001 +From: Eugen Hristev <eugen.hristev@microchip.com> +Date: Thu, 19 Nov 2020 17:43:09 +0200 +Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be + exported and referenced in DT + +Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock +from phandle in DT. + +Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> +[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] +Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com +Signed-off-by: Stephen Boyd <sboyd@kernel.org> +--- + drivers/clk/at91/sama7g5.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c +index 7ef7963126b6..d3c3469d47d9 100644 +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -117,7 +117,8 @@ static const struct { + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, }, ++ .c = 1, ++ .eid = PMC_CPUPLL, }, + }, + + [PLL_ID_SYS] = { +@@ -131,7 +132,8 @@ static const struct { + .p = "syspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, +- .c = 1, }, ++ .c = 1, ++ .eid = PMC_SYSPLL, }, + }, + + [PLL_ID_DDR] = { +-- +2.32.0 + |