diff options
Diffstat (limited to 'target/linux/ar71xx')
6 files changed, 222 insertions, 14 deletions
diff --git a/target/linux/ar71xx/patches-3.3/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch b/target/linux/ar71xx/patches-3.3/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch new file mode 100644 index 0000000000..9ffb398ea4 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch @@ -0,0 +1,106 @@ +From 177dc53a07e2c660d1c1a6cec4576c802325e330 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Nov 2012 09:02:01 +0100 +Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs + +GPIO function selection is not working on the AR934x +SoCs because the offset of the function selection +register is different on those. + +Add a helper routine which returns the correct +register address based on the SoC type, and use +that in the 'ath79_gpio_function_*' routines. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/gpio.c | 38 ++++++++++++++++-------- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + 2 files changed, 28 insertions(+), 12 deletions(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip + .base = 0, + }; + ++static void __iomem *ath79_gpio_get_function_reg(void) ++{ ++ u32 reg = 0; ++ ++ if (soc_is_ar71xx() || ++ soc_is_ar724x() || ++ soc_is_ar913x() || ++ soc_is_ar933x()) ++ reg = AR71XX_GPIO_REG_FUNC; ++ else if (soc_is_ar934x()) ++ reg = AR934X_GPIO_REG_FUNC; ++ else ++ BUG(); ++ ++ return ath79_gpio_base + reg; ++} ++ + void ath79_gpio_function_enable(u32 mask) + { +- void __iomem *base = ath79_gpio_base; ++ void __iomem *reg = ath79_gpio_get_function_reg(); + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + +- __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, +- base + AR71XX_GPIO_REG_FUNC); ++ __raw_writel(__raw_readl(reg) | mask, reg); + /* flush write */ +- __raw_readl(base + AR71XX_GPIO_REG_FUNC); ++ __raw_readl(reg); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + + void ath79_gpio_function_disable(u32 mask) + { +- void __iomem *base = ath79_gpio_base; ++ void __iomem *reg = ath79_gpio_get_function_reg(); + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + +- __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, +- base + AR71XX_GPIO_REG_FUNC); ++ __raw_writel(__raw_readl(reg) & ~mask, reg); + /* flush write */ +- __raw_readl(base + AR71XX_GPIO_REG_FUNC); ++ __raw_readl(reg); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + + void ath79_gpio_function_setup(u32 set, u32 clear) + { +- void __iomem *base = ath79_gpio_base; ++ void __iomem *reg = ath79_gpio_get_function_reg(); + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + +- __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, +- base + AR71XX_GPIO_REG_FUNC); ++ __raw_writel((__raw_readl(reg) & ~clear) | set, reg); + /* flush write */ +- __raw_readl(base + AR71XX_GPIO_REG_FUNC); ++ __raw_readl(reg); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -520,6 +520,8 @@ + #define AR71XX_GPIO_REG_INT_ENABLE 0x24 + #define AR71XX_GPIO_REG_FUNC 0x28 + ++#define AR934X_GPIO_REG_FUNC 0x6c ++ + #define AR71XX_GPIO_COUNT 16 + #define AR724X_GPIO_COUNT 18 + #define AR913X_GPIO_COUNT 22 diff --git a/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch index 6b09fc0a9b..86e136f67e 100644 --- a/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch +++ b/target/linux/ar71xx/patches-3.3/505-MIPS-ath79-add-ath79_gpio_function_select.patch @@ -10,7 +10,7 @@ #endif /* __ATH79_COMMON_H */ --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c -@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set, +@@ -198,6 +198,34 @@ void ath79_gpio_function_setup(u32 set, spin_unlock_irqrestore(&ath79_gpio_lock, flags); } diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch index 8a11a70d11..150f0eecb8 100644 --- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch @@ -153,7 +153,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -520,6 +582,14 @@ +@@ -520,6 +582,12 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -163,12 +163,10 @@ +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 -+#define AR934X_GPIO_REG_FUNC 0x6c -+ + #define AR934X_GPIO_REG_FUNC 0x6c + #define AR71XX_GPIO_COUNT 16 - #define AR724X_GPIO_COUNT 18 - #define AR913X_GPIO_COUNT 22 -@@ -548,4 +618,133 @@ +@@ -550,4 +618,133 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 diff --git a/target/linux/ar71xx/patches-3.6/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch b/target/linux/ar71xx/patches-3.6/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch new file mode 100644 index 0000000000..a9845baba8 --- /dev/null +++ b/target/linux/ar71xx/patches-3.6/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch @@ -0,0 +1,106 @@ +From 177dc53a07e2c660d1c1a6cec4576c802325e330 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Wed, 14 Nov 2012 09:02:01 +0100 +Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs + +GPIO function selection is not working on the AR934x +SoCs because the offset of the function selection +register is different on those. + +Add a helper routine which returns the correct +register address based on the SoC type, and use +that in the 'ath79_gpio_function_*' routines. + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +--- + arch/mips/ath79/gpio.c | 38 ++++++++++++++++-------- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + 2 files changed, 28 insertions(+), 12 deletions(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip + .base = 0, + }; + ++static void __iomem *ath79_gpio_get_function_reg(void) ++{ ++ u32 reg = 0; ++ ++ if (soc_is_ar71xx() || ++ soc_is_ar724x() || ++ soc_is_ar913x() || ++ soc_is_ar933x()) ++ reg = AR71XX_GPIO_REG_FUNC; ++ else if (soc_is_ar934x()) ++ reg = AR934X_GPIO_REG_FUNC; ++ else ++ BUG(); ++ ++ return ath79_gpio_base + reg; ++} ++ + void ath79_gpio_function_enable(u32 mask) + { +- void __iomem *base = ath79_gpio_base; ++ void __iomem *reg = ath79_gpio_get_function_reg(); + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + +- __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, +- base + AR71XX_GPIO_REG_FUNC); ++ __raw_writel(__raw_readl(reg) | mask, reg); + /* flush write */ +- __raw_readl(base + AR71XX_GPIO_REG_FUNC); ++ __raw_readl(reg); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + + void ath79_gpio_function_disable(u32 mask) + { +- void __iomem *base = ath79_gpio_base; ++ void __iomem *reg = ath79_gpio_get_function_reg(); + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + +- __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, +- base + AR71XX_GPIO_REG_FUNC); ++ __raw_writel(__raw_readl(reg) & ~mask, reg); + /* flush write */ +- __raw_readl(base + AR71XX_GPIO_REG_FUNC); ++ __raw_readl(reg); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + + void ath79_gpio_function_setup(u32 set, u32 clear) + { +- void __iomem *base = ath79_gpio_base; ++ void __iomem *reg = ath79_gpio_get_function_reg(); + unsigned long flags; + + spin_lock_irqsave(&ath79_gpio_lock, flags); + +- __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set, +- base + AR71XX_GPIO_REG_FUNC); ++ __raw_writel((__raw_readl(reg) & ~clear) | set, reg); + /* flush write */ +- __raw_readl(base + AR71XX_GPIO_REG_FUNC); ++ __raw_readl(reg); + + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -520,6 +520,8 @@ + #define AR71XX_GPIO_REG_INT_ENABLE 0x24 + #define AR71XX_GPIO_REG_FUNC 0x28 + ++#define AR934X_GPIO_REG_FUNC 0x6c ++ + #define AR71XX_GPIO_COUNT 16 + #define AR7240_GPIO_COUNT 18 + #define AR7241_GPIO_COUNT 20 diff --git a/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch index 6b09fc0a9b..86e136f67e 100644 --- a/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch +++ b/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch @@ -10,7 +10,7 @@ #endif /* __ATH79_COMMON_H */ --- a/arch/mips/ath79/gpio.c +++ b/arch/mips/ath79/gpio.c -@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set, +@@ -198,6 +198,34 @@ void ath79_gpio_function_setup(u32 set, spin_unlock_irqrestore(&ath79_gpio_lock, flags); } diff --git a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch index a59d92b6d5..511fc1fd8c 100644 --- a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch @@ -153,7 +153,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -520,6 +582,14 @@ +@@ -520,6 +582,12 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -163,12 +163,10 @@ +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 -+#define AR934X_GPIO_REG_FUNC 0x6c -+ + #define AR934X_GPIO_REG_FUNC 0x6c + #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 -@@ -549,4 +619,133 @@ +@@ -551,4 +619,133 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 |