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-rw-r--r--target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch23
-rw-r--r--target/linux/ar71xx/patches-4.4/910-unaligned_access_hacks.patch10
2 files changed, 5 insertions, 28 deletions
diff --git a/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch b/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch
deleted file mode 100644
index 64fb545b24..0000000000
--- a/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 18 May 2016 18:03:31 +0200
-Subject: [PATCH] MIPS: ath79: fix register address in ath79_ddr_wb_flush()
-
-ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
-need to be a multiple of 4.
-
-Cc: Alban Bedel <albeu@free.fr>
-Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/mips/ath79/common.c
-+++ b/arch/mips/ath79/common.c
-@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
-
- void ath79_ddr_wb_flush(u32 reg)
- {
-- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
-+ void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg * 4;
-
- /* Flush the DDR write buffer. */
- __raw_writel(0x1, flush_reg);
diff --git a/target/linux/ar71xx/patches-4.4/910-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-4.4/910-unaligned_access_hacks.patch
index bbfe7bd803..f766850aeb 100644
--- a/target/linux/ar71xx/patches-4.4/910-unaligned_access_hacks.patch
+++ b/target/linux/ar71xx/patches-4.4/910-unaligned_access_hacks.patch
@@ -250,7 +250,7 @@
&sin->sin6_addr);
sin->sin6_scope_id = 0;
}
-@@ -770,12 +770,12 @@ int ip6_datagram_send_ctl(struct net *ne
+@@ -773,12 +773,12 @@ int ip6_datagram_send_ctl(struct net *ne
}
if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
@@ -370,7 +370,7 @@
return neigh_create(&arp_tbl, pkey, dev);
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
-@@ -451,48 +451,53 @@ static void tcp_options_write(__be32 *pt
+@@ -456,48 +456,53 @@ static void tcp_options_write(__be32 *pt
u16 options = opts->options; /* mungable copy */
if (unlikely(OPTION_MD5 & options)) {
@@ -447,7 +447,7 @@
}
if (unlikely(opts->num_sack_blocks)) {
-@@ -500,16 +505,17 @@ static void tcp_options_write(__be32 *pt
+@@ -505,16 +510,17 @@ static void tcp_options_write(__be32 *pt
tp->duplicate_sack : tp->selective_acks;
int this_sack;
@@ -471,7 +471,7 @@
}
tp->rx_opt.dsack = 0;
-@@ -522,13 +528,14 @@ static void tcp_options_write(__be32 *pt
+@@ -527,13 +533,14 @@ static void tcp_options_write(__be32 *pt
if (foc->exp) {
len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
@@ -838,7 +838,7 @@
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
-@@ -3822,14 +3822,16 @@ static bool tcp_parse_aligned_timestamp(
+@@ -3836,14 +3836,16 @@ static bool tcp_parse_aligned_timestamp(
{
const __be32 *ptr = (const __be32 *)(th + 1);