diff options
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch b/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch new file mode 100644 index 0000000000..97400e3ec8 --- /dev/null +++ b/target/linux/ar71xx/patches-4.9/940-qca955x-add-more-registers.patch @@ -0,0 +1,44 @@ +Index: linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +=================================================================== +--- linux-4.9.111.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -134,7 +134,7 @@ + #define QCA955X_PCI_CTRL_SIZE 0x100 + + #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +-#define QCA955X_GMAC_SIZE 0x40 ++#define QCA955X_GMAC_SIZE 0x64 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 +@@ -1269,7 +1269,11 @@ + */ + + #define QCA955X_GMAC_REG_ETH_CFG 0x00 ++#define QCA955X_GMAC_REG_SGMII_RESET 0x14 + #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 ++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 + + #define QCA955X_ETH_CFG_RGMII_EN BIT(0) + #define QCA955X_ETH_CFG_MII_GE0 BIT(1) +@@ -1291,6 +1295,18 @@ + #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 + #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + ++#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0 ++#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) ++#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) ++#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) ++#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) ++#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) ++ ++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) ++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++ ++#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) ++ + #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) + #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 + #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf |