diff options
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch deleted file mode 100644 index 09e6617b90..0000000000 --- a/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Felix Fietkau <nbd@nbd.name> -Date: Sat, 14 May 2016 20:20:04 +0200 -Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer - SoCs - -AR913x, AR724x and AR933x are the only SoCs where the -ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c -Invert the logic to make the code compatible with AR95xx - -Signed-off-by: Felix Fietkau <nbd@nbd.name> ---- - ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void) - { - ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, - AR71XX_DDR_CTRL_SIZE); -- if (soc_is_ar71xx() || soc_is_ar934x()) { -- ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; -- ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; -- } else { -+ if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { - ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; - ath79_ddr_pci_win_base = 0; -+ } else { -+ ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; -+ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; - } - } - EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); |