diff options
Diffstat (limited to 'target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch b/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch new file mode 100644 index 0000000000..5a60ffe898 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch @@ -0,0 +1,113 @@ +From f48780829e9de625cb7fa0850fc31d050da6adeb Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Fri, 15 Feb 2013 13:38:16 +0000 +Subject: [PATCH] MIPS: ath79: add SoC detection code for the QCA955X SoCs + +commit 2e6c91e392fd7be2ef0ba1e9a20e0ebe8ab79cf3 upstream. + +Also add 'soc_is_qca955[68x]' helper functions +and a Kconfig symbol for the SoC family. + +Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com> +Cc: Giori, Kathy <kgiori@qca.qualcomm.com> +Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com> +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Patchwork: http://patchwork.linux-mips.org/patch/4943/ +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/ath79/setup.c | 18 +++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + arch/mips/include/asm/mach-ath79/ath79.h | 17 +++++++++++++++++ + 4 files changed, 40 insertions(+), 1 deletion(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -88,6 +88,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA955X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config PCI_AR724X + def_bool n + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9556: ++ ath79_soc = ATH79_SOC_QCA9556; ++ chip = "9556"; ++ rev = id & QCA955X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_QCA9558: ++ ath79_soc = ATH79_SOC_QCA9558; ++ chip = "9558"; ++ rev = id & QCA955X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } + + ath79_soc_rev = rev; + +- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); ++ if (soc_is_qca955x()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", ++ chip, rev); ++ else ++ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); + } + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -392,6 +392,8 @@ + + #define AR934X_REV_ID_REVISION_MASK 0xf + ++#define QCA955X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,8 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9556, ++ ATH79_SOC_QCA9558, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9556(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9556; ++} ++ ++static inline int soc_is_qca9558(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9558; ++} ++ ++static inline int soc_is_qca955x(void) ++{ ++ return soc_is_qca9556() || soc_is_qca9558(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; |