diff options
Diffstat (limited to 'target/linux/ar71xx/files/arch')
5 files changed, 613 insertions, 10 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c new file mode 100644 index 0000000000..18101ce8e4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c @@ -0,0 +1,171 @@ +/* + * MR1750 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include <linux/platform_device.h> +#include <linux/ar8216_platform.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <linux/platform_data/phy-at803x.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define MR1750_GPIO_LED_LAN 12 +#define MR1750_GPIO_LED_WLAN_2G 13 +#define MR1750_GPIO_LED_STATUS_GREEN 19 +#define MR1750_GPIO_LED_STATUS_RED 21 +#define MR1750_GPIO_LED_POWER 22 +#define MR1750_GPIO_LED_WLAN_5G 23 + +#define MR1750_GPIO_BTN_RESET 17 + +#define MR1750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR1750_KEYS_DEBOUNCE_INTERVAL (3 * MR1750_KEYS_POLL_INTERVAL) + +#define MR1750_MAC0_OFFSET 0 +#define MR1750_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led mr1750_leds_gpio[] __initdata = { + { + .name = "mr1750:blue:power", + .gpio = MR1750_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr1750:blue:wan", + .gpio = MR1750_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "mr1750:blue:wlan24", + .gpio = MR1750_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "mr1750:blue:wlan58", + .gpio = MR1750_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "mr1750:green:status", + .gpio = MR1750_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "mr1750:red:status", + .gpio = MR1750_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr1750_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR1750_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct at803x_platform_data mr1750_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 0, + .fixup_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info mr1750_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 5, + .platform_data = &mr1750_at803x_data, + }, +}; + +static void __init mr1750_setup_qca955x_eth_cfg(u32 mask, + unsigned int rxd, + unsigned int rxdv, + unsigned int txd, + unsigned int txe) +{ + void __iomem *base; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = mask; + t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init mr1750_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_eth0_pll_data.pll_1000 = 0xae000000; + ath79_eth0_pll_data.pll_100 = 0xa0000101; + ath79_eth0_pll_data.pll_10 = 0xa0001313; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio), + mr1750_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr1750_gpio_keys), + mr1750_gpio_keys); + + ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1); + ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac); + ath79_register_pci(); + + mr1750_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(mr1750_mdio0_info, + ARRAY_SIZE(mr1750_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(5); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup); +MIPS_MACHINE(ATH79_MACH_MR1750V2, "MR1750v2", "OpenMesh MR1750v2", mr1750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c index fe3e1fad51..b439f58892 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c @@ -23,6 +23,7 @@ #include <linux/ath9k_platform.h> #include <asm/mach-ath79/ar71xx_regs.h> +#include <linux/platform_data/phy-at803x.h> #include "common.h" #include "dev-ap9x-pci.h" @@ -94,18 +95,37 @@ static struct gpio_keys_button mr900_gpio_keys[] __initdata = { }, }; +static struct at803x_platform_data mr900_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 0, + .fixup_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info mr900_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 5, + .platform_data = &mr900_at803x_data, + }, +}; -static void __init mr900_gmac_setup(void) +static void __init mr900_setup_qca955x_eth_cfg(u32 mask, + unsigned int rxd, + unsigned int rxdv, + unsigned int txd, + unsigned int txe) { void __iomem *base; u32 t; base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); - t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); - - t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); - t |= QCA955X_ETH_CFG_RGMII_EN; + t = mask; + t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); @@ -118,9 +138,9 @@ static void __init mr900_setup(void) u8 mac[6], pcie_mac[6]; struct ath9k_platform_data *pdata; - ath79_eth0_pll_data.pll_1000 = 0xbe000101; - ath79_eth0_pll_data.pll_100 = 0x80000101; - ath79_eth0_pll_data.pll_10 = 0x80001313; + ath79_eth0_pll_data.pll_1000 = 0xae000000; + ath79_eth0_pll_data.pll_100 = 0xa0000101; + ath79_eth0_pll_data.pll_10 = 0xa0001313; ath79_register_m25p80(NULL); @@ -141,10 +161,12 @@ static void __init mr900_setup(void) } pdata->use_eeprom = true; - mr900_gmac_setup(); - + mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(mr900_mdio0_info, + ARRAY_SIZE(mr900_mdio0_info)); + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0); /* GMAC0 is connected to the RMGII interface */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c index 6b0bdc3dcd..3b282a36ea 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c @@ -223,3 +223,4 @@ static void __init om2p_hs_setup(void) MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup); MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup); +MIPS_MACHINE(ATH79_MACH_OM2P_HSv3, "OM2P-HSv3", "OpenMesh OM2P HSv3", om2p_hs_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pac.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pac.c new file mode 100644 index 0000000000..f6974aff71 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pac.c @@ -0,0 +1,193 @@ +/* + * OpenMesh OM5P-AC support + * + * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com> + * Copyright (C) 2014 Sven Eckelmann <sven@open-mesh.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/i2c-algo-bit.h> +#include <linux/i2c-gpio.h> +#include <linux/platform_data/phy-at803x.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define OM5PAC_GPIO_LED_POWER 18 +#define OM5PAC_GPIO_LED_GREEN 21 +#define OM5PAC_GPIO_LED_RED 23 +#define OM5PAC_GPIO_LED_YELLOW 22 +#define OM5PAC_GPIO_LED_LAN 20 +#define OM5PAC_GPIO_LED_WAN 19 +#define OM5PAC_GPIO_I2C_SCL 12 +#define OM5PAC_GPIO_I2C_SDA 11 + +#define OM5PAC_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM5PAC_KEYS_DEBOUNCE_INTERVAL (3 * OM5PAC_KEYS_POLL_INTERVAL) + +#define OM5PAC_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led om5pac_leds_gpio[] __initdata = { + { + .name = "om5pac:blue:power", + .gpio = OM5PAC_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om5pac:red:wifi", + .gpio = OM5PAC_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om5pac:yellow:wifi", + .gpio = OM5PAC_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om5pac:green:wifi", + .gpio = OM5PAC_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "om5pac:blue:lan", + .gpio = OM5PAC_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "om5pac:blue:wan", + .gpio = OM5PAC_GPIO_LED_WAN, + .active_low = 1, + } +}; + +static struct flash_platform_data om5pac_flash_data = { + .type = "mx25l12805d", +}; + +static struct i2c_gpio_platform_data om5pac_i2c_device_platdata = { + .sda_pin = OM5PAC_GPIO_I2C_SDA, + .scl_pin = OM5PAC_GPIO_I2C_SCL, + .udelay = 10, + .sda_is_open_drain = 1, + .scl_is_open_drain = 1, +}; + +static struct platform_device om5pac_i2c_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &om5pac_i2c_device_platdata, + }, +}; + +static struct i2c_board_info om5pac_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("tmp423", 0x4c), + }, +}; + +static struct at803x_platform_data om5pac_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info om5pac_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 1, + .platform_data = &om5pac_at803x_data, + }, + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 2, + .platform_data = &om5pac_at803x_data, + }, +}; + +static void __init om5p_ac_setup_qca955x_eth_cfg(u32 mask, + unsigned int rxd, + unsigned int rxdv, + unsigned int txd, + unsigned int txe) +{ + void __iomem *base; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = mask; + t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init om5p_ac_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + /* temperature sensor */ + platform_device_register(&om5pac_i2c_device); + i2c_register_board_info(0, om5pac_i2c_devs, + ARRAY_SIZE(om5pac_i2c_devs)); + + ath79_gpio_output_select(OM5PAC_GPIO_LED_WAN, QCA955X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&om5pac_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pac_leds_gpio), + om5pac_leds_gpio); + + ath79_init_mac(mac, art, 0x02); + ath79_register_wmac(art + OM5PAC_WMAC_CALDATA_OFFSET, mac); + + om5p_ac_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(om5pac_mdio0_info, + ARRAY_SIZE(om5pac_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); + + /* GMAC0 is connected to the PHY1 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_mask = BIT(1); + ath79_eth0_pll_data.pll_1000 = 0x82000101; + ath79_eth0_pll_data.pll_100 = 0x80000101; + ath79_eth0_pll_data.pll_10 = 0x80001313; + ath79_register_eth(0); + + /* GMAC1 is connected to MDIO1 in SGMII mode */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth1_data.phy_mask = BIT(2); + ath79_eth1_pll_data.pll_1000 = 0x03000101; + ath79_eth1_pll_data.pll_100 = 0x80000101; + ath79_eth1_pll_data.pll_10 = 0x80001313; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_register_eth(1); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_OM5P_AC, "OM5P-AC", "OpenMesh OM5P AC", om5p_ac_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c new file mode 100644 index 0000000000..587ca32601 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c @@ -0,0 +1,216 @@ +/* + * OpenMesh OM5P-ACv2 support + * + * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com> + * Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com> + * Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/mdio-gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/i2c-algo-bit.h> +#include <linux/i2c-gpio.h> +#include <linux/platform_data/phy-at803x.h> + +#include <asm/mach-ath79/ar71xx_regs.h> +#include <asm/mach-ath79/ath79.h> + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define OM5PACV2_GPIO_LED_POWER 14 +#define OM5PACV2_GPIO_LED_GREEN 13 +#define OM5PACV2_GPIO_LED_RED 23 +#define OM5PACV2_GPIO_LED_YELLOW 15 +#define OM5PACV2_GPIO_BTN_RESET 1 +#define OM5PACV2_GPIO_I2C_SCL 18 +#define OM5PACV2_GPIO_I2C_SDA 19 +#define OM5PACV2_GPIO_PA_DCDC 2 +#define OM5PACV2_GPIO_PA_HIGH 16 + +#define OM5PACV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL) + +#define OM5PACV2_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led om5pacv2_leds_gpio[] __initdata = { + { + .name = "om5pac:blue:power", + .gpio = OM5PACV2_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om5pac:red:wifi", + .gpio = OM5PACV2_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om5pac:yellow:wifi", + .gpio = OM5PACV2_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om5pac:green:wifi", + .gpio = OM5PACV2_GPIO_LED_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = OM5PACV2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = { + .sda_pin = OM5PACV2_GPIO_I2C_SDA, + .scl_pin = OM5PACV2_GPIO_I2C_SCL, + .udelay = 10, + .sda_is_open_drain = 1, + .scl_is_open_drain = 1, +}; + +static struct platform_device om5pacv2_i2c_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &om5pacv2_i2c_device_platdata, + }, +}; + +static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("tmp423", 0x4e), + }, +}; + +static struct flash_platform_data om5pacv2_flash_data = { + .type = "mx25l12805d", +}; + +static struct at803x_platform_data om5pacv2_an_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct at803x_platform_data om5pacv2_an_at8031_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info om5pacv2_an_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 4, + .platform_data = &om5pacv2_an_at803x_data, + }, + { + .bus_id = "ag71xx-mdio.1", + .phy_addr = 1, + .platform_data = &om5pacv2_an_at8031_data, + }, +}; + +static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask, + unsigned int rxd, + unsigned int rxdv, + unsigned int txd, + unsigned int txe) +{ + void __iomem *base; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = mask; + t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static void __init om5p_acv2_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */ + ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE); + ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO); + gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH, + "PA DC/DC"); + gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH"); + + /* temperature sensor */ + platform_device_register(&om5pacv2_i2c_device); + i2c_register_board_info(0, om5pacv2_i2c_devs, + ARRAY_SIZE(om5pacv2_i2c_devs)); + + ath79_register_m25p80(&om5pacv2_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio), + om5pacv2_leds_gpio); + ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om5pacv2_gpio_keys), + om5pacv2_gpio_keys); + + ath79_init_mac(mac, art, 0x02); + ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac); + + om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0); + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, 0x0); + + mdiobus_register_board_info(om5pacv2_an_mdio0_info, + ARRAY_SIZE(om5pacv2_an_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); + + /* GMAC0 is connected to the PHY4 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_pll_data.pll_1000 = 0x82000101; + ath79_eth0_pll_data.pll_100 = 0x80000101; + ath79_eth0_pll_data.pll_10 = 0x80001313; + ath79_register_eth(0); + + /* GMAC1 is connected to MDIO1 in SGMII mode */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_eth1_data.phy_mask = BIT(1); + ath79_eth1_pll_data.pll_1000 = 0x03000101; + ath79_eth1_pll_data.pll_100 = 0x80000101; + ath79_eth1_pll_data.pll_10 = 0x80001313; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_register_eth(1); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup); 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