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-rw-r--r--package/acx/patches/003-endianness-fixes.patch112
1 files changed, 112 insertions, 0 deletions
diff --git a/package/acx/patches/003-endianness-fixes.patch b/package/acx/patches/003-endianness-fixes.patch
new file mode 100644
index 0000000000..05f6acf98d
--- /dev/null
+++ b/package/acx/patches/003-endianness-fixes.patch
@@ -0,0 +1,112 @@
+diff -Nur -x '*.o' -x '*.ko' acx-20070101/pci.c acx-20070101.big/pci.c
+--- acx-20070101/pci.c 2007-06-02 17:29:53.000000000 +0200
++++ acx-20070101.big/pci.c 2007-06-02 17:23:37.000000000 +0200
+@@ -123,6 +123,11 @@
+ ** Register access
+ */
+
++#define acx_readl(v) le32_to_cpu(readl((v)))
++#define acx_readw(v) le16_to_cpu(readw((v)))
++#define acx_writew(v,r) writew(le16_to_cpu((v)), r)
++#define acx_writel(v,r) writel(le32_to_cpu((v)), r)
++
+ /* Pick one */
+ /* #define INLINE_IO static */
+ #define INLINE_IO static inline
+@@ -131,17 +136,17 @@
+ read_reg32(acx_device_t *adev, unsigned int offset)
+ {
+ #if ACX_IO_WIDTH == 32
+- return readl((u8 *)adev->iobase + adev->io[offset]);
++ return acx_readl((u8 *)adev->iobase + adev->io[offset]);
+ #else
+- return readw((u8 *)adev->iobase + adev->io[offset])
+- + (readw((u8 *)adev->iobase + adev->io[offset] + 2) << 16);
++ return acx_readw((u8 *)adev->iobase + adev->io[offset])
++ + (acx_readw((u8 *)adev->iobase + adev->io[offset] + 2) << 16);
+ #endif
+ }
+
+ INLINE_IO u16
+ read_reg16(acx_device_t *adev, unsigned int offset)
+ {
+- return readw((u8 *)adev->iobase + adev->io[offset]);
++ return acx_readw((u8 *)adev->iobase + adev->io[offset]);
+ }
+
+ INLINE_IO u8
+@@ -154,17 +159,17 @@
+ write_reg32(acx_device_t *adev, unsigned int offset, u32 val)
+ {
+ #if ACX_IO_WIDTH == 32
+- writel(val, (u8 *)adev->iobase + adev->io[offset]);
++ acx_writel(val, (u8 *)adev->iobase + adev->io[offset]);
+ #else
+- writew(val & 0xffff, (u8 *)adev->iobase + adev->io[offset]);
+- writew(val >> 16, (u8 *)adev->iobase + adev->io[offset] + 2);
++ acx_writew(val & 0xffff, (u8 *)adev->iobase + adev->io[offset]);
++ acx_writew(val >> 16, (u8 *)adev->iobase + adev->io[offset] + 2);
+ #endif
+ }
+
+ INLINE_IO void
+ write_reg16(acx_device_t *adev, unsigned int offset, u16 val)
+ {
+- writew(val, (u8 *)adev->iobase + adev->io[offset]);
++ acx_writew(val, (u8 *)adev->iobase + adev->io[offset]);
+ }
+
+ INLINE_IO void
+@@ -192,7 +197,7 @@
+ {
+ /* fast version (accesses the first register, IO_ACX_SOFT_RESET,
+ * which should be safe): */
+- return readl(adev->iobase) != 0xffffffff;
++ return acx_readl(adev->iobase) != 0xffffffff;
+ }
+
+
+@@ -835,7 +840,7 @@
+ static inline void
+ acxpci_write_cmd_type_status(acx_device_t *adev, u16 type, u16 status)
+ {
+- writel(type | (status << 16), adev->cmd_area);
++ acx_writel(type | (status << 16), adev->cmd_area);
+ write_flush(adev);
+ }
+
+@@ -848,7 +853,7 @@
+ {
+ u32 cmd_type, cmd_status;
+
+- cmd_type = readl(adev->cmd_area);
++ cmd_type = acx_readl(adev->cmd_area);
+ cmd_status = (cmd_type >> 16);
+ cmd_type = (u16)cmd_type;
+
+@@ -2415,12 +2420,12 @@
+ #endif
+ u32 info_type, info_status;
+
+- info_type = readl(adev->info_area);
++ info_type = acx_readl(adev->info_area);
+ info_status = (info_type >> 16);
+ info_type = (u16)info_type;
+
+ /* inform fw that we have read this info message */
+- writel(info_type | 0x00010000, adev->info_area);
++ acx_writel(info_type | 0x00010000, adev->info_area);
+ write_reg16(adev, IO_ACX_INT_TRIG, INT_TRIG_INFOACK);
+ write_flush(adev);
+
+@@ -4209,8 +4214,8 @@
+ #define ENDIANNESS_STRING "running on a BIG-ENDIAN CPU\n"
+ #endif
+ log(L_INIT,
+- ENDIANNESS_STRING
+- "PCI module " ACX_RELEASE " initialized, "
++ "acx: " ENDIANNESS_STRING
++ "acx: PCI module " ACX_RELEASE " initialized, "
+ "waiting for cards to probe...\n"
+ );
+