diff options
Diffstat (limited to 'package/uboot-xburst/files/cpu')
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz4740.c | 559 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz4740_nand.c | 199 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz_lcd.c | 484 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz_lcd.h | 260 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz_mmc.c | 1416 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz_mmc.h | 113 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/jz_serial.c | 141 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/mmc_protocol.h | 273 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c | 420 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h | 234 | ||||
| -rw-r--r-- | package/uboot-xburst/files/cpu/mips/usb_boot.S | 880 |
11 files changed, 0 insertions, 4979 deletions
diff --git a/package/uboot-xburst/files/cpu/mips/jz4740.c b/package/uboot-xburst/files/cpu/mips/jz4740.c deleted file mode 100644 index 5ae57971d7..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz4740.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Jz4740 common routines - * - * Copyright (c) 2006 - * Ingenic Semiconductor, <jlwei@ingenic.cn> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> - -#ifdef CONFIG_JZ4740 -#include <common.h> -#include <command.h> -#include <asm/jz4740.h> - -extern void board_early_init(void); - -/* PLL output clock = EXTAL * NF / (NR * NO) - * - * NF = FD + 2, NR = RD + 2 - * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3) - */ -void pll_init(void) -{ - register unsigned int cfcr, plcr1; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */ - int nf, pllout2; - - cfcr = CPM_CPCCR_CLKOEN | - CPM_CPCCR_PCS | - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); - - /* Init USB Host clock, pllout2 must be n*48MHz */ - REG_CPM_UHCCDR = pllout2 / 48000000 - 1; - - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* init PLL */ - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; -} - -void pll_add_test(int new_freq) -{ - register unsigned int cfcr, plcr1; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; - int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */ - int nf, pllout2; - - cfcr = CPM_CPCCR_CLKOEN | - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2); - - /* Init UHC clock */ - REG_CPM_UHCCDR = pllout2 / 48000000 - 1; - - /* nf = new_freq * 2 / CONFIG_SYS_EXTAL; */ - nf = new_freq / 1000000; /* step length is 1M */ - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (10 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* init PLL */ - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; -} - -void calc_clocks_add_test(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int pllout; - unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - pllout = __cpm_get_pllout(); - - gd->cpu_clk = pllout / div[__cpm_get_cdiv()]; - gd->sys_clk = pllout / div[__cpm_get_hdiv()]; - gd->per_clk = pllout / div[__cpm_get_pdiv()]; - gd->mem_clk = pllout / div[__cpm_get_mdiv()]; - gd->dev_clk = CONFIG_SYS_EXTAL; -} - -void sdram_add_test(int new_freq) -{ - register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = new_freq; - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; - - REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE; - REG_EMC_RTCOR = 0; - REG_EMC_RTCNT = 0; - - /* Basic DMCR register value. */ - dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | - ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | - (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | - (SDRAM_BW16<<EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* SDRAM timimg parameters */ - ns = 1000000000 / mem_clk; - -#if 0 - tmp = SDRAM_TRAS/ns; - if (tmp < 4) tmp = 4; - if (tmp > 11) tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - - tmp = SDRAM_RCD/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - - tmp = SDRAM_TPC/ns; - if (tmp > 7) tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - - tmp = SDRAM_TRWL/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; - if (tmp > 14) tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); -#else - dmcr |= 0xfffc; -#endif - - /* First, precharge phase */ - REG_EMC_DMCR = dmcr; - - /* Set refresh registers */ - tmp = SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - - REG_EMC_RTCOR = tmp; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* SDRAM mode values */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* precharge all chip-selects */ - REG8(EMC_SDMR0|sdmode) = 0; - - /* wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 200; - while (tmp--); - - /* enable refresh and set SDRAM mode */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* write sdram mode register for each chip-select */ - REG8(EMC_SDMR0|sdmode) = 0; - - /* everything is ok now */ -} - -void sdram_init(void) -{ - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = CONFIG_SYS_CPU_SPEED; - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; - - REG_EMC_BCR = 0; /* Disable bus release */ - REG_EMC_RTCSR = 0; /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ -#define SDRAM_ROW0 11 -#define SDRAM_COL0 8 -#define SDRAM_BANK40 0 - - dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | - ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | - (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | - (SDRAM_BW16<<EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Basic DMCR value */ - dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | - ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | - (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | - (SDRAM_BW16<<EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* SDRAM timimg */ - ns = 1000000000 / mem_clk; - tmp = SDRAM_TRAS/ns; - if (tmp < 4) tmp = 4; - if (tmp > 11) tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - tmp = SDRAM_RCD/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - tmp = SDRAM_TPC/ns; - if (tmp > 7) tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - tmp = SDRAM_TRWL/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; - if (tmp > 14) tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - REG_EMC_DMCR = dmcr; - REG8(EMC_SDMR0|sdmode) = 0; - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 2. Enable auto-refresh */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; - - tmp = SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - REG_EMC_RTCOR = tmp; - REG_EMC_RTCNT = 0; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 3. Mode Register Set */ - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - REG8(EMC_SDMR0|sdmode) = 0; - - /* Set back to basic DMCR value */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* everything is ok now */ -} - -#ifndef CONFIG_NAND_SPL - -static void calc_clocks(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int pllout; - unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - pllout = __cpm_get_pllout(); - - gd->cpu_clk = pllout / div[__cpm_get_cdiv()]; - gd->sys_clk = pllout / div[__cpm_get_hdiv()]; - gd->per_clk = pllout / div[__cpm_get_pdiv()]; - gd->mem_clk = pllout / div[__cpm_get_mdiv()]; - gd->dev_clk = CONFIG_SYS_EXTAL; -} - -static void rtc_init(void) -{ - unsigned long rtcsta; - - while ( !__rtc_write_ready()) ; - __rtc_enable_alarm(); /* enable alarm */ - - while ( !__rtc_write_ready()) - ; - REG_RTC_RGR = 0x00007fff; /* type value */ - - while ( !__rtc_write_ready()) - ; - REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ - - while ( !__rtc_write_ready()) - ; - REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ -#if 0 - while ( !__rtc_write_ready()) - ; - rtcsta = REG_RTC_HWRSR; - while ( !__rtc_write_ready()) - ; - if (rtcsta & 0x33) { - if (rtcsta & 0x10) { - while ( !__rtc_write_ready()) - ; - REG_RTC_RSR = 0x0; - } - while ( !__rtc_write_ready()) - ; - REG_RTC_HWRSR = 0x0; - } -#endif -} - -/* - * jz4740 board init routine - */ -int jz_board_init(void) -{ - board_early_init(); /* init gpio, pll etc. */ -#ifndef CONFIG_NAND_U_BOOT - pll_init(); /* init PLL */ - sdram_init(); /* init sdram memory */ -#endif - calc_clocks(); /* calc the clocks */ - rtc_init(); /* init rtc on any reset: */ - return 0; -} - -/* U-Boot common routines */ -phys_size_t initdram(int board_type) -{ - u32 dmcr; - u32 rows, cols, dw, banks; - ulong size; - - dmcr = REG_EMC_DMCR; - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; - - size = (1 << (rows + cols)) * dw * banks; - - return size; -} - -/* - * Timer routines - */ - -#define TIMER_CHAN 0 -#define TIMER_FDATA 0xffff /* Timer full data value */ -#define TIMER_HZ CONFIG_SYS_HZ - -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ - -static ulong timestamp; -static ulong lastdec; - -void reset_timer_masked (void); -ulong get_timer_masked (void); -void udelay_masked (unsigned long usec); - -/* - * timer without interrupts - */ - -int timer_init(void) -{ - REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; - REG_TCU_TCNT(TIMER_CHAN) = 0; - REG_TCU_TDHR(TIMER_CHAN) = 0; - REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; - - REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ - REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ - REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ - - lastdec = 0; - timestamp = 0; - - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked (); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer(ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } - else { - if (usec >= 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec <= now) { - /* normal mode */ - timestamp += (now - lastdec); - } else { - /* we have an overflow ... */ - timestamp += TIMER_FDATA + now - lastdec; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return TIMER_HZ; -} - -#endif /* CONFIG_NAND_SPL */ - -/* End of timer routine. */ - -#endif diff --git a/package/uboot-xburst/files/cpu/mips/jz4740_nand.c b/package/uboot-xburst/files/cpu/mips/jz4740_nand.c deleted file mode 100644 index 7877194f14..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz4740_nand.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Platform independend driver for JZ4740. - * - * Copyright (c) 2007 Ingenic Semiconductor Inc. - * Author: <jlwei@ingenic.cn> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ -#include <common.h> - -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740) - -#include <nand.h> -#include <asm/jz4740.h> -#include <asm/io.h> - -#define PAR_SIZE 9 -#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST ) -#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) - -#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS) - -#define __nand_rs_ecc_encoding() (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING) -#define __nand_rs_ecc_decoding() (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING) -#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) -#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) - -static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long nandaddr = (unsigned long)this->IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - /* Change this to use I/O accessors. */ - if (ctrl & NAND_NCE) - REG_EMC_NFCSR |= EMC_NFCSR_NFCE1; - else - REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1; - } - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - nandaddr |= 0x00008000; - else /* must be ALE */ - nandaddr |= 0x00010000; - - writeb(cmd, (uint8_t *)nandaddr); -} - -static int jz_device_ready(struct mtd_info *mtd) -{ - int ready; - udelay(20); /* FIXME: add 20us delay */ - ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0; - return ready; -} - -/* - * EMC setup - */ -static void jz_device_setup(void) -{ - /* Set NFE bit */ - REG_EMC_NFCSR |= EMC_NFCSR_NFE1; - REG_EMC_SMCR1 = 0x094c4400; - /* REG_EMC_SMCR3 = 0x04444400; */ -} - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - /* - * Don't use "chip" to address the NAND device, - * generate the cs from the address where it is encoded. - */ -} - -static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat, - u_char* ecc_code) -{ - volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0; - short i; - - __nand_ecc_encode_sync() - __nand_ecc_disable(); - - for(i = 0; i < PAR_SIZE; i++) - ecc_code[i] = *paraddr++; - - return 0; -} - -static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode) -{ - __nand_ecc_enable(); - __nand_select_rs_ecc(); - - REG_EMC_NFINTS = 0x0; - if (NAND_ECC_READ == mode){ - __nand_rs_ecc_decoding(); - } - if (NAND_ECC_WRITE == mode){ - __nand_rs_ecc_encoding(); - } -} - -/* Correct 1~9-bit errors in 512-bytes data */ -static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask) -{ - int i; - - idx--; - - i = idx + (idx >> 3); - if (i >= 512) - return; - - mask <<= (idx & 0x7); - - dat[i] ^= mask & 0xff; - if (i < 511) - dat[i+1] ^= (mask >> 8) & 0xff; -} - -static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0; - short k; - u32 stat; - /* Set PAR values */ - - for (k = 0; k < PAR_SIZE; k++) { - *paraddr++ = read_ecc[k]; - } - - /* Set PRDY */ - REG_EMC_NFECR |= EMC_NFECR_PRDY; - - /* Wait for completion */ - __nand_ecc_decode_sync(); - __nand_ecc_disable(); - - /* Check decoding */ - stat = REG_EMC_NFINTS; - if (stat & EMC_NFINTS_ERR) { - if (stat & EMC_NFINTS_UNCOR) { - printk("Uncorrectable error occurred\n"); - return -1; - } - else { - u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; - switch (errcnt) { - case 4: - jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - case 3: - jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - case 2: - jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - case 1: - jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); - return 0; - default: - break; - } - } - } - /* no error need to be correct */ - return 0; -} - -/* - * Main initialization routine - */ -int board_nand_init(struct nand_chip *nand) -{ - jz_device_setup(); - - nand->cmd_ctrl = jz_hwcontrol; - nand->dev_ready = jz_device_ready; - - /* FIXME: should use NAND_ECC_SOFT */ - nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc; - nand->ecc.correct = jzsoc_nand_rs_correct_data; - nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = 512; - nand->ecc.bytes = 9; - - /* 20 us command delay time */ - nand->chip_delay = 20; - - return 0; -} -#endif /* (CONFIG_SYS_CMD_NAND) */ diff --git a/package/uboot-xburst/files/cpu/mips/jz_lcd.c b/package/uboot-xburst/files/cpu/mips/jz_lcd.c deleted file mode 100644 index 927b82a6ac..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz_lcd.c +++ /dev/null @@ -1,484 +0,0 @@ -/* - * JzRISC lcd controller - * - * xiangfu liu <xiangfu.z@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Fallowing macro may be used: - * CONFIG_LCD : LCD support - * LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 - * CONFIG_LCD_LOGO : show logo - */ - -#include <config.h> -#include <common.h> -#include <lcd.h> - -#include <asm/io.h> /* virt_to_phys() */ - -#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD) - -#if defined(CONFIG_JZ4740) -#include <asm/jz4740.h> -#endif - -#include "jz_lcd.h" - - -struct jzfb_info { - unsigned int cfg; /* panel mode and pin usage etc. */ - unsigned int w; - unsigned int h; - unsigned int bpp; /* bit per pixel */ - unsigned int fclk; /* frame clk */ - unsigned int hsw; /* hsync width, in pclk */ - unsigned int vsw; /* vsync width, in line count */ - unsigned int elw; /* end of line, in pclk */ - unsigned int blw; /* begin of line, in pclk */ - unsigned int efw; /* end of frame, in line count */ - unsigned int bfw; /* begin of frame, in line count */ -}; - -static struct jzfb_info jzfb = { - #if defined(CONFIG_NANONOTE) - MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, - 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 - #endif - -}; - -/************************************************************************/ - -vidinfo_t panel_info = { -#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) - 320, 240, LCD_BPP, -#endif -}; - -/*----------------------------------------------------------------------*/ - -int lcd_line_length; - -int lcd_color_fg; -int lcd_color_bg; - -/* - * Frame buffer memory information - */ -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - -/*----------------------------------------------------------------------*/ - -void lcd_ctrl_init (void *lcdbase); - -void lcd_enable (void); -void lcd_disable (void); - -/*----------------------------------------------------------------------*/ - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); -static void jz_lcd_desc_init(vidinfo_t *vid); -static int jz_lcd_hw_init( vidinfo_t *vid ); -extern int flush_cache_all(void); - -#if LCD_BPP == LCD_COLOR8 -void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); -#endif -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void); -#endif - -/*-----------------------------------------------------------------------*/ - -void lcd_ctrl_init (void *lcdbase) -{ - __lcd_display_pin_init(); - - jz_lcd_init_mem(lcdbase, &panel_info); - jz_lcd_desc_init(&panel_info); - jz_lcd_hw_init(&panel_info); - - __lcd_display_on() ; -} - -/*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ -} -#endif -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_MONOCHROME -static -void lcd_initcolregs (void) -{ -} -#endif - -/* - * Before enabled lcd controller, lcd registers should be configured correctly. - */ - -void lcd_enable (void) -{ - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ -} - -void lcd_disable (void) -{ - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ - /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ -} - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) -{ - u_long palette_mem_size; - struct jz_fb_info *fbi = &vid->jz_fb; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (u_long)lcdbase; - fbi->palette_size = 256; - palette_mem_size = fbi->palette_size * sizeof(u16); - - debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); - /* locate palette and descs at end of page following fb */ - fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} - -static void jz_lcd_desc_init(vidinfo_t *vid) -{ - struct jz_fb_info * fbi; - fbi = &vid->jz_fb; - fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); - fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; - - fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ - - fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); - - if( NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); - fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); - } else { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ - } - - flush_cache_all(); -} - -static int jz_lcd_hw_init(vidinfo_t *vid) -{ - struct jz_fb_info *fbi = &vid->jz_fb; - unsigned int val = 0; - unsigned int pclk; - unsigned int stnH; -#if defined(CONFIG_MIPS_JZ4740) - int pll_div; -#endif - - /* Setting Control register */ - switch (jzfb.bpp) { - case 1: - val |= LCD_CTRL_BPP_1; - break; - case 2: - val |= LCD_CTRL_BPP_2; - break; - case 4: - val |= LCD_CTRL_BPP_4; - break; - case 8: - val |= LCD_CTRL_BPP_8; - break; - case 15: - val |= LCD_CTRL_RGB555; - case 16: - val |= LCD_CTRL_BPP_16; - break; -#if defined(CONFIG_MIPS_JZ4740) - case 17 ... 32: - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ - break; -#endif - default: - printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); - val |= LCD_CTRL_BPP_16; - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.bpp) { - case 1: - /* val |= LCD_CTRL_PEDN; */ - case 2: - val |= LCD_CTRL_FRC_2; - break; - case 4: - val |= LCD_CTRL_FRC_4; - break; - case 8: - default: - val |= LCD_CTRL_FRC_16; - break; - } - break; - } - - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.cfg & STN_DAT_PINMASK) { -#define align2(n) (n)=((((n)+1)>>1)<<1) -#define align4(n) (n)=((((n)+3)>>2)<<2) -#define align8(n) (n)=((((n)+7)>>3)<<3) - case STN_DAT_PIN1: - /* Do not adjust the hori-param value. */ - break; - case STN_DAT_PIN2: - align2(jzfb.hsw); - align2(jzfb.elw); - align2(jzfb.blw); - break; - case STN_DAT_PIN4: - align4(jzfb.hsw); - align4(jzfb.elw); - align4(jzfb.blw); - break; - case STN_DAT_PIN8: - align8(jzfb.hsw); - align8(jzfb.elw); - align8(jzfb.blw); - break; - } - break; - } - - REG_LCD_CTRL = val; - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - stnH = jzfb.h >> 1; - else - stnH = jzfb.h; - - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); - - /* Screen setting */ - REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); - REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); - REG_LCD_DAV = (0 << 16) | (stnH); - - /* AC BIAs signal */ - REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); - - break; - - case MODE_TFT_GEN: - case MODE_TFT_SHARP: - case MODE_TFT_CASIO: - case MODE_TFT_SAMSUNG: - case MODE_8BIT_SERIAL_TFT: - case MODE_TFT_18BIT: - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; -#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42) - REG_LCD_DAV = (0 << 16) | ( jzfb.h ); -#else - REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); -#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/ - REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); - REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ - | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_TFT_SAMSUNG: - { - unsigned int total, tp_s, tp_e, ckv_s, ckv_e; - unsigned int rev_s, rev_e, inv_s, inv_e; - - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - tp_s = jzfb.blw + jzfb.w + 1; - tp_e = tp_s + 1; - /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ - ckv_s = tp_s - pclk/(1000000000/4100); - ckv_e = tp_s + total; - rev_s = tp_s - 11; /* -11.5 clk */ - rev_e = rev_s + total; - inv_s = tp_s; - inv_e = inv_s + total; - REG_LCD_CLS = (tp_s << 16) | tp_e; - REG_LCD_PS = (ckv_s << 16) | ckv_e; - REG_LCD_SPL = (rev_s << 16) | rev_e; - REG_LCD_REV = (inv_s << 16) | inv_e; - jzfb.cfg |= STFT_REVHI | STFT_SPLHI; - break; - } - case MODE_TFT_SHARP: - { - unsigned int total, cls_s, cls_e, ps_s, ps_e; - unsigned int spl_s, spl_e, rev_s, rev_e; - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; -#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42) - spl_s = 1; - spl_e = spl_s + 1; - cls_s = 0; - cls_e = total - 60; /* > 4us (pclk = 80ns) */ - ps_s = cls_s; - ps_e = cls_e; - rev_s = total - 40; /* > 3us (pclk = 80ns) */ - rev_e = rev_s + total; - jzfb.cfg |= STFT_PSHI; -#else /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/ - spl_s = total - 5; /* LD */ - spl_e = total -3; - cls_s = 32; /* CKV */ - cls_e = 145; - ps_s = 0; /* OEV */ - ps_e = 45; - rev_s = 0; /* POL */ - rev_e = 0; -#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/ - REG_LCD_SPL = (spl_s << 16) | spl_e; - REG_LCD_CLS = (cls_s << 16) | cls_e; - REG_LCD_PS = (ps_s << 16) | ps_e; - REG_LCD_REV = (rev_s << 16) | rev_e; - break; - } - case MODE_TFT_CASIO: - break; - } - - /* Configure the LCD panel */ - REG_LCD_CFG = jzfb.cfg; - - /* Timing setting */ - __cpm_stop_lcd(); - - val = jzfb.fclk; /* frame clk */ - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } - else { - /* serial mode: Hsync period = 3*Width_Pixel */ - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - pclk = (pclk * 3); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk >>= 1; - - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ - pll_div = pll_div ? 1 : 2 ; - val = ( __cpm_get_pllout()/pll_div ) / pclk; - val--; - if ( val > 0x1ff ) { - printf("CPM_LPCDR too large, set it to 0x1ff\n"); - val = 0x1ff; - } - __cpm_set_pixdiv(val); - - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ - if ( val > 150000000 ) { - printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); - printf("Change LCDClock to 150MHz\n"); - val = 150000000; - } - val = ( __cpm_get_pllout()/pll_div ) / val; - val--; - if ( val > 0x1f ) { - printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); - val = 0x1f; - } - __cpm_set_ldiv( val ); - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ - - __cpm_start_lcd(); - udelay(1000); - - REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ - - return 0; -} - diff --git a/package/uboot-xburst/files/cpu/mips/jz_lcd.h b/package/uboot-xburst/files/cpu/mips/jz_lcd.h deleted file mode 100644 index dfd63e03af..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz_lcd.h +++ /dev/null @@ -1,260 +0,0 @@ -/* - * JzRISC lcd controller - * - * xiangfu liu <xiangfu.z@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __JZLCD_H__ -#define __JZLCD_H__ - -#include <asm/io.h> -/* - * change u-boot macro to celinux macro - */ -/* Chip type */ -#if defined(CONFIG_JZ4740) -#define CONFIG_MIPS_JZ4740 1 -#endif - -/* board type */ -#if defined(CONFIG_NANONOTE) -#define CONFIG_MIPS_JZ4740_PI 1 -#endif - -#define mdelay(n) udelay((n)*1000) - -/* - * change u-boot macro to celinux macro - */ - -#define NR_PALETTE 256 - -struct lcd_desc{ - unsigned int next_desc; /* LCDDAx */ - unsigned int databuf; /* LCDSAx */ - unsigned int frame_id; /* LCDFIDx */ - unsigned int cmd; /* LCDCMDx */ -}; - -#define MODE_MASK 0x0f -#define MODE_TFT_GEN 0x00 -#define MODE_TFT_SHARP 0x01 -#define MODE_TFT_CASIO 0x02 -#define MODE_TFT_SAMSUNG 0x03 -#define MODE_CCIR656_NONINT 0x04 -#define MODE_CCIR656_INT 0x05 -#define MODE_STN_COLOR_SINGLE 0x08 -#define MODE_STN_MONO_SINGLE 0x09 -#define MODE_STN_COLOR_DUAL 0x0a -#define MODE_STN_MONO_DUAL 0x0b -#define MODE_8BIT_SERIAL_TFT 0x0c - -#define MODE_TFT_18BIT (1<<7) - -#define STN_DAT_PIN1 (0x00 << 4) -#define STN_DAT_PIN2 (0x01 << 4) -#define STN_DAT_PIN4 (0x02 << 4) -#define STN_DAT_PIN8 (0x03 << 4) -#define STN_DAT_PINMASK STN_DAT_PIN8 - -#define STFT_PSHI (1 << 15) -#define STFT_CLSHI (1 << 14) -#define STFT_SPLHI (1 << 13) -#define STFT_REVHI (1 << 12) - -#define SYNC_MASTER (0 << 16) -#define SYNC_SLAVE (1 << 16) - -#define DE_P (0 << 9) -#define DE_N (1 << 9) - -#define PCLK_P (0 << 10) -#define PCLK_N (1 << 10) - -#define HSYNC_P (0 << 11) -#define HSYNC_N (1 << 11) - -#define VSYNC_P (0 << 8) -#define VSYNC_N (1 << 8) - -#define DATA_NORMAL (0 << 17) -#define DATA_INVERSE (1 << 17) - - -/* Jz LCDFB supported I/O controls. */ -#define FBIOSETBACKLIGHT 0x4688 -#define FBIODISPON 0x4689 -#define FBIODISPOFF 0x468a -#define FBIORESET 0x468b -#define FBIOPRINT_REG 0x468c - -/* - * LCD panel specific definition - */ - -#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL) - -#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */ -#define MODE 0xcd /* 24bit parellel RGB */ -#endif -#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL) -#define MODE 0xc9 /* 8bit serial RGB */ -#endif - -#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */ - #define SPEN (32*2+21) /*LCD_SPL */ - #define SPCK (32*2+23) /*LCD_CLS */ - #define SPDA (32*2+22) /*LCD_D12 */ - #define LCD_RET (32*3+27) -#else -#error "cpu/misp/Jzlcd.h, please define SPI pins on your board." -#endif - - #define __spi_write_reg1(reg, val) \ - do { \ - unsigned char no;\ - unsigned short value;\ - unsigned char a=0;\ - unsigned char b=0;\ - a=reg;\ - b=val;\ - __gpio_set_pin(SPEN);\ - __gpio_set_pin(SPCK);\ - __gpio_clear_pin(SPDA);\ - __gpio_clear_pin(SPEN);\ - udelay(25);\ - value=((a<<8)|(b&0xFF));\ - for(no=0;no<16;no++)\ - {\ - __gpio_clear_pin(SPCK);\ - if((value&0x8000)==0x8000)\ - __gpio_set_pin(SPDA);\ - else\ - __gpio_clear_pin(SPDA);\ - udelay(25);\ - __gpio_set_pin(SPCK);\ - value=(value<<1); \ - udelay(25);\ - }\ - __gpio_set_pin(SPEN);\ - udelay(100);\ - } while (0) - - #define __spi_write_reg(reg, val) \ - do {\ - __spi_write_reg1((reg<<2|2), val);\ - udelay(100); \ - }while(0) - - - #define __lcd_special_pin_init() \ - do { \ - __gpio_as_output(SPEN); /* use SPDA */\ - __gpio_as_output(SPCK); /* use SPCK */\ - __gpio_as_output(SPDA); /* use SPDA */\ - __gpio_as_output(LCD_RET);\ - } while (0) - -#if defined(CONFIG_NANONOTE) - #define __lcd_special_on() \ - do { \ - udelay(50);\ - __spi_write_reg1(0x05, 0x16); \ - __spi_write_reg1(0x04, 0x0b); \ - __spi_write_reg1(0x07, 0x8d); \ - __spi_write_reg1(0x01, 0x95); \ - __spi_write_reg1(0x08, 0xc0); \ - __spi_write_reg1(0x03, 0x40); \ - __spi_write_reg1(0x06, 0x15); \ - __spi_write_reg1(0x05, 0xd7); \ - } while (0) /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */ - - #define __lcd_special_off() \ - do { \ - __spi_write_reg1(0x05, 0x5e); \ - } while (0) -#endif /* CONFIG_NANONOTE */ -#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */ - -#ifndef __lcd_special_pin_init -#define __lcd_special_pin_init() -#endif -#ifndef __lcd_special_on -#define __lcd_special_on() -#endif -#ifndef __lcd_special_off -#define __lcd_special_off() -#endif - - -/* - * Platform specific definition - */ - -#if defined(CONFIG_MIPS_JZ4740_PI) - - /* 100 level: 0,1,...,100 */ - #define __lcd_set_backlight_level(n)\ - do { \ - __gpio_as_output(32*3+27); \ - __gpio_set_pin(32*3+27); \ - } while (0) - - #define __lcd_close_backlight() \ - do { \ - __gpio_as_output(GPIO_PWM); \ - __gpio_clear_pin(GPIO_PWM); \ - } while (0) - - #define __lcd_display_pin_init() \ - do { \ - __gpio_as_output(GPIO_DISP_OFF_N); \ - __cpm_start_tcu(); \ - __lcd_special_pin_init(); \ - } while (0) - /* __lcd_set_backlight_level(100); \*/ - #define __lcd_display_on() \ - do { \ - __gpio_set_pin(GPIO_DISP_OFF_N); \ - __lcd_special_on(); \ - } while (0) - - #define __lcd_display_off() \ - do { \ - __lcd_special_off(); \ - __gpio_clear_pin(GPIO_DISP_OFF_N); \ - } while (0) - -#endif /* CONFIG_MIPS_JZ4740_PI) */ - -/***************************************************************************** - * LCD display pin dummy macros - *****************************************************************************/ -#ifndef __lcd_display_pin_init -#define __lcd_display_pin_init() -#endif -#ifndef __lcd_display_on -#define __lcd_display_on() -#endif -#ifndef __lcd_display_off -#define __lcd_display_off() -#endif -#ifndef __lcd_set_backlight_level -#define __lcd_set_backlight_level(n) -#endif - diff --git a/package/uboot-xburst/files/cpu/mips/jz_mmc.c b/package/uboot-xburst/files/cpu/mips/jz_mmc.c deleted file mode 100644 index b3c4e99604..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz_mmc.c +++ /dev/null @@ -1,1416 +0,0 @@ -/* - * (C) Copyright 2003 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <part.h> - -#if defined CONFIG_JZ4740 -#include <asm-mips/jz4740.h> - -#include "jz_mmc.h" - -#define CFG_MMC_BASE 0x80600000 -static int sd2_0 = 0; - -/* - * GPIO definition - */ -#if defined(CONFIG_SAKC) - -#define __msc_init_io() \ -do { \ - __gpio_as_input(GPIO_SD_CD_N); \ -} while (0) - -#else -#define __msc_init_io() \ -do { \ - __gpio_as_output(GPIO_SD_VCC_EN_N); \ - __gpio_as_input(GPIO_SD_CD_N); \ -} while (0) - -#define __msc_enable_power() \ -do { \ - __gpio_clear_pin(GPIO_SD_VCC_EN_N); \ -} while (0) - -#define __msc_disable_power() \ -do { \ - __gpio_set_pin(GPIO_SD_VCC_EN_N); \ -} while (0) - -#endif /* CONFIG_SAKE */ - -#define __msc_card_detected() \ -({ \ - int detected = 1; \ - __gpio_as_input(GPIO_SD_CD_N); \ - __gpio_disable_pull(GPIO_SD_CD_N); \ - if (!__gpio_get_pin(GPIO_SD_CD_N)) \ - detected = 0; \ - detected; \ -}) - -/* - * Local functions - */ - -#ifdef CONFIG_MMC -extern int -fat_register_device(block_dev_desc_t *dev_desc, int part_no); - -static block_dev_desc_t mmc_dev; - -block_dev_desc_t * mmc_get_dev(int dev) -{ - return ((block_dev_desc_t *)&mmc_dev); -} - -/* - * FIXME needs to read cid and csd info to determine block size - * and other parameters - */ -static uchar mmc_buf[MMC_BLOCK_SIZE]; -static int mmc_ready = 0; -static mmc_csd_t mmc_csd; -static int use_4bit; /* Use 4-bit data bus */ -/* - * MMC Events - */ -#define MMC_EVENT_NONE 0x00 /* No events */ -#define MMC_EVENT_RX_DATA_DONE 0x01 /* Rx data done */ -#define MMC_EVENT_TX_DATA_DONE 0x02 /* Tx data done */ -#define MMC_EVENT_PROG_DONE 0x04 /* Programming is done */ - - -#define MMC_IRQ_MASK() \ -do { \ - REG_MSC_IMASK = 0xffff; \ - REG_MSC_IREG = 0xffff; \ -} while (0) - -/* Stop the MMC clock and wait while it happens */ -static inline int jz_mmc_stop_clock(void) -{ - int timeout = 1000; - - REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; - - while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) { - timeout--; - if (timeout == 0) { - return MMC_ERROR_TIMEOUT; - } - udelay(1); - } - return MMC_NO_ERROR; -} - -/* Start the MMC clock and operation */ -static inline int jz_mmc_start_clock(void) -{ - REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP; - return MMC_NO_ERROR; -} - -static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate) -{ - u32 clkrt; - u32 clk_src = is_sd ? 24000000: 16000000; - - clkrt = 0; - while (rate < clk_src) - { - clkrt ++; - clk_src >>= 1; - } - return clkrt; -} - -/* Set the MMC clock frequency */ -void jz_mmc_set_clock(int sd, u32 rate) -{ - jz_mmc_stop_clock(); - - /* Select clock source of MSC */ - __cpm_select_msc_clk(sd); - - /* Set clock dividor of MSC */ - REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate); -} - -static int jz_mmc_check_status(struct mmc_request *request) -{ - u32 status = REG_MSC_STAT; - - /* Checking for response or data timeout */ - if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) { - printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd); - return MMC_ERROR_TIMEOUT; - } - - /* Checking for CRC error */ - if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) { - printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status); - return MMC_ERROR_CRC; - } - - return MMC_NO_ERROR; -} - -/* Obtain response to the command and store it to response buffer */ -static void jz_mmc_get_response(struct mmc_request *request) -{ - int i; - u8 *buf; - u32 data; - - DEBUG(3, "fetch response for request %d, cmd %d\n", request->rtype, request->cmd); - - buf = request->response; - request->result = MMC_NO_ERROR; - - switch (request->rtype) { - case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6: - case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5: - { - data = REG_MSC_RES; - buf[0] = (data >> 8) & 0xff; - buf[1] = data & 0xff; - data = REG_MSC_RES; - buf[2] = (data >> 8) & 0xff; - buf[3] = data & 0xff; - data = REG_MSC_RES; - buf[4] = data & 0xff; - - DEBUG(3, "request %d, response [%02x %02x %02x %02x %02x]\n", - request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]); - break; - } - case RESPONSE_R2_CID: case RESPONSE_R2_CSD: - { - for (i = 0; i < 16; i += 2) { - data = REG_MSC_RES; - buf[i] = (data >> 8) & 0xff; - buf[i+1] = data & 0xff; - } - DEBUG(3, "request %d, response [", request->rtype); -#if CONFIG_MMC_DEBUG_VERBOSE > 2 - if (g_mmc_debug >= 3) { - int n; - for (n = 0; n < 17; n++) - printk("%02x ", buf[n]); - printk("]\n"); - } -#endif - break; - } - case RESPONSE_NONE: - DEBUG(3, "No response\n"); - break; - - default: - DEBUG(3, "unhandled response type for request %d\n", request->rtype); - break; - } -} - -static int jz_mmc_receive_data(struct mmc_request *req) -{ - u32 stat, timeout, data, cnt; - u8 *buf = req->buffer; - u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */ - - timeout = 0x3ffffff; - - while (timeout) { - timeout--; - stat = REG_MSC_STAT; - - if (stat & MSC_STAT_TIME_OUT_READ) - return MMC_ERROR_TIMEOUT; - else if (stat & MSC_STAT_CRC_READ_ERROR) - return MMC_ERROR_CRC; - else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY) - || (stat & MSC_STAT_DATA_FIFO_AFULL)) { - /* Ready to read data */ - break; - } - udelay(1); - } - if (!timeout) - return MMC_ERROR_TIMEOUT; - - /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */ - cnt = wblocklen; - while (cnt) { - data = REG_MSC_RXFIFO; - { - *buf++ = (u8)(data >> 0); - *buf++ = (u8)(data >> 8); - *buf++ = (u8)(data >> 16); - *buf++ = (u8)(data >> 24); - } - cnt --; - while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY)) - ; - } - return MMC_NO_ERROR; -} - -static int jz_mmc_transmit_data(struct mmc_request *req) -{ -#if 0 - u32 nob = req->nob; - u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */ - u8 *buf = req->buffer; - u32 *wbuf = (u32 *)buf; - u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */ - u32 stat, timeout, data, cnt; - - for (nob; nob >= 1; nob--) { - timeout = 0x3FFFFFF; - - while (timeout) { - timeout--; - stat = REG_MSC_STAT; - - if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS)) - return MMC_ERROR_CRC; - else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) { - /* Ready to write data */ - break; - } - - udelay(1); - } - - if (!timeout) - return MMC_ERROR_TIMEOUT; - - /* Write data to TXFIFO */ - cnt = wblocklen; - while (cnt) { - while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL) - ; - - if (waligned) { - REG_MSC_TXFIFO = *wbuf++; - } - else { - data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24); - REG_MSC_TXFIFO = data; - } - - cnt--; - } - } -#endif - return MMC_NO_ERROR; -} - - -/* - * Name: int jz_mmc_exec_cmd() - * Function: send command to the card, and get a response - * Input: struct mmc_request *req : MMC/SD request - * Output: 0: right >0: error code - */ -int jz_mmc_exec_cmd(struct mmc_request *request) -{ - u32 cmdat = 0, events = 0; - int retval, timeout = 0x3fffff; - - /* Indicate we have no result yet */ - request->result = MMC_NO_RESPONSE; - if (request->cmd == MMC_CIM_RESET) { - /* On reset, 1-bit bus width */ - use_4bit = 0; - - /* Reset MMC/SD controller */ - __msc_reset(); - - /* On reset, drop MMC clock down */ - jz_mmc_set_clock(0, MMC_CLOCK_SLOW); - - /* On reset, stop MMC clock */ - jz_mmc_stop_clock(); - } - if (request->cmd == MMC_SEND_OP_COND) { - DEBUG(3, "Have an MMC card\n"); - /* always use 1bit for MMC */ - use_4bit = 0; - } - if (request->cmd == SET_BUS_WIDTH) { - if (request->arg == 0x2) { - printf("Use 4-bit bus width\n"); - use_4bit = 1; - } - else { - printf("Use 1-bit bus width\n"); - use_4bit = 0; - } - } - - /* stop clock */ - jz_mmc_stop_clock(); - - /* mask all interrupts */ - REG_MSC_IMASK = 0xffff; - - /* clear status */ - REG_MSC_IREG = 0xffff; - - /* use 4-bit bus width when possible */ - if (use_4bit) - cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT; - - /* Set command type and events */ - switch (request->cmd) { - /* MMC core extra command */ - case MMC_CIM_RESET: - cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */ - break; - - /* bc - broadcast - no response */ - case MMC_GO_IDLE_STATE: - case MMC_SET_DSR: - break; - - /* bcr - broadcast with response */ - case MMC_SEND_OP_COND: - case MMC_ALL_SEND_CID: - case MMC_GO_IRQ_STATE: - break; - - /* adtc - addressed with data transfer */ - case MMC_READ_DAT_UNTIL_STOP: - case MMC_READ_SINGLE_BLOCK: - case MMC_READ_MULTIPLE_BLOCK: - case SEND_SCR: - cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ; - events = MMC_EVENT_RX_DATA_DONE; - break; - - case MMC_WRITE_DAT_UNTIL_STOP: - case MMC_WRITE_BLOCK: - case MMC_WRITE_MULTIPLE_BLOCK: - case MMC_PROGRAM_CID: - case MMC_PROGRAM_CSD: - case MMC_SEND_WRITE_PROT: - case MMC_GEN_CMD: - case MMC_LOCK_UNLOCK: - cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE; - events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE; - - break; - - case MMC_STOP_TRANSMISSION: - events = MMC_EVENT_PROG_DONE; - break; - - /* ac - no data transfer */ - default: - break; - } - - /* Set response type */ - switch (request->rtype) { - case RESPONSE_NONE: - break; - - case RESPONSE_R1B: - cmdat |= MSC_CMDAT_BUSY; - /*FALLTHRU*/ - case RESPONSE_R1: - cmdat |= MSC_CMDAT_RESPONSE_R1; - break; - case RESPONSE_R2_CID: - case RESPONSE_R2_CSD: - cmdat |= MSC_CMDAT_RESPONSE_R2; - break; - case RESPONSE_R3: - cmdat |= MSC_CMDAT_RESPONSE_R3; - break; - case RESPONSE_R4: - cmdat |= MSC_CMDAT_RESPONSE_R4; - break; - case RESPONSE_R5: - cmdat |= MSC_CMDAT_RESPONSE_R5; - break; - case RESPONSE_R6: - cmdat |= MSC_CMDAT_RESPONSE_R6; - break; - default: - break; - } - - /* Set command index */ - if (request->cmd == MMC_CIM_RESET) { - REG_MSC_CMD = MMC_GO_IDLE_STATE; - } else { - REG_MSC_CMD = request->cmd; - } - - /* Set argument */ - REG_MSC_ARG = request->arg; - - /* Set block length and nob */ - if (request->cmd == SEND_SCR) { /* get SCR from DataFIFO */ - REG_MSC_BLKLEN = 8; - REG_MSC_NOB = 1; - } else { - REG_MSC_BLKLEN = request->block_len; - REG_MSC_NOB = request->nob; - } - - /* Set command */ - REG_MSC_CMDAT = cmdat; - - DEBUG(1, "Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd, - cmdat, request->arg, request->rtype); - - /* Start MMC/SD clock and send command to card */ - jz_mmc_start_clock(); - - /* Wait for command completion */ - while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES)) - ; - - if (timeout == 0) - return MMC_ERROR_TIMEOUT; - - REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */ - - /* Check for status */ - retval = jz_mmc_check_status(request); - if (retval) { - return retval; - } - - /* Complete command with no response */ - if (request->rtype == RESPONSE_NONE) { - return MMC_NO_ERROR; - } - - /* Get response */ - jz_mmc_get_response(request); - - /* Start data operation */ - if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) { - if (events & MMC_EVENT_RX_DATA_DONE) { - if (request->cmd == SEND_SCR) { - /* SD card returns SCR register as data. - MMC core expect it in the response buffer, - after normal response. */ - request->buffer = (u8 *)((u32)request->response + 5); - } - jz_mmc_receive_data(request); - } - - if (events & MMC_EVENT_TX_DATA_DONE) { - jz_mmc_transmit_data(request); - } - - /* Wait for Data Done */ - while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE)) - ; - REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */ - } - - /* Wait for Prog Done event */ - if (events & MMC_EVENT_PROG_DONE) { - while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE)) - ; - REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */ - } - - /* Command completed */ - - return MMC_NO_ERROR; /* return successfully */ -} - -int mmc_block_read(u8 *dst, ulong src, ulong len) -{ - - struct mmc_request request; - struct mmc_response_r1 r1; - int retval; - - if (len == 0) { - return 0; - } - mmc_simple_cmd(&request, MMC_SEND_STATUS, mmcinfo.rca, RESPONSE_R1); - retval = mmc_unpack_r1(&request, &r1, 0); - if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) { - return retval; - } - - mmc_simple_cmd(&request, MMC_SET_BLOCKLEN, len, RESPONSE_R1); - if ((retval = mmc_unpack_r1(&request, &r1, 0))) { - return retval; - } - - if (sd2_0) - src /= len; - - mmc_send_cmd(&request, MMC_READ_SINGLE_BLOCK, src, 1,len, RESPONSE_R1, dst); - if ((retval = mmc_unpack_r1(&request, &r1, 0))) { - return retval; - } - return retval; -} - -int mmc_block_write(ulong dst, uchar *src, int len) -{ - return 0; -} - -int mmc_read(ulong src, uchar *dst, int size) -{ - ulong end, part_start, part_end, part_len, aligned_start, aligned_end; - ulong mmc_block_size, mmc_block_address; - - if (size == 0) { - return 0; - } - - if (!mmc_ready) { - printf("MMC card is not ready\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - src -= CFG_MMC_BASE; - end = src + size; - part_start = ~mmc_block_address & src; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & src; - aligned_end = mmc_block_address & end; - /* all block aligned accesses */ - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; - debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { - return -1; - } - memcpy(dst, mmc_buf+part_start, part_len); - dst += part_len; - src += part_len; - } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - - if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) { - return -1; - } - } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - - if (part_end && src < end) { - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { - return -1; - } - memcpy(dst, mmc_buf, part_end); - } - return 0; - -} - -int mmc_write(uchar *src, ulong dst, int size) -{ - ulong end, part_start, part_end, part_len, aligned_start, aligned_end; - ulong mmc_block_size, mmc_block_address; - - if (size == 0) { - return 0; - } - - if (!mmc_ready) { - printf("MMC card is not ready\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - dst -= CFG_MMC_BASE; - end = dst + size; - part_start = ~mmc_block_address & dst; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & dst; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; - debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) { - return -1; - } - memcpy(mmc_buf+part_start, src, part_len); - if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) { - return -1; - } - dst += part_len; - src += part_len; - } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) { - return -1; - } - } - debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if (part_end && dst < end) { - debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { - return -1; - } - memcpy(mmc_buf, src, part_end); - if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) { - return -1; - } - } - return 0; -} - -ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst) -{ - ulong src; - int mmc_block_size = MMC_BLOCK_SIZE; - - src = blknr * mmc_block_size + CFG_MMC_BASE; - mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size); - return blkcnt; -} - -int mmc_select_card(void) -{ - struct mmc_request request; - struct mmc_response_r1 r1; - int retval; - - mmc_simple_cmd(&request, MMC_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B); - retval = mmc_unpack_r1(&request, &r1, 0); - if (retval) { - return retval; - } - - if (mmcinfo.sd) { - mmc_simple_cmd(&request, MMC_APP_CMD, mmcinfo.rca, RESPONSE_R1); - retval = mmc_unpack_r1(&request,&r1,0); - if (retval) { - return retval; - } -#if defined(MMC_BUS_WIDTH_1BIT) - mmc_simple_cmd(&request, SET_BUS_WIDTH, 1, RESPONSE_R1); -#else - mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1); -#endif - retval = mmc_unpack_r1(&request,&r1,0); - if (retval) { - return retval; - } - } - return 0; -} - -/* - * Configure card - */ -static void mmc_configure_card(void) -{ - u32 rate; - - /* Get card info */ - if (sd2_0) - mmcinfo.block_num = (mmcinfo.csd.c_size + 1) << 10; - else - mmcinfo.block_num = (mmcinfo.csd.c_size + 1) * (1 << (mmcinfo.csd.c_size_mult + 2)); - - mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len; - - /* Fix the clock rate */ - rate = mmc_tran_speed(mmcinfo.csd.tran_speed); - if (rate < MMC_CLOCK_SLOW) - rate = MMC_CLOCK_SLOW; - if ((mmcinfo.sd == 0) && (rate > MMC_CLOCK_FAST)) - rate = MMC_CLOCK_FAST; - if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST)) - rate = SD_CLOCK_FAST; - - DEBUG(2,"mmc_configure_card: block_len=%d block_num=%d rate=%d\n", mmcinfo.block_len, mmcinfo.block_num, rate); - - jz_mmc_set_clock(mmcinfo.sd, rate); -} - -/* - * State machine routines to initialize card(s) - */ - -/* - CIM_SINGLE_CARD_ACQ (frequency at 400 kHz) - --- Must enter from GO_IDLE_STATE --- - 1. SD_SEND_OP_COND (SD Card) [CMD55] + [CMD41] - 2. SEND_OP_COND (Full Range) [CMD1] {optional} - 3. SEND_OP_COND (Set Range ) [CMD1] - If busy, delay and repeat step 2 - 4. ALL_SEND_CID [CMD2] - If timeout, set an error (no cards found) - 5. SET_RELATIVE_ADDR [CMD3] - 6. SEND_CSD [CMD9] - 7. SET_DSR [CMD4] Only call this if (csd.dsr_imp). - 8. Set clock frequency (check available in csd.tran_speed) - */ - -#define MMC_INIT_DOING 0 -#define MMC_INIT_PASSED 1 -#define MMC_INIT_FAILED 2 - -static int mmc_init_card_state(struct mmc_request *request) -{ - struct mmc_response_r1 r1; - struct mmc_response_r3 r3; - int retval; - int ocr = 0x40300000; - int limit_41 = 0; - - DEBUG(2,"mmc_init_card_state\n"); - - switch (request->cmd) { - case MMC_GO_IDLE_STATE: /* No response to parse */ - if (mmcinfo.sd) - mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1); - else - mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3); - break; - - case 8: - retval = mmc_unpack_r1(request,&r1,mmcinfo.state); - mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1); - break; - - case MMC_APP_CMD: - retval = mmc_unpack_r1(request,&r1,mmcinfo.state); - if (retval & (limit_41 < 100)) { - DEBUG(0, "mmc_init_card_state: unable to MMC_APP_CMD error=%d (%s)\n", - retval, mmc_result_to_string(retval)); - limit_41++; - mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3); - } else if (limit_41 < 100) { - limit_41++; - mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3); - } else{ - /* reset the card to idle*/ - mmc_simple_cmd(request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE); - mmcinfo.sd = 0; - } - break; - - case SD_SEND_OP_COND: - retval = mmc_unpack_r3(request, &r3); - if (retval) { - /* Try MMC card */ - mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3); - break; - } - - DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr); - - if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){ - udelay(10000); - mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1); - } - else { - /* Set the data bus width to 4 bits */ - mmcinfo.sd = 1; /* SD Card ready */ - mmcinfo.state = CARD_STATE_READY; - mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID); - } - break; - - case MMC_SEND_OP_COND: - retval = mmc_unpack_r3(request, &r3); - if (retval) { - DEBUG(0,"mmc_init_card_state: failed SEND_OP_COND error=%d (%s)\n", - retval, mmc_result_to_string(retval)); - return MMC_INIT_FAILED; - } - - DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr); - if (!(r3.ocr & MMC_CARD_BUSY)) { - mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3); - } - else { - mmcinfo.sd = 0; /* MMC Card ready */ - mmcinfo.state = CARD_STATE_READY; - mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID); - } - break; - - case MMC_ALL_SEND_CID: - retval = mmc_unpack_cid( request, &mmcinfo.cid ); - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_dev.blksz = 512; - mmc_dev.lba = 0x10000; - mmc_dev.removable = 0; - - /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */ - if ( retval && (retval != MMC_ERROR_CRC)) { - DEBUG(0,"mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n", - retval, mmc_result_to_string(retval)); - return MMC_INIT_FAILED; - } - mmcinfo.state = CARD_STATE_IDENT; - if(mmcinfo.sd) - mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, 0, RESPONSE_R6); - else - mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1); - break; - - case MMC_SET_RELATIVE_ADDR: - if (mmcinfo.sd) { - retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca); - mmcinfo.rca = mmcinfo.rca << 16; - DEBUG(2, "mmc_init_card_state: Get RCA from SD: 0x%04x Status: %x\n", mmcinfo.rca, r1.status); - } else { - retval = mmc_unpack_r1(request,&r1,mmcinfo.state); - mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16; - } - if (retval) { - DEBUG(0, "mmc_init_card_state: unable to SET_RELATIVE_ADDR error=%d (%s)\n", - retval, mmc_result_to_string(retval)); - return MMC_INIT_FAILED; - } - - mmcinfo.state = CARD_STATE_STBY; - mmc_simple_cmd(request, MMC_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD); - - break; - - case MMC_SEND_CSD: - retval = mmc_unpack_csd(request, &mmcinfo.csd); - mmc_csd_t *csd = (mmc_csd_t *)retval; - memcpy(&mmc_csd, csd, sizeof(csd)); - mmc_ready = 1; - - printf("MMC card is ready\n"); - /* FIXME add verbose printout for csd */ - - /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */ - if (retval && (retval != MMC_ERROR_CRC)) { - DEBUG(0, "mmc_init_card_state: unable to SEND_CSD error=%d (%s)\n", - retval, mmc_result_to_string(retval)); - return MMC_INIT_FAILED; - } - if (mmcinfo.csd.dsr_imp) { - DEBUG(0, "mmc_init_card_state: driver doesn't support setting DSR\n"); - } - mmc_configure_card(); - return MMC_INIT_PASSED; - - default: - DEBUG(0, "mmc_init_card_state: error! Illegal last cmd %d\n", request->cmd); - return MMC_INIT_FAILED; - } - - return MMC_INIT_DOING; -} - -int mmc_init_card(void) -{ - struct mmc_request request; - int retval; - - mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */ - mmc_simple_cmd(&request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE); - mmcinfo.sd = 1; /* assuming a SD card */ - - while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING) - ; - - if (retval == MMC_INIT_PASSED) - return MMC_NO_ERROR; - else - return MMC_NO_RESPONSE; -} - -int mmc_legacy_init(int verbose) -{ - if (!__msc_card_detected()) - return 1; - - printf("MMC card found\n"); - - /* Step-1: init GPIO */ - __gpio_as_msc(); - - __msc_init_io(); - - /* Step-2: turn on power of card */ -#if !defined(CONFIG_SAKC) - __msc_enable_power(); -#endif - - /* Step-3: Reset MSC Controller. */ - __msc_reset(); - - /* Step-3: mask all IRQs. */ - MMC_IRQ_MASK(); - - /* Step-4: stop MMC/SD clock */ - jz_mmc_stop_clock(); - mmc_init_card(); - mmc_select_card(); - - mmc_dev.block_read = mmc_bread; - fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ - - return 0; -} - -int mmc_ident(block_dev_desc_t *dev) -{ - return 0; -} - -int mmc2info(ulong addr) -{ - /* FIXME hard codes to 32 MB device */ - if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { - return 1; - } - return 0; -} -/* - * Debugging functions - */ - -static char * mmc_result_strings[] = { - "NO_RESPONSE", - "NO_ERROR", - "ERROR_OUT_OF_RANGE", - "ERROR_ADDRESS", - "ERROR_BLOCK_LEN", - "ERROR_ERASE_SEQ", - "ERROR_ERASE_PARAM", - "ERROR_WP_VIOLATION", - "ERROR_CARD_IS_LOCKED", - "ERROR_LOCK_UNLOCK_FAILED", - "ERROR_COM_CRC", - "ERROR_ILLEGAL_COMMAND", - "ERROR_CARD_ECC_FAILED", - "ERROR_CC", - "ERROR_GENERAL", - "ERROR_UNDERRUN", - "ERROR_OVERRUN", - "ERROR_CID_CSD_OVERWRITE", - "ERROR_STATE_MISMATCH", - "ERROR_HEADER_MISMATCH", - "ERROR_TIMEOUT", - "ERROR_CRC", - "ERROR_DRIVER_FAILURE", -}; - -char * mmc_result_to_string(int i) -{ - return mmc_result_strings[i+1]; -} - -static char * card_state_strings[] = { - "empty", - "idle", - "ready", - "ident", - "stby", - "tran", - "data", - "rcv", - "prg", - "dis", -}; - -static inline char * card_state_to_string(int i) -{ - return card_state_strings[i+1]; -} - -/* - * Utility functions - */ - -#define PARSE_U32(_buf,_index) \ - (((u32)_buf[_index]) << 24) | (((u32)_buf[_index+1]) << 16) | \ - (((u32)_buf[_index+2]) << 8) | ((u32)_buf[_index+3]); - -#define PARSE_U16(_buf,_index) \ - (((u16)_buf[_index]) << 8) | ((u16)_buf[_index+1]); - -int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd) -{ - u8 *buf = request->response; - int num = 0; - - if (request->result) - return request->result; - - csd->csd_structure = (buf[1] & 0xc0) >> 6; - if (csd->csd_structure) - sd2_0 = 1; - else - sd2_0 = 0; - - switch (csd->csd_structure) { - case 0 : - csd->taac = buf[2]; - csd->nsac = buf[3]; - csd->tran_speed = buf[4]; - csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4); - csd->read_bl_len = buf[6] & 0x0f; - /* for support 2GB card*/ - if (csd->read_bl_len >= 10) - { - num = csd->read_bl_len - 9; - csd->read_bl_len = 9; - } - - csd->read_bl_partial = (buf[7] & 0x80) ? 1 : 0; - csd->write_blk_misalign = (buf[7] & 0x40) ? 1 : 0; - csd->read_blk_misalign = (buf[7] & 0x20) ? 1 : 0; - csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0; - csd->c_size = ((((u16)buf[7]) & 0x03) << 10) | (((u16)buf[8]) << 2) | (((u16)buf[9]) & 0xc0) >> 6; - - if (num) - csd->c_size = csd->c_size << num; - - - csd->vdd_r_curr_min = (buf[9] & 0x38) >> 3; - csd->vdd_r_curr_max = buf[9] & 0x07; - csd->vdd_w_curr_min = (buf[10] & 0xe0) >> 5; - csd->vdd_w_curr_max = (buf[10] & 0x1c) >> 2; - csd->c_size_mult = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7); - switch (csd->csd_structure) { - case CSD_STRUCT_VER_1_0: - case CSD_STRUCT_VER_1_1: - csd->erase.v22.sector_size = (buf[11] & 0x7c) >> 2; - csd->erase.v22.erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5); - - break; - case CSD_STRUCT_VER_1_2: - default: - csd->erase.v31.erase_grp_size = (buf[11] & 0x7c) >> 2; - csd->erase.v31.erase_grp_mult = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5); - break; - } - csd->wp_grp_size = buf[12] & 0x1f; - csd->wp_grp_enable = (buf[13] & 0x80) ? 1 : 0; - csd->default_ecc = (buf[13] & 0x60) >> 5; - csd->r2w_factor = (buf[13] & 0x1c) >> 2; - csd->write_bl_len = ((buf[13] & 0x03) << 2) | ((buf[14] & 0xc0) >> 6); - if (csd->write_bl_len >= 10) - csd->write_bl_len = 9; - - csd->write_bl_partial = (buf[14] & 0x20) ? 1 : 0; - csd->file_format_grp = (buf[15] & 0x80) ? 1 : 0; - csd->copy = (buf[15] & 0x40) ? 1 : 0; - csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0; - csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0; - csd->file_format = (buf[15] & 0x0c) >> 2; - csd->ecc = buf[15] & 0x03; - - DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n" - " ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n" - " read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n" - " vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n" - " wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n" - " write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n" - " perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n", - csd->csd_structure, csd->spec_vers, - csd->taac, csd->nsac, csd->tran_speed, - csd->ccc, csd->read_bl_len, - csd->read_bl_partial, csd->write_blk_misalign, - csd->read_blk_misalign, csd->dsr_imp, - csd->c_size, csd->vdd_r_curr_min, - csd->vdd_r_curr_max, csd->vdd_w_curr_min, - csd->vdd_w_curr_max, csd->c_size_mult, - csd->wp_grp_size, csd->wp_grp_enable, - csd->default_ecc, csd->r2w_factor, - csd->write_bl_len, csd->write_bl_partial, - csd->file_format_grp, csd->copy, - csd->perm_write_protect, csd->tmp_write_protect, - csd->file_format, csd->ecc); - switch (csd->csd_structure) { - case CSD_STRUCT_VER_1_0: - case CSD_STRUCT_VER_1_1: - DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n", - csd->erase.v22.sector_size, - csd->erase.v22.erase_grp_size); - break; - case CSD_STRUCT_VER_1_2: - default: - DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n", - csd->erase.v31.erase_grp_size, - csd->erase.v31.erase_grp_mult); - break; - - } - break; - - case 1 : - csd->taac = 0; - csd->nsac = 0; - csd->tran_speed = buf[4]; - csd->ccc = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4); - - csd->read_bl_len = 9; - csd->read_bl_partial = 0; - csd->write_blk_misalign = 0; - csd->read_blk_misalign = 0; - csd->dsr_imp = (buf[7] & 0x10) ? 1 : 0; - csd->c_size = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ; - switch (csd->csd_structure) { - case CSD_STRUCT_VER_1_0: - case CSD_STRUCT_VER_1_1: - csd->erase.v22.sector_size = 0x7f; - csd->erase.v22.erase_grp_size = 0; - break; - case CSD_STRUCT_VER_1_2: - default: - csd->erase.v31.erase_grp_size = 0x7f; - csd->erase.v31.erase_grp_mult = 0; - break; - } - csd->wp_grp_size = 0; - csd->wp_grp_enable = 0; - csd->default_ecc = (buf[13] & 0x60) >> 5; - csd->r2w_factor = 4;/* Unused */ - csd->write_bl_len = 9; - - csd->write_bl_partial = 0; - csd->file_format_grp = 0; - csd->copy = (buf[15] & 0x40) ? 1 : 0; - csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0; - csd->tmp_write_protect = (buf[15] & 0x10) ? 1 : 0; - csd->file_format = 0; - csd->ecc = buf[15] & 0x03; - - DEBUG(2," csd_structure=%d spec_vers=%d taac=%02x nsac=%02x tran_speed=%02x\n" - " ccc=%04x read_bl_len=%d read_bl_partial=%d write_blk_misalign=%d\n" - " read_blk_misalign=%d dsr_imp=%d c_size=%d vdd_r_curr_min=%d\n" - " vdd_r_curr_max=%d vdd_w_curr_min=%d vdd_w_curr_max=%d c_size_mult=%d\n" - " wp_grp_size=%d wp_grp_enable=%d default_ecc=%d r2w_factor=%d\n" - " write_bl_len=%d write_bl_partial=%d file_format_grp=%d copy=%d\n" - " perm_write_protect=%d tmp_write_protect=%d file_format=%d ecc=%d\n", - csd->csd_structure, csd->spec_vers, - csd->taac, csd->nsac, csd->tran_speed, - csd->ccc, csd->read_bl_len, - csd->read_bl_partial, csd->write_blk_misalign, - csd->read_blk_misalign, csd->dsr_imp, - csd->c_size, csd->vdd_r_curr_min, - csd->vdd_r_curr_max, csd->vdd_w_curr_min, - csd->vdd_w_curr_max, csd->c_size_mult, - csd->wp_grp_size, csd->wp_grp_enable, - csd->default_ecc, csd->r2w_factor, - csd->write_bl_len, csd->write_bl_partial, - csd->file_format_grp, csd->copy, - csd->perm_write_protect, csd->tmp_write_protect, - csd->file_format, csd->ecc); - switch (csd->csd_structure) { - case CSD_STRUCT_VER_1_0: - case CSD_STRUCT_VER_1_1: - DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n", - csd->erase.v22.sector_size, - csd->erase.v22.erase_grp_size); - break; - case CSD_STRUCT_VER_1_2: - default: - DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n", - csd->erase.v31.erase_grp_size, - csd->erase.v31.erase_grp_mult); - break; - } - } - - if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH; - - return 0; -} - -int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state) -{ - u8 *buf = request->response; - - if (request->result) return request->result; - - r1->cmd = buf[0]; - r1->status = PARSE_U32(buf,1); - - DEBUG(2, "mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status); - - if (R1_STATUS(r1->status)) { - if (r1->status & R1_OUT_OF_RANGE) return MMC_ERROR_OUT_OF_RANGE; - if (r1->status & R1_ADDRESS_ERROR) return MMC_ERROR_ADDRESS; - if (r1->status & R1_BLOCK_LEN_ERROR) return MMC_ERROR_BLOCK_LEN; - if (r1->status & R1_ERASE_SEQ_ERROR) return MMC_ERROR_ERASE_SEQ; - if (r1->status & R1_ERASE_PARAM) return MMC_ERROR_ERASE_PARAM; - if (r1->status & R1_WP_VIOLATION) return MMC_ERROR_WP_VIOLATION; - /*if (r1->status & R1_CARD_IS_LOCKED) return MMC_ERROR_CARD_IS_LOCKED; */ - if (r1->status & R1_LOCK_UNLOCK_FAILED) return MMC_ERROR_LOCK_UNLOCK_FAILED; - if (r1->status & R1_COM_CRC_ERROR) return MMC_ERROR_COM_CRC; - if (r1->status & R1_ILLEGAL_COMMAND) return MMC_ERROR_ILLEGAL_COMMAND; - if (r1->status & R1_CARD_ECC_FAILED) return MMC_ERROR_CARD_ECC_FAILED; - if (r1->status & R1_CC_ERROR) return MMC_ERROR_CC; - if (r1->status & R1_ERROR) return MMC_ERROR_GENERAL; - if (r1->status & R1_UNDERRUN) return MMC_ERROR_UNDERRUN; - if (r1->status & R1_OVERRUN) return MMC_ERROR_OVERRUN; - if (r1->status & R1_CID_CSD_OVERWRITE) return MMC_ERROR_CID_CSD_OVERWRITE; - } - - if (buf[0] != request->cmd) return MMC_ERROR_HEADER_MISMATCH; - - /* This should be last - it's the least dangerous error */ - - return 0; -} - -int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr) -{ - u8 *buf = request->response; - if (request->result) return request->result; - - *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */ - return mmc_unpack_r1(request, r1, state); - -} - -int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca) -{ - u8 *buf = request->response; - - if (request->result) return request->result; - - *rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */ - - *(buf+1) = 0; - *(buf+2) = 0; - - return mmc_unpack_r1(request, r1, state); -} - -int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid) -{ - u8 *buf = request->response; - int i; - - if (request->result) return request->result; - - cid->mid = buf[1]; - cid->oid = PARSE_U16(buf,2); - for (i = 0 ; i < 6 ; i++) - cid->pnm[i] = buf[4+i]; - cid->pnm[6] = 0; - cid->prv = buf[10]; - cid->psn = PARSE_U32(buf,11); - cid->mdt = buf[15]; - - DEBUG(2,"mmc_unpack_cid: mid=%d oid=%d pnm=%s prv=%d.%d psn=%08x mdt=%d/%d\n", - cid->mid, cid->oid, cid->pnm, - (cid->prv>>4), (cid->prv&0xf), - cid->psn, (cid->mdt>>4), (cid->mdt&0xf)+1997); - - if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH; - return 0; -} - -int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3) -{ - u8 *buf = request->response; - - if (request->result) return request->result; - - r3->ocr = PARSE_U32(buf,1); - DEBUG(2,"mmc_unpack_r3: ocr=%08x\n", r3->ocr); - - if (buf[0] != 0x3f) return MMC_ERROR_HEADER_MISMATCH; - return 0; -} - -#define KBPS 1 -#define MBPS 1000 - -static u32 ts_exp[] = { 100*KBPS, 1*MBPS, 10*MBPS, 100*MBPS, 0, 0, 0, 0 }; -static u32 ts_mul[] = { 0, 1000, 1200, 1300, 1500, 2000, 2500, 3000, - 3500, 4000, 4500, 5000, 5500, 6000, 7000, 8000 }; - -u32 mmc_tran_speed(u8 ts) -{ - u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3]; - - if (rate <= 0) { - DEBUG(0, "mmc_tran_speed: error - unrecognized speed 0x%02x\n", ts); - return 1; - } - - return rate; -} - -void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, - u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer) -{ - request->cmd = cmd; - request->arg = arg; - request->rtype = rtype; - request->nob = nob; - request->block_len = block_len; - request->buffer = buffer; - request->cnt = nob * block_len; - - jz_mmc_exec_cmd(request); -} - -#endif /* CONFIG_MMC */ -#endif /* CONFIG_JZ4740 */ diff --git a/package/uboot-xburst/files/cpu/mips/jz_mmc.h b/package/uboot-xburst/files/cpu/mips/jz_mmc.h deleted file mode 100644 index 0c7b70ff8a..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz_mmc.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/drivers/mmc/jz_mmc.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: jz_mmc.h,v 1.3 2007-06-15 08:04:20 jlwei Exp $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_JZMMC_H__ -#define __MMC_JZMMC_H__ - -#include "mmc_protocol.h" - -#define MMC_DEBUG_LEVEL 0 /* Enable Debug: 0 - no debug */ - -#define MMC_BLOCK_SIZE 512 /* MMC/SD Block Size */ - -#define ID_TO_RCA(x) ((x)+1) - -#define MMC_OCR_ARG 0x00ff8000 /* Argument of OCR */ - -enum mmc_result_t { - MMC_NO_RESPONSE = -1, - MMC_NO_ERROR = 0, - MMC_ERROR_OUT_OF_RANGE, - MMC_ERROR_ADDRESS, - MMC_ERROR_BLOCK_LEN, - MMC_ERROR_ERASE_SEQ, - MMC_ERROR_ERASE_PARAM, - MMC_ERROR_WP_VIOLATION, - MMC_ERROR_CARD_IS_LOCKED, - MMC_ERROR_LOCK_UNLOCK_FAILED, - MMC_ERROR_COM_CRC, - MMC_ERROR_ILLEGAL_COMMAND, - MMC_ERROR_CARD_ECC_FAILED, - MMC_ERROR_CC, - MMC_ERROR_GENERAL, - MMC_ERROR_UNDERRUN, - MMC_ERROR_OVERRUN, - MMC_ERROR_CID_CSD_OVERWRITE, - MMC_ERROR_STATE_MISMATCH, - MMC_ERROR_HEADER_MISMATCH, - MMC_ERROR_TIMEOUT, - MMC_ERROR_CRC, - MMC_ERROR_DRIVER_FAILURE, -}; - -/* the information structure of MMC/SD Card */ -typedef struct MMC_INFO -{ - int id; /* Card index */ - int sd; /* MMC or SD card */ - int rca; /* RCA */ - u32 scr; /* SCR 63:32*/ - int flags; /* Ejected, inserted */ - enum card_state state; /* empty, ident, ready, whatever */ - - /* Card specific information */ - struct mmc_cid cid; - struct mmc_csd csd; - u32 block_num; - u32 block_len; - u32 erase_unit; -} mmc_info; - -mmc_info mmcinfo; - -struct mmc_request { - int index; /* Slot index - used for CS lines */ - int cmd; /* Command to send */ - u32 arg; /* Argument to send */ - enum mmc_rsp_t rtype; /* Response type expected */ - - /* Data transfer (these may be modified at the low level) */ - u16 nob; /* Number of blocks to transfer*/ - u16 block_len; /* Block length */ - u8 *buffer; /* Data buffer */ - u32 cnt; /* Data length, for PIO */ - - /* Results */ - u8 response[18]; /* Buffer to store response - CRC is optional */ - enum mmc_result_t result; -}; - -char * mmc_result_to_string(int); -int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd); -int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state); -int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca); -int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr); -int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid); -int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3); - -void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, - u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer); -u32 mmc_tran_speed(u8 ts); -void jz_mmc_set_clock(int sd, u32 rate); -void jz_mmc_hardware_init(void); - -static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype) -{ - mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0); -} - -int mmc_legacy_init(int verbose); -int mmc_read(ulong src, uchar *dst, int size); -int mmc_write(uchar *src, ulong dst, int size); -int mmc2info(ulong addr); - -#endif /* __MMC_JZMMC_H__ */ diff --git a/package/uboot-xburst/files/cpu/mips/jz_serial.c b/package/uboot-xburst/files/cpu/mips/jz_serial.c deleted file mode 100644 index e9a18a105b..0000000000 --- a/package/uboot-xburst/files/cpu/mips/jz_serial.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Jz47xx UART support - * - * Hardcoded to UART 0 for now - * Options also hardcoded to 8N1 - * - * Copyright (c) 2005 - * Ingenic Semiconductor, <jlwei@ingenic.cn> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> - -#if defined(CONFIG_JZ4740) - -#include <common.h> - -#include <asm/jz4740.h> - -#undef UART_BASE -#ifndef CONFIG_SYS_UART_BASE -#define UART_BASE UART0_BASE -#else -#define UART_BASE CONFIG_SYS_UART_BASE -#endif - -/****************************************************************************** -* -* serial_init - initialize a channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -int serial_init (void) -{ -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR); - volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); - volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER); - volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR); - - /* Disable port interrupts while changing hardware */ - *uart_ier = 0; - - /* Disable UART unit function */ - *uart_fcr = ~UART_FCR_UUE; - - /* Set both receiver and transmitter in UART mode (not SIR) */ - *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE); - - /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ - *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1; - - /* Set baud rate */ - serial_setbrg(); - - /* Enable UART unit, enable and clear FIFO */ - *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS; -#endif - return 0; -} - -void serial_setbrg (void) -{ - volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR); - volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR); - volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR); - u32 baud_div, tmp; - - baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE; - - tmp = *uart_lcr; - tmp |= UART_LCR_DLAB; - *uart_lcr = tmp; - - *uart_dlhr = (baud_div >> 8) & 0xff; - *uart_dllr = baud_div & 0xff; - - tmp &= ~UART_LCR_DLAB; - *uart_lcr = tmp; -} - -void serial_putc (const char c) -{ - volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR); - volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR); - - if (c == '\n') serial_putc ('\r'); - - /* Wait for fifo to shift out some bytes */ - while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) ); - - *uart_tdr = (u8)c; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR); - - while (!serial_tstc()); - - return *uart_rdr; -} - -int serial_tstc (void) -{ - volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR); - - if (*uart_lsr & UART_LSR_DR) { - /* Data in rfifo */ - return (1); - } - return 0; -} - -#endif diff --git a/package/uboot-xburst/files/cpu/mips/mmc_protocol.h b/package/uboot-xburst/files/cpu/mips/mmc_protocol.h deleted file mode 100644 index ebd59125b6..0000000000 --- a/package/uboot-xburst/files/cpu/mips/mmc_protocol.h +++ /dev/null @@ -1,273 +0,0 @@ -/* -********************************************************************** -* -* uC/MMC -* -* (c) Copyright 2005 - 2007, Ingenic Semiconductor, Inc -* All rights reserved. -* -*********************************************************************** - ----------------------------------------------------------------------- -File : mmc_protocol.h -Purpose : MMC protocol definitions. - ----------------------------------------------------------------------- -Version-Date-----Author-Explanation ----------------------------------------------------------------------- -1.00.00 20060831 WeiJianli First release - ----------------------------------------------------------------------- -Known problems or limitations with current version ----------------------------------------------------------------------- -(none) ----------------------------END-OF-HEADER------------------------------ -*/ - -#ifndef __MMC_PROTOCOL__ -#define __MMC_PROTOCOL__ - -/* Standard MMC/SD clock speeds */ -#define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */ -#define MMC_CLOCK_FAST 20000000 /* 20 MHz for maximum for normal operation */ -#define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */ - -/* Extra MMC commands for state control */ -/* Use negative numbers to disambiguate */ -#define MMC_CIM_RESET -1 - -/* Standard MMC commands (3.1) type argument response */ - /* class 1 */ -#define MMC_GO_IDLE_STATE 0 /* bc */ -#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ -#define MMC_ALL_SEND_CID 2 /* bcr R2 */ -#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ -#define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ -#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ -#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ -#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ -#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ -#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ -#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ - - /* class 2 */ -#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ -#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ -#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ - - /* class 3 */ -#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ - - /* class 4 */ -#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ -#define MMC_PROGRAM_CID 26 /* adtc R1 */ -#define MMC_PROGRAM_CSD 27 /* adtc R1 */ - - /* class 6 */ -#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ -#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ -#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ - - /* class 5 */ -#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ -#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ -#define MMC_ERASE 37 /* ac R1b */ - - /* class 9 */ -#define MMC_FAST_IO 39 /* ac <Complex> R4 */ -#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ - - /* class 7 */ -#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ - - /* class 8 */ -#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ -#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */ - - /* SD class */ -#define SD_SEND_OP_COND 41 /* bcr [31:0] OCR R3 */ -#define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ -#define SEND_SCR 51 /* adtc [31:0] staff R1 */ - -/* Don't change the order of these; they are used in dispatch tables */ -enum mmc_rsp_t { - RESPONSE_NONE = 0, - RESPONSE_R1 = 1, - RESPONSE_R1B = 2, - RESPONSE_R2_CID = 3, - RESPONSE_R2_CSD = 4, - RESPONSE_R3 = 5, - RESPONSE_R4 = 6, - RESPONSE_R5 = 7, - RESPONSE_R6 = 8, -}; - - -/* - MMC status in R1 - Type - e : error bit - s : status bit - r : detected and set for the actual command response - x : detected and set during command execution. the host must poll - the card by sending status command in order to read these bits. - Clear condition - a : according to the card state - b : always related to the previous command. Reception of - a valid command will clear it (with a delay of one command) - c : clear by read - */ - -#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ -#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ -#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ -#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ -#define R1_ERASE_PARAM (1 << 27) /* ex, c */ -#define R1_WP_VIOLATION (1 << 26) /* erx, c */ -#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ -#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ -#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ -#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ -#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ -#define R1_CC_ERROR (1 << 20) /* erx, c */ -#define R1_ERROR (1 << 19) /* erx, c */ -#define R1_UNDERRUN (1 << 18) /* ex, c */ -#define R1_OVERRUN (1 << 17) /* ex, c */ -#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ -#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ -#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ -#define R1_ERASE_RESET (1 << 13) /* sr, c */ -#define R1_STATUS(x) (x & 0xFFFFE000) -#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ -#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ -#define R1_APP_CMD (1 << 7) /* sr, c */ - -enum card_state { - CARD_STATE_EMPTY = -1, - CARD_STATE_IDLE = 0, - CARD_STATE_READY = 1, - CARD_STATE_IDENT = 2, - CARD_STATE_STBY = 3, - CARD_STATE_TRAN = 4, - CARD_STATE_DATA = 5, - CARD_STATE_RCV = 6, - CARD_STATE_PRG = 7, - CARD_STATE_DIS = 8, -}; - -/* These are unpacked versions of the actual responses */ - - struct mmc_response_r1 { - u8 cmd; - u32 status; -}; - -typedef struct mmc_cid { - u8 mid; - u16 oid; - u8 pnm[7]; /* Product name (we null-terminate) */ - u8 prv; - u32 psn; - u8 mdt; -}mmc_cid_t; - -typedef struct mmc_csd { - u8 csd_structure; - u8 spec_vers; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc; - u8 read_bl_len; - u8 read_bl_partial; - u8 write_blk_misalign; - u8 read_blk_misalign; - u8 dsr_imp; - u16 c_size; - u8 vdd_r_curr_min; - u8 vdd_r_curr_max; - u8 vdd_w_curr_min; - u8 vdd_w_curr_max; - u8 c_size_mult; - union { - struct { /* MMC system specification version 3.1 */ - u8 erase_grp_size; - u8 erase_grp_mult; - } v31; - struct { /* MMC system specification version 2.2 */ - u8 sector_size; - u8 erase_grp_size; - } v22; - } erase; - u8 wp_grp_size; - u8 wp_grp_enable; - u8 default_ecc; - u8 r2w_factor; - u8 write_bl_len; - u8 write_bl_partial; - u8 file_format_grp; - u8 copy; - u8 perm_write_protect; - u8 tmp_write_protect; - u8 file_format; - u8 ecc; -}mmc_csd_t;; - -struct mmc_response_r3 { - u32 ocr; -}; - -#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */ -#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */ -#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */ -#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */ -#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */ -#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */ -#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */ -#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */ -#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ -#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ -#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ -#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ -#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ -#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ -#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ -#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ -#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ -#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ -#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ -#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ -#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ -#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ -#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ -#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ -#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ - - -/* CSD field definitions */ - -#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ -#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ -#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */ - -#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ -#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ -#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ -#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */ - -#if MMC_DEBUG_LEVEL - -#define DEBUG(n, args...) \ - do { \ - if (n <= MMC_DEBUG_LEVEL) { \ - printf(args); \ - } \ - } while(0) -#else -#define DEBUG(n, args...) -#endif /* MMC_DEBUG_EN */ - -#endif /* __MMC_PROTOCOL__ */ diff --git a/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c b/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c deleted file mode 100644 index 4c98d29439..0000000000 --- a/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c +++ /dev/null @@ -1,420 +0,0 @@ -/* - * JzRISC lcd controller - * - * xiangfu liu <xiangfu.z@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <lcd.h> - -#include <asm/io.h> /* virt_to_phys() */ - -#include <asm/jz4740.h> -#include "nanonote_gpm940b0.h" - -#define align2(n) (n)=((((n)+1)>>1)<<1) -#define align4(n) (n)=((((n)+3)>>2)<<2) -#define align8(n) (n)=((((n)+7)>>3)<<3) - -struct jzfb_info { - unsigned int cfg; /* panel mode and pin usage etc. */ - unsigned int w; - unsigned int h; - unsigned int bpp; /* bit per pixel */ - unsigned int fclk; /* frame clk */ - unsigned int hsw; /* hsync width, in pclk */ - unsigned int vsw; /* vsync width, in line count */ - unsigned int elw; /* end of line, in pclk */ - unsigned int blw; /* begin of line, in pclk */ - unsigned int efw; /* end of frame, in line count */ - unsigned int bfw; /* begin of frame, in line count */ -}; - -static struct jzfb_info jzfb = { - MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, - 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 -}; - -vidinfo_t panel_info = { - 320, 240, LCD_BPP, -}; - -int lcd_line_length; - -int lcd_color_fg; -int lcd_color_bg; -/* - * Frame buffer memory information - */ -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); -void lcd_disable (void); - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); -static void jz_lcd_desc_init(vidinfo_t *vid); -static int jz_lcd_hw_init( vidinfo_t *vid ); -extern int flush_cache_all(void); - -void lcd_ctrl_init (void *lcdbase) -{ - __lcd_display_pin_init(); - - jz_lcd_init_mem(lcdbase, &panel_info); - jz_lcd_desc_init(&panel_info); - jz_lcd_hw_init(&panel_info); - - __lcd_display_on() ; -} - -/* - * Before enabled lcd controller, lcd registers should be configured correctly. - */ - -void lcd_enable (void) -{ - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ -} - -void lcd_disable (void) -{ - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ - /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ -} - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) -{ - u_long palette_mem_size; - struct jz_fb_info *fbi = &vid->jz_fb; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (u_long)lcdbase; - fbi->palette_size = 256; - palette_mem_size = fbi->palette_size * sizeof(u16); - - debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); - /* locate palette and descs at end of page following fb */ - fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} - -static void jz_lcd_desc_init(vidinfo_t *vid) -{ - struct jz_fb_info * fbi; - fbi = &vid->jz_fb; - fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); - fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; - - fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ - - fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); - - if(NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); - fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); - } else { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ - } - - flush_cache_all(); -} - -static int jz_lcd_hw_init(vidinfo_t *vid) -{ - struct jz_fb_info *fbi = &vid->jz_fb; - unsigned int val = 0; - unsigned int pclk; - unsigned int stnH; - int pll_div; - - /* Setting Control register */ - switch (jzfb.bpp) { - case 1: - val |= LCD_CTRL_BPP_1; - break; - case 2: - val |= LCD_CTRL_BPP_2; - break; - case 4: - val |= LCD_CTRL_BPP_4; - break; - case 8: - val |= LCD_CTRL_BPP_8; - break; - case 15: - val |= LCD_CTRL_RGB555; - case 16: - val |= LCD_CTRL_BPP_16; - break; - case 17 ... 32: - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ - break; - - default: - printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); - val |= LCD_CTRL_BPP_16; - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.bpp) { - case 1: - /* val |= LCD_CTRL_PEDN; */ - case 2: - val |= LCD_CTRL_FRC_2; - break; - case 4: - val |= LCD_CTRL_FRC_4; - break; - case 8: - default: - val |= LCD_CTRL_FRC_16; - break; - } - break; - } - - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.cfg & STN_DAT_PINMASK) { - case STN_DAT_PIN1: - /* Do not adjust the hori-param value. */ - break; - case STN_DAT_PIN2: - align2(jzfb.hsw); - align2(jzfb.elw); - align2(jzfb.blw); - break; - case STN_DAT_PIN4: - align4(jzfb.hsw); - align4(jzfb.elw); - align4(jzfb.blw); - break; - case STN_DAT_PIN8: - align8(jzfb.hsw); - align8(jzfb.elw); - align8(jzfb.blw); - break; - } - break; - } - - REG_LCD_CTRL = val; - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - stnH = jzfb.h >> 1; - else - stnH = jzfb.h; - - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); - - /* Screen setting */ - REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); - REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); - REG_LCD_DAV = (0 << 16) | (stnH); - - /* AC BIAs signal */ - REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); - - break; - - case MODE_TFT_GEN: - case MODE_TFT_SHARP: - case MODE_TFT_CASIO: - case MODE_TFT_SAMSUNG: - case MODE_8BIT_SERIAL_TFT: - case MODE_TFT_18BIT: - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; - REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); - REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); - REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ - | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_TFT_SAMSUNG: - { - unsigned int total, tp_s, tp_e, ckv_s, ckv_e; - unsigned int rev_s, rev_e, inv_s, inv_e; - - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - tp_s = jzfb.blw + jzfb.w + 1; - tp_e = tp_s + 1; - /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ - ckv_s = tp_s - pclk/(1000000000/4100); - ckv_e = tp_s + total; - rev_s = tp_s - 11; /* -11.5 clk */ - rev_e = rev_s + total; - inv_s = tp_s; - inv_e = inv_s + total; - REG_LCD_CLS = (tp_s << 16) | tp_e; - REG_LCD_PS = (ckv_s << 16) | ckv_e; - REG_LCD_SPL = (rev_s << 16) | rev_e; - REG_LCD_REV = (inv_s << 16) | inv_e; - jzfb.cfg |= STFT_REVHI | STFT_SPLHI; - break; - } - case MODE_TFT_SHARP: - { - unsigned int total, cls_s, cls_e, ps_s, ps_e; - unsigned int spl_s, spl_e, rev_s, rev_e; - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - spl_s = 1; - spl_e = spl_s + 1; - cls_s = 0; - cls_e = total - 60; /* > 4us (pclk = 80ns) */ - ps_s = cls_s; - ps_e = cls_e; - rev_s = total - 40; /* > 3us (pclk = 80ns) */ - rev_e = rev_s + total; - jzfb.cfg |= STFT_PSHI; - REG_LCD_SPL = (spl_s << 16) | spl_e; - REG_LCD_CLS = (cls_s << 16) | cls_e; - REG_LCD_PS = (ps_s << 16) | ps_e; - REG_LCD_REV = (rev_s << 16) | rev_e; - break; - } - case MODE_TFT_CASIO: - break; - } - - /* Configure the LCD panel */ - REG_LCD_CFG = jzfb.cfg; - - /* Timing setting */ - __cpm_stop_lcd(); - - val = jzfb.fclk; /* frame clk */ - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } else { - /* serial mode: Hsync period = 3*Width_Pixel */ - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - pclk = (pclk * 3); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk >>= 1; - - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ - pll_div = pll_div ? 1 : 2 ; - val = ( __cpm_get_pllout()/pll_div ) / pclk; - val--; - if ( val > 0x1ff ) { - printf("CPM_LPCDR too large, set it to 0x1ff\n"); - val = 0x1ff; - } - __cpm_set_pixdiv(val); - - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ - if ( val > 150000000 ) { - printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); - printf("Change LCDClock to 150MHz\n"); - val = 150000000; - } - val = ( __cpm_get_pllout()/pll_div ) / val; - val--; - if ( val > 0x1f ) { - printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); - val = 0x1f; - } - __cpm_set_ldiv( val ); - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ - - __cpm_start_lcd(); - udelay(1000); - - REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ - - return 0; -} - -void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ -} - -void lcd_initcolregs (void) -{ -} diff --git a/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h b/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h deleted file mode 100644 index 8ff78ada24..0000000000 --- a/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * JzRISC lcd controller - * - * xiangfu liu <xiangfu.z@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __QI_LB60_GPM940B0_H__ -#define __QI_LB60_GPM940B0_H__ - -#include <asm/io.h> - -#define mdelay(n) udelay((n)*1000) - -#define NR_PALETTE 256 - -struct lcd_desc{ - unsigned int next_desc; /* LCDDAx */ - unsigned int databuf; /* LCDSAx */ - unsigned int frame_id; /* LCDFIDx */ - unsigned int cmd; /* LCDCMDx */ -}; - -#define MODE_MASK 0x0f -#define MODE_TFT_GEN 0x00 -#define MODE_TFT_SHARP 0x01 -#define MODE_TFT_CASIO 0x02 -#define MODE_TFT_SAMSUNG 0x03 -#define MODE_CCIR656_NONINT 0x04 -#define MODE_CCIR656_INT 0x05 -#define MODE_STN_COLOR_SINGLE 0x08 -#define MODE_STN_MONO_SINGLE 0x09 -#define MODE_STN_COLOR_DUAL 0x0a -#define MODE_STN_MONO_DUAL 0x0b -#define MODE_8BIT_SERIAL_TFT 0x0c - -#define MODE_TFT_18BIT (1<<7) - -#define STN_DAT_PIN1 (0x00 << 4) -#define STN_DAT_PIN2 (0x01 << 4) -#define STN_DAT_PIN4 (0x02 << 4) -#define STN_DAT_PIN8 (0x03 << 4) -#define STN_DAT_PINMASK STN_DAT_PIN8 - -#define STFT_PSHI (1 << 15) -#define STFT_CLSHI (1 << 14) -#define STFT_SPLHI (1 << 13) -#define STFT_REVHI (1 << 12) - -#define SYNC_MASTER (0 << 16) -#define SYNC_SLAVE (1 << 16) - -#define DE_P (0 << 9) -#define DE_N (1 << 9) - -#define PCLK_P (0 << 10) -#define PCLK_N (1 << 10) - -#define HSYNC_P (0 << 11) -#define HSYNC_N (1 << 11) - -#define VSYNC_P (0 << 8) -#define VSYNC_N (1 << 8) - -#define DATA_NORMAL (0 << 17) -#define DATA_INVERSE (1 << 17) - - -/* Jz LCDFB supported I/O controls. */ -#define FBIOSETBACKLIGHT 0x4688 -#define FBIODISPON 0x4689 -#define FBIODISPOFF 0x468a -#define FBIORESET 0x468b -#define FBIOPRINT_REG 0x468c - -/* - * LCD panel specific definition - */ -#define MODE 0xc9 /* 8bit serial RGB */ -#define SPEN (32*2+21) /*LCD_SPL */ -#define SPCK (32*2+23) /*LCD_CLS */ -#define SPDA (32*2+22) /*LCD_D12 */ -#define LCD_RET (32*3+27) - -#define __spi_write_reg1(reg, val) \ -do { \ - unsigned char no;\ - unsigned short value;\ - unsigned char a=0;\ - unsigned char b=0;\ - a=reg;\ - b=val;\ - __gpio_set_pin(SPEN);\ - __gpio_set_pin(SPCK);\ - __gpio_clear_pin(SPDA);\ - __gpio_clear_pin(SPEN);\ - udelay(25);\ - value=((a<<8)|(b&0xFF));\ - for(no=0;no<16;no++)\ - {\ - __gpio_clear_pin(SPCK);\ - if((value&0x8000)==0x8000)\ - __gpio_set_pin(SPDA);\ - else\ - __gpio_clear_pin(SPDA);\ - udelay(25);\ - __gpio_set_pin(SPCK);\ - value=(value<<1); \ - udelay(25);\ - }\ - __gpio_set_pin(SPEN);\ - udelay(100);\ -} while (0) - -#define __spi_write_reg(reg, val) \ -do {\ - __spi_write_reg1((reg<<2|2), val);\ - udelay(100); \ -}while(0) - -#define __lcd_special_pin_init() \ -do { \ - __gpio_as_output(SPEN); /* use SPDA */\ - __gpio_as_output(SPCK); /* use SPCK */\ - __gpio_as_output(SPDA); /* use SPDA */\ - __gpio_as_output(LCD_RET);\ -} while (0) - -#define __lcd_special_on() \ -do { \ - __spi_write_reg1(0x05, 0x1e); \ - udelay(50);\ - __spi_write_reg1(0x05, 0x5d); \ - __spi_write_reg1(0x0B, 0x81); \ - __spi_write_reg1(0x01, 0x95); \ - __spi_write_reg1(0x00, 0x07); \ - __spi_write_reg1(0x06, 0x15); \ - __spi_write_reg1(0x07, 0x8d); \ - __spi_write_reg1(0x04, 0x0f); \ - __spi_write_reg1(0x0d, 0x3d); \ - __spi_write_reg1(0x10, 0x42); \ - __spi_write_reg1(0x11, 0x3a); \ - __spi_write_reg1(0x05, 0x5f); \ -} while (0) - -#define __lcd_special_off() \ -do { \ - __spi_write_reg1(0x05, 0x5e); \ -} while (0) - -#define __lcd_display_pin_init() \ -do { \ - __lcd_special_pin_init();\ - __gpio_as_pwm();\ - __lcd_set_backlight_level(8);\ -} while (0) - -#define __lcd_display_on() \ -do { \ - __lcd_set_backlight_level(8); \ - __lcd_special_on();\ -} while (0) - -#define __lcd_display_off() \ -do { \ - __lcd_set_backlight_level(0); \ - __lcd_special_off();\ -} while (0) - -#define __lcd_set_backlight_level(n)\ -do { \ - __gpio_as_output(LCD_RET); \ - __gpio_set_pin(LCD_RET); \ -} while (0) - -#if defined(CONFIG_SAKC) -#define __lcd_close_backlight() \ -do { \ - __gpio_as_output(GPIO_PWM); \ - __gpio_clear_pin(GPIO_PWM); \ -} while (0) -#endif - -#if defined(CONFIG_SAKC) -#define __lcd_display_pin_init() \ -do { \ - __cpm_start_tcu(); \ - __lcd_special_pin_init(); \ -} while (0) - -#define __lcd_display_on() \ -do { \ - __lcd_special_on(); \ -} while (0) - -#define __lcd_display_off() \ -do { \ - __lcd_special_off(); \ -} while (0) -#else -#define __lcd_display_pin_init() \ -do { \ - __cpm_start_tcu(); \ - __lcd_special_pin_init(); \ -} while (0) - -#define __lcd_display_on() \ -do { \ - __gpio_set_pin(GPIO_DISP_OFF_N); \ - __lcd_special_on(); \ -} while (0) - -#define __lcd_display_off() \ -do { \ - __lcd_special_off(); \ - __gpio_clear_pin(GPIO_DISP_OFF_N); \ -} while (0) -#endif - -#endif /* __QI_LB60_GPM940B0_H__ */ diff --git a/package/uboot-xburst/files/cpu/mips/usb_boot.S b/package/uboot-xburst/files/cpu/mips/usb_boot.S deleted file mode 100644 index 107b928c71..0000000000 --- a/package/uboot-xburst/files/cpu/mips/usb_boot.S +++ /dev/null @@ -1,880 +0,0 @@ -/* - * for jz4740 usb boot - * - * Copyright (c) 2009 Xiangfu Liu <xiangfu.z@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - .set noreorder - .globl usb_boot - .text - -//---------------------------------------------------------------------- -// Both NAND and USB boot load data to D-Cache first, then transfer -// data from D-Cache to I-Cache, and jump to execute the code in I-Cache. -// So init caches first and then dispatch to a proper boot routine. -//---------------------------------------------------------------------- - -.macro load_addr reg addr - li \reg, 0x80000000 - addiu \reg, \reg, \addr - la $2, usbboot_begin - subu \reg, \reg, $2 -.endm - -usb_boot: - //-------------------------------------------------------------- - // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. - //-------------------------------------------------------------- - la $9, 0xB0000000 // CPCCR: Clock Control Register - la $8, 0x42041110 // I:S:M:P=1:2:2:2 - sw $8, 0($9) - - la $9, 0xB0000010 // CPPCR: PLL Control Register - la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2) - sw $8, 0($9) - - mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state - nop - - mtc0 $0, $16 // CP0_CONFIG - nop - - // Relocate code to beginning of the ram - - la $2, usbboot_begin - la $3, usbboot_end - li $4, 0x80000000 - -1: - lw $5, 0($2) - sw $5, 0($4) - addiu $2, $2, 4 - bne $2, $3, 1b - addiu $4, $4, 4 - - li $2, 0x80000000 - ori $3, $2, 0 - addiu $3, $3, usbboot_end - la $4, usbboot_begin - subu $3, $3, $4 - - -2: - cache 0x0, 0($2) // Index_Invalidate_I - cache 0x1, 0($2) // Index_Writeback_Inv_D - addiu $2, $2, 32 - subu $4, $3, $2 - bgtz $4, 2b - nop - - load_addr $3, usb_boot_return - - jr $3 - -usbboot_begin: - -init_caches: - li $2, 3 // cacheable for kseg0 access - mtc0 $2, $16 // CP0_CONFIG - nop - - li $2, 0x20000000 // enable idx-store-data cache insn - mtc0 $2, $26 // CP0_ERRCTL - - ori $2, $28, 0 // start address - ori $3, $2, 0x3fe0 // end address, total 16KB - mtc0 $0, $28, 0 // CP0_TAGLO - mtc0 $0, $28, 1 // CP0_DATALO -cache_clear_a_line: - cache 0x8, 0($2) // Index_Store_Tag_I - cache 0x9, 0($2) // Index_Store_Tag_D - bne $2, $3, cache_clear_a_line - addiu $2, $2, 32 // increment CACHE_LINE_SIZE - - ori $2, $28, 0 // start address - ori $3, $2, 0x3fe0 // end address, total 16KB - la $4, 0x1ffff000 // physical address and 4KB page mask -cache_alloc_a_line: - and $5, $2, $4 - ori $5, $5, 1 // V bit of the physical tag - mtc0 $5, $28, 0 // CP0_TAGLO - cache 0x8, 0($2) // Index_Store_Tag_I - cache 0x9, 0($2) // Index_Store_Tag_D - bne $2, $3, cache_alloc_a_line - addiu $2, $2, 32 // increment CACHE_LINE_SIZE - - nop - nop - nop - //-------------------------------------------------------------- - // Transfer data from dcache to icache, then jump to icache. - // - // Input parameters: - // - // $19: data length in bytes - // $20: jump target address - //-------------------------------------------------------------- -xfer_d2i: - - ori $8, $20, 0 - addu $9, $8, $19 // total 16KB - -1: - cache 0x0, 0($8) // Index_Invalidate_I - cache 0x1, 0($8) // Index_Writeback_Inv_D - bne $8, $9, 1b - addiu $8, $8, 32 - - // flush write-buffer - sync - - // Invalidate BTB - mfc0 $8, $16, 7 // CP0_CONFIG - nop - ori $8, 2 - mtc0 $8, $16, 7 - nop - - // Overwrite config to disable ram initalisation - li $2, 0xff - sb $2, 20($20) - - jalr $20 - nop - -icache_return: - //-------------------------------------------------------------- - // User code can return to here after executing itself in - // icache, by jumping to $31. - //-------------------------------------------------------------- - b usb_boot_return - nop - - -usb_boot_return: - //-------------------------------------------------------------- - // Enable the USB PHY - //-------------------------------------------------------------- - la $9, 0xB0000024 // CPM_SCR - lw $8, 0($9) - ori $8, 0x40 // USBPHY_ENABLE - sw $8, 0($9) - - //-------------------------------------------------------------- - // Initialize USB registers - //-------------------------------------------------------------- - la $27, 0xb3040000 // USB registers base address - - sb $0, 0x0b($27) // INTRUSBE: disable common USB interrupts - sh $0, 0x06($27) // INTRINE: disable EPIN interrutps - sh $0, 0x08($27) // INTROUTE: disable EPOUT interrutps - - li $9, 0x61 - sb $9, 0x01($27) // POWER: HSENAB | SUSPENDM | SOFTCONN - - //-------------------------------------------------------------- - // Initialize USB states - //-------------------------------------------------------------- - li $22, 0 // set EP0 to IDLE state - li $23, 1 // no data stage - - //-------------------------------------------------------------- - // Main loop of polling the usb commands - //-------------------------------------------------------------- -usb_command_loop: - lbu $9, 0x0a($27) // read INTRUSB - andi $9, 0x04 // check USB_INTR_RESET - beqz $9, check_intr_ep0in - nop - - //-------------------------------------------------------------- - // 1. Handle USB reset interrupt - //-------------------------------------------------------------- -handle_reset_intr: - lbu $9, 0x01($27) // read POWER - andi $9, 0x10 // test HS_MODE - bnez $9, _usb_set_maxpktsize - li $9, 512 // max packet size of HS mode - li $9, 64 // max packet size of FS mode - -_usb_set_maxpktsize: - li $8, 1 - sb $8, 0x0e($27) // set INDEX 1 - - sh $9, 0x10($27) // INMAXP - sb $0, 0x13($27) // INCSRH - sh $9, 0x14($27) // OUTMAXP - sb $0, 0x17($27) // OUTCSRH - -_usb_flush_fifo: - li $8, 0x48 // INCSR_CDT && INCSR_FF - sb $8, 0x12($27) // INCSR - li $8, 0x90 // OUTCSR_CDT && OUTCSR_FF - sb $8, 0x16($27) // OUTCSR - - li $22, 0 // set EP0 to IDLE state - li $23, 1 // no data stage - - //-------------------------------------------------------------- - // 2. Check and handle EP0 interrupt - //-------------------------------------------------------------- -check_intr_ep0in: - lhu $10, 0x02($27) // read INTRIN - andi $9, $10, 0x1 // check EP0 interrupt - beqz $9, check_intr_ep1in - nop - -handle_ep0_intr: - sb $0, 0x0e($27) // set INDEX 0 - lbu $11, 0x12($27) // read CSR0 - - andi $9, $11, 0x04 // check SENTSTALL - beqz $9, _ep0_setupend - nop - -_ep0_sentstall: - andi $9, $11, 0xdb - sb $9, 0x12($27) // clear SENDSTALL and SENTSTALL - li $22, 0 // set EP0 to IDLE state - -_ep0_setupend: - andi $9, $11, 0x10 // check SETUPEND - beqz $9, ep0_idle_state - nop - - ori $9, $11, 0x80 - sb $9, 0x12($27) // set SVDSETUPEND - li $22, 0 // set EP0 to IDLE state - -ep0_idle_state: - bnez $22, ep0_tx_state - nop - - //-------------------------------------------------------------- - // 2.1 Handle EP0 IDLE state interrupt - //-------------------------------------------------------------- - andi $9, $11, 0x01 // check OUTPKTRDY - beqz $9, check_intr_ep1in - nop - - //-------------------------------------------------------------- - // Read 8-bytes setup packet from the FIFO - //-------------------------------------------------------------- - lw $25, 0x20($27) // first word of setup packet - lw $26, 0x20($27) // second word of setup packet - - andi $9, $25, 0x60 // bRequestType & USB_TYPE_MASK - beqz $9, _ep0_std_req - nop - - //-------------------------------------------------------------- - // 2.1.1 Vendor-specific setup request - //-------------------------------------------------------------- -_ep0_vend_req: - li $22, 0 // set EP0 to IDLE state - li $23, 1 // NoData = 1 - - andi $9, $25, 0xff00 // check bRequest - srl $9, $9, 8 - beqz $9, __ep0_get_cpu_info - sub $8, $9, 0x1 - beqz $8, __ep0_set_data_address - sub $8, $9, 0x2 - beqz $8, __ep0_set_data_length - sub $8, $9, 0x3 - beqz $8, __ep0_flush_caches - sub $8, $9, 0x4 - beqz $8, __ep0_prog_start1 - sub $8, $9, 0x5 - beqz $8, __ep0_prog_start2 - nop - b _ep0_idle_state_fini // invalid request - nop - -__ep0_get_cpu_info: - load_addr $20, cpu_info_data // data pointer to transfer - li $21, 8 // bytes left to transfer - li $22, 1 // set EP0 to TX state - li $23, 0 // NoData = 0 - - b _ep0_idle_state_fini - nop - -__ep0_set_data_address: - li $9, 0xffff0000 - and $9, $25, $9 - andi $8, $26, 0xffff - or $20, $9, $8 // data address of next transfer - - b _ep0_idle_state_fini - nop - -__ep0_set_data_length: - li $9, 0xffff0000 - and $9, $25, $9 - andi $8, $26, 0xffff - or $21, $9, $8 // data length of next transfer - - li $9, 0x48 // SVDOUTPKTRDY and DATAEND - sb $9, 0x12($27) // CSR0 - - // We must write packet to FIFO before EP1-IN interrupt here. - b handle_epin1_intr - nop - -__ep0_flush_caches: - // Flush dcache and invalidate icache. - li $8, 0x80000000 - addi $9, $8, 0x3fe0 // total 16KB - -1: - cache 0x0, 0($8) // Index_Invalidate_I - cache 0x1, 0($8) // Index_Writeback_Inv_D - bne $8, $9, 1b - addiu $8, $8, 32 - - // flush write-buffer - sync - - // Invalidate BTB - mfc0 $8, $16, 7 // CP0_CONFIG - nop - ori $8, 2 - mtc0 $8, $16, 7 - nop - - b _ep0_idle_state_fini - nop - -__ep0_prog_start1: - li $9, 0x48 // SVDOUTPKTRDY and DATAEND - sb $9, 0x12($27) // CSR0 - - li $9, 0xffff0000 - and $9, $25, $9 - andi $8, $26, 0xffff - or $20, $9, $8 // target address - - b xfer_d2i - li $19, 0x2000 // 16KB data length - -__ep0_prog_start2: - li $9, 0x48 // SVDOUTPKTRDY and DATAEND - sb $9, 0x12($27) // CSR0 - - li $9, 0xffff0000 - and $9, $25, $9 - andi $8, $26, 0xffff - or $20, $9, $8 // target address - - jalr $20 // jump, and place the return address in $31 - nop - -__ep0_prog_start2_return: - // User code can return to here after executing itself, by jumping to $31. - b usb_boot_return - nop - - //-------------------------------------------------------------- - // 2.1.2 Standard setup request - //-------------------------------------------------------------- -_ep0_std_req: - andi $12, $25, 0xff00 // check bRequest - srl $12, $12, 8 - sub $9, $12, 0x05 // check USB_REQ_SET_ADDRESS - bnez $9, __ep0_req_set_config - nop - - //-------------------------------------------------------------- - // Handle USB_REQ_SET_ADDRESS - //-------------------------------------------------------------- -__ep0_req_set_addr: - srl $9, $25, 16 // get wValue - sb $9, 0x0($27) // set FADDR - li $23, 1 // NoData = 1 - b _ep0_idle_state_fini - nop - -__ep0_req_set_config: - sub $9, $12, 0x09 // check USB_REQ_SET_CONFIGURATION - bnez $9, __ep0_req_get_desc - nop - - //-------------------------------------------------------------- - // Handle USB_REQ_SET_CONFIGURATION - //-------------------------------------------------------------- - li $23, 1 // NoData = 1 - b _ep0_idle_state_fini - nop - -__ep0_req_get_desc: - sub $9, $12, 0x06 // check USB_REQ_GET_DESCRIPTOR - bnez $9, _ep0_idle_state_fini - li $23, 1 // NoData = 1 - - //-------------------------------------------------------------- - // Handle USB_REQ_GET_DESCRIPTOR - //-------------------------------------------------------------- - li $23, 0 // NoData = 0 - - srl $9, $25, 24 // wValue >> 8 - sub $8, $9, 0x01 // check USB_DT_DEVICE - beqz $8, ___ep0_get_dev_desc - srl $21, $26, 16 // get wLength - sub $8, $9, 0x02 // check USB_DT_CONFIG - beqz $8, ___ep0_get_conf_desc - sub $8, $9, 0x03 // check USB_DT_STRING - beqz $8, ___ep0_get_string_desc - sub $8, $9, 0x06 // check USB_DT_DEVICE_QUALIFIER - beqz $8, ___ep0_get_dev_qualifier - nop - b _ep0_idle_state_fini - nop - -___ep0_get_dev_desc: - load_addr $20, device_desc // data pointer - li $22, 1 // set EP0 to TX state - sub $8, $21, 18 - blez $8, _ep0_idle_state_fini // wLength <= 18 - nop - li $21, 18 // max length of device_desc - b _ep0_idle_state_fini - nop - -___ep0_get_dev_qualifier: - load_addr $20, dev_qualifier // data pointer - li $22, 1 // set EP0 to TX state - sub $8, $21, 10 - blez $8, _ep0_idle_state_fini // wLength <= 10 - nop - li $21, 10 // max length of dev_qualifier - b _ep0_idle_state_fini - nop - -___ep0_get_conf_desc: - load_addr $20, config_desc_fs // data pointer of FS mode - lbu $8, 0x01($27) // read POWER - andi $8, 0x10 // test HS_MODE - beqz $8, ___ep0_get_conf_desc2 - nop - load_addr $20, config_desc_hs // data pointer of HS mode - -___ep0_get_conf_desc2: - li $22, 1 // set EP0 to TX state - sub $8, $21, 32 - blez $8, _ep0_idle_state_fini // wLength <= 32 - nop - li $21, 32 // max length of config_desc - b _ep0_idle_state_fini - nop - -___ep0_get_string_desc: - li $22, 1 // set EP0 to TX state - - srl $9, $25, 16 // wValue & 0xff - andi $9, 0xff - - sub $8, $9, 1 - beqz $8, ___ep0_get_string_manufacture - sub $8, $9, 2 - beqz $8, ___ep0_get_string_product - nop - -___ep0_get_string_lang_ids: - load_addr $20, string_lang_ids // data pointer - b _ep0_idle_state_fini - li $21, 4 // data length - -___ep0_get_string_manufacture: - load_addr $20, string_manufacture // data pointer - b _ep0_idle_state_fini - li $21, 16 // data length - -___ep0_get_string_product: - load_addr $20, string_product // data pointer - b _ep0_idle_state_fini - li $21, 46 // data length - -_ep0_idle_state_fini: - li $9, 0x40 // SVDOUTPKTRDY - beqz $23, _ep0_idle_state_fini2 - nop - ori $9, $9, 0x08 // DATAEND -_ep0_idle_state_fini2: - sb $9, 0x12($27) // CSR0 - beqz $22, check_intr_ep1in - nop - - //-------------------------------------------------------------- - // 2.2 Handle EP0 TX state interrupt - //-------------------------------------------------------------- -ep0_tx_state: - sub $9, $22, 1 - bnez $9, check_intr_ep1in - nop - - sub $9, $21, 64 // max packetsize - blez $9, _ep0_tx_state2 // data count <= 64 - ori $19, $21, 0 - li $19, 64 - -_ep0_tx_state2: - beqz $19, _ep0_tx_state3 // send ZLP - ori $18, $19, 0 // record bytes to be transferred - sub $21, $21, $19 // decrement data count - -_ep0_fifo_write_loop: - lbu $9, 0($20) // read data - sb $9, 0x20($27) // load FIFO - sub $19, $19, 1 // decrement counter - bnez $19, _ep0_fifo_write_loop - addi $20, $20, 1 // increment data pointer - - sub $9, $18, 64 // max packetsize - beqz $9, _ep0_tx_state4 - nop - -_ep0_tx_state3: - // transferred bytes < max packetsize - li $9, 0x0a // set INPKTRDY and DATAEND - sb $9, 0x12($27) // CSR0 - li $22, 0 // set EP0 to IDLE state - b check_intr_ep1in - nop - -_ep0_tx_state4: - // transferred bytes == max packetsize - li $9, 0x02 // set INPKTRDY - sb $9, 0x12($27) // CSR0 - b check_intr_ep1in - nop - - //-------------------------------------------------------------- - // 3. Check and handle EP1 BULK-IN interrupt - //-------------------------------------------------------------- -check_intr_ep1in: - andi $9, $10, 0x2 // check EP1 IN interrupt - beqz $9, check_intr_ep1out - nop - -handle_epin1_intr: - li $9, 1 - sb $9, 0x0e($27) // set INDEX 1 - lbu $9, 0x12($27) // read INCSR - - andi $8, $9, 0x2 // check INCSR_FFNOTEMPT - bnez $8, _epin1_tx_state4 - nop - -_epin1_write_fifo: - lhu $9, 0x10($27) // get INMAXP - sub $8, $21, $9 - blez $8, _epin1_tx_state1 // bytes left <= INMAXP - ori $19, $21, 0 - ori $19, $9, 0 - -_epin1_tx_state1: - beqz $19, _epin1_tx_state4 // No data - nop - - sub $21, $21, $19 // decrement data count - - srl $5, $19, 2 // # of word - andi $6, $19, 0x3 // # of byte - beqz $5, _epin1_tx_state2 - nop - -_epin1_fifo_write_word: - lw $9, 0($20) // read data from source address - sw $9, 0x24($27) // write FIFO - sub $5, $5, 1 // decrement counter - bnez $5, _epin1_fifo_write_word - addiu $20, $20, 4 // increment dest address - -_epin1_tx_state2: - beqz $6, _epin1_tx_state3 - nop - -_epin1_fifo_write_byte: - lbu $9, 0($20) // read data from source address - sb $9, 0x24($27) // write FIFO - sub $6, $6, 1 // decrement counter - bnez $6, _epin1_fifo_write_byte - addiu $20, $20, 1 // increment dest address - -_epin1_tx_state3: - li $9, 0x1 - sb $9, 0x12($27) // INCSR, set INPKTRDY - -_epin1_tx_state4: - // nop - - //-------------------------------------------------------------- - // 4. Check and handle EP1 BULK-OUT interrupt - //-------------------------------------------------------------- -check_intr_ep1out: - lhu $9, 0x04($27) // read INTROUT - andi $9, 0x2 - beqz $9, check_status_next - nop - -handle_epout1_intr: - li $9, 1 - sb $9, 0x0e($27) // set INDEX 1 - - lbu $9, 0x16($27) // read OUTCSR - andi $9, 0x1 // check OUTPKTRDY - beqz $9, check_status_next - nop - -_epout1_read_fifo: - lhu $19, 0x18($27) // read OUTCOUNT - srl $5, $19, 2 // # of word - andi $6, $19, 0x3 // # of byte - beqz $5, _epout1_rx_state1 - nop - -_epout1_fifo_read_word: - lw $9, 0x24($27) // read FIFO - sw $9, 0($20) // store to dest address - sub $5, $5, 1 // decrement counter - bnez $5, _epout1_fifo_read_word - addiu $20, $20, 4 // increment dest address - -_epout1_rx_state1: - beqz $6, _epout1_rx_state2 - nop - -_epout1_fifo_read_byte: - lbu $9, 0x24($27) // read FIFO - sb $9, 0($20) // store to dest address - sub $6, $6, 1 // decrement counter - bnez $6, _epout1_fifo_read_byte - addiu $20, $20, 1 // increment dest address - -_epout1_rx_state2: - sb $0, 0x16($27) // clear OUTPKTRDY - -check_status_next: - b usb_command_loop - nop - -//-------------------------------------------------------------- -// Device/Configuration/Interface/Endpoint/String Descriptors -//-------------------------------------------------------------- - - .align 2 -device_desc: - .byte 0x12 // bLength - .byte 0x01 // bDescriptorType - .byte 0x00 // bcdUSB - .byte 0x02 // bcdUSB - .byte 0x00 // bDeviceClass - .byte 0x00 // bDeviceSubClass - .byte 0x00 // bDeviceProtocol - .byte 0x40 // bMaxPacketSize0 - .byte 0x1a // idVendor - .byte 0x60 // idVendor - .byte 0x40 // idProduct - .byte 0x47 // idProduct - .byte 0x00 // bcdDevice - .byte 0x01 // bcdDevice - .byte 0x01 // iManufacturer - .byte 0x02 // iProduct - .byte 0x00 // iSerialNumber - .byte 0x01 // bNumConfigurations - - .align 2 -dev_qualifier: - .byte 0x0a // bLength - .byte 0x06 // bDescriptorType - .byte 0x00 // bcdUSB - .byte 0x02 // bcdUSB - .byte 0x00 // bDeviceClass - .byte 0x00 // bDeviceSubClass - .byte 0x00 // bDeviceProtocol - .byte 0x40 // bMaxPacketSize0 - .byte 0x01 // bNumConfigurations - .byte 0x00 // bRESERVED - - .align 2 -config_desc_hs: - .byte 0x09 // bLength - .byte 0x02 // bDescriptorType - .byte 0x20 // wTotalLength - .byte 0x00 // wTotalLength - .byte 0x01 // bNumInterfaces - .byte 0x01 // bConfigurationValue - .byte 0x00 // iConfiguration - .byte 0xc0 // bmAttributes - .byte 0x01 // MaxPower -intf_desc_hs: - .byte 0x09 // bLength - .byte 0x04 // bDescriptorType - .byte 0x00 // bInterfaceNumber - .byte 0x00 // bAlternateSetting - .byte 0x02 // bNumEndpoints - .byte 0xff // bInterfaceClass - .byte 0x00 // bInterfaceSubClass - .byte 0x50 // bInterfaceProtocol - .byte 0x00 // iInterface -ep1_desc_hs: - .byte 0x07 // bLength - .byte 0x05 // bDescriptorType - .byte 0x01 // bEndpointAddress - .byte 0x02 // bmAttributes - .byte 0x00 // wMaxPacketSize - .byte 0x02 // wMaxPacketSize - .byte 0x00 // bInterval -ep2_desc_hs: - .byte 0x07 // bLength - .byte 0x05 // bDescriptorType - .byte 0x81 // bEndpointAddress - .byte 0x02 // bmAttributes - .byte 0x00 // wMaxPacketSize - .byte 0x02 // wMaxPacketSize - .byte 0x00 // bInterval - - .align 2 -config_desc_fs: - .byte 0x09 // bLength - .byte 0x02 // bDescriptorType - .byte 0x20 // wTotalLength - .byte 0x00 // wTotalLength - .byte 0x01 // bNumInterfaces - .byte 0x01 // bConfigurationValue - .byte 0x00 // iConfiguration - .byte 0xc0 // bmAttributes - .byte 0x01 // MaxPower -intf_desc_fs: - .byte 0x09 // bLength - .byte 0x04 // bDescriptorType - .byte 0x00 // bInterfaceNumber - .byte 0x00 // bAlternateSetting - .byte 0x02 // bNumEndpoints - .byte 0xff // bInterfaceClass - .byte 0x00 // bInterfaceSubClass - .byte 0x50 // bInterfaceProtocol - .byte 0x00 // iInterface -ep1_desc_fs: - .byte 0x07 // bLength - .byte 0x05 // bDescriptorType - .byte 0x01 // bEndpointAddress - .byte 0x02 // bmAttributes - .byte 0x40 // wMaxPacketSize - .byte 0x00 // wMaxPacketSize - .byte 0x00 // bInterval -ep2_desc_fs: - .byte 0x07 // bLength - .byte 0x05 // bDescriptorType - .byte 0x81 // bEndpointAddress - .byte 0x02 // bmAttributes - .byte 0x40 // wMaxPacketSize - .byte 0x00 // wMaxPacketSize - .byte 0x00 // bInterval - - .align 2 -string_lang_ids: - .byte 0x04 - .byte 0x03 - .byte 0x09 - .byte 0x04 - - .align 2 -string_manufacture: - .byte 0x10 - .byte 0x03 - .byte 0x49 - .byte 0x00 - .byte 0x6e - .byte 0x00 - .byte 0x67 - .byte 0x00 - .byte 0x65 - .byte 0x00 - .byte 0x6e - .byte 0x00 - .byte 0x69 - .byte 0x00 - .byte 0x63 - .byte 0x00 - - .align 2 -string_product: - .byte 0x2e - .byte 0x03 - .byte 0x4a - .byte 0x00 - .byte 0x5a - .byte 0x00 - .byte 0x34 - .byte 0x00 - .byte 0x37 - .byte 0x00 - .byte 0x34 - .byte 0x00 - .byte 0x30 - .byte 0x00 - .byte 0x20 - .byte 0x00 - .byte 0x55 - .byte 0x00 - .byte 0x53 - .byte 0x00 - .byte 0x42 - .byte 0x00 - .byte 0x20 - .byte 0x00 - .byte 0x42 - .byte 0x00 - .byte 0x6f - .byte 0x00 - .byte 0x6f - .byte 0x00 - .byte 0x74 - .byte 0x00 - .byte 0x20 - .byte 0x00 - .byte 0x44 - .byte 0x00 - .byte 0x65 - .byte 0x00 - .byte 0x76 - .byte 0x00 - .byte 0x69 - .byte 0x00 - .byte 0x63 - .byte 0x00 - .byte 0x65 - .byte 0x00 - - .align 2 -cpu_info_data: - .byte 0x4a - .byte 0x5a - .byte 0x34 - .byte 0x37 - .byte 0x34 - .byte 0x30 - .byte 0x56 - .byte 0x31 -usbboot_end: - - .set reorder |