diff options
Diffstat (limited to 'package/uboot-lantiq')
92 files changed, 0 insertions, 21912 deletions
diff --git a/package/uboot-lantiq/Makefile b/package/uboot-lantiq/Makefile deleted file mode 100644 index 8909ee981e..0000000000 --- a/package/uboot-lantiq/Makefile +++ /dev/null @@ -1,190 +0,0 @@ -# -# Copyright (C) 2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=u-boot - -PKG_VERSION:=2010.03 -PKG_MD5SUM:=2bf5ebf497dddc52440b1ea386cc1332 -PKG_RELEASE:=1 - -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot -PKG_TARGETS:=bin - -include $(INCLUDE_DIR)/package.mk - -ifeq ($(DUMP),) - STAMP_CONFIGURED:=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/.configured - STAMP_BUILT:=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/.built -endif - -define Package/uboot-lantiq-template - SECTION:=boot - CATEGORY:=Boot Loaders - DEPENDS:=@TARGET_lantiq_danube - URL:=http://www.denx.de/wiki/U-Boot - VARIANT:=$(1) - TITLE:=$(1) ($(2)) - MAINTAINER:=John Crispin <blogic@openwrt.org> -endef - -#Lantiq -Package/uboot-lantiq-easy50712_DDR166M_flash=$(call Package/uboot-lantiq-template,easy50712_DDR166M_flash,NOR) -Package/uboot-lantiq-easy50712_DDR166M_ramboot=$(call Package/uboot-lantiq-template,easy50712_DDR166M_ramboot,RAM) -Package/uboot-lantiq-easy50812_DDR166M_flash=$(call Package/uboot-lantiq-template,easy50812_DDR166M_flash,NOR) -Package/uboot-lantiq-easy50812_DDR166M_ramboot=$(call Package/uboot-lantiq-template,easy50812_DDR166M_ramboot,RAM) - -DDR_CONFIG_easy50712_DDR166M_ramboot:=easy50712_DDR166M -DDR_CONFIG_easy50812_DDR166M_ramboot:=easy50812 - -#Siemens -Package/uboot-lantiq-gigaSX76X_DDRsamsung166_flash=$(call Package/uboot-lantiq-template,gigaSX76X_DDRsamsung166_flash,NOR) -Package/uboot-lantiq-gigaSX76X_DDRsamsung166_ramboot=$(call Package/uboot-lantiq-template,gigaSX76X_DDRsamsung166_ramboot,RAM) - -DDR_CONFIG_gigaSX76X_DDRsamsung166_ramboot:=easy50712_DDR166M - -#Arcadyan -Package/uboot-lantiq-arv3527P_flash=$(call Package/uboot-lantiq-template,arv3527P_flash,NOR) -Package/uboot-lantiq-arv3527P_ramboot=$(call Package/uboot-lantiq-template,arv3527P_ramboot,RAM) -Package/uboot-lantiq-arv3527P_brnboot=$(call Package/uboot-lantiq-template,arv3527P_brnboot,BRN) -Package/uboot-lantiq-arv4518PW_flash=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR) -Package/uboot-lantiq-arv4518PW_ramboot=$(call Package/uboot-lantiq-template,arv4518PW_ramboot,RAM) -Package/uboot-lantiq-arv4518PW_brnboot=$(call Package/uboot-lantiq-template,arv4518PW_brnboot,BRN) -Package/uboot-lantiq-arv4519PW_flash=$(call Package/uboot-lantiq-template,arv4519PW_flash,NOR) -Package/uboot-lantiq-arv4519PW_ramboot=$(call Package/uboot-lantiq-template,arv4519PW_ramboot,RAM) -Package/uboot-lantiq-arv4519PW_brnboot=$(call Package/uboot-lantiq-template,arv4519PW_brnboot,BRN) -Package/uboot-lantiq-arv4520PW_flash=$(call Package/uboot-lantiq-template,arv4520PW_flash,NOR) -Package/uboot-lantiq-arv4520PW_ramboot=$(call Package/uboot-lantiq-template,arv4520PW_ramboot,RAM) -Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4520PW_brnboot,BRN) -Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR) -Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM) -Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN) -Package/uboot-lantiq-arv7525PW_flash=$(call Package/uboot-lantiq-template,arv7525PW_flash,NOR) -Package/uboot-lantiq-arv7525PW_ramboot=$(call Package/uboot-lantiq-template,arv7525PW_ramboot,RAM) -Package/uboot-lantiq-arv7525PW_brnboot=$(call Package/uboot-lantiq-template,arv7525PW_brnboot,BRN) -Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR) -Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM) -Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN) -Package/uboot-lantiq-arv752DPW_flash=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR) -Package/uboot-lantiq-arv752DPW_ramboot=$(call Package/uboot-lantiq-template,arv752DPW_ramboot,RAM) -Package/uboot-lantiq-arv752DPW_brnboot=$(call Package/uboot-lantiq-template,arv752DPW_brnboot,BRN) -Package/uboot-lantiq-arv752DPW22_flash=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR) -Package/uboot-lantiq-arv752DPW22_ramboot=$(call Package/uboot-lantiq-template,arv752DPW22_ramboot,RAM) -Package/uboot-lantiq-arv752DPW22_brnboot=$(call Package/uboot-lantiq-template,arv752DPW22_brnboot,BRN) -Package/uboot-lantiq-arv7518PW_flash=$(call Package/uboot-lantiq-template,arv7518PW_flash,NOR) -Package/uboot-lantiq-arv7518PW_ramboot=$(call Package/uboot-lantiq-template,arv7518PW_ramboot,RAM) -Package/uboot-lantiq-arv7518PW_brnboot=$(call Package/uboot-lantiq-template,arv7518PW_brnboot,BRN) - -DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32 -DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64 -DDR_CONFIG_arv4519PW_ramboot:=arcadyan_psc166_32 -DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32 -DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32 -DDR_CONFIG_arv7525PW_ramboot:=arcadyan_psc166_32 -DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32 -DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64 -DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64 -DDR_CONFIG_arv7518PW_ramboot:=arcadyan_psc166_64 - -define Build/Prepare - $(PKG_UNPACK) - cp -r $(CP_OPTS) $(FILES_DIR)/* $(PKG_BUILD_DIR)/ - $(Build/Patch) - find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf -endef - -UBOOT_MAKE_OPTS:= \ - CROSS_COMPILE=$(TARGET_CROSS) \ - ENDIANNESS= \ - V=1 - -define Build/Configure/Target - $(MAKE) -s -C $(PKG_BUILD_DIR) \ - $(UBOOT_MAKE_OPTS) \ - O=$(PKG_BUILD_DIR)/$(BUILD_VARIANT) \ - $(1)_config -endef - -define Build/Configure - $(call Build/Configure/Target,$(BUILD_VARIANT)) -endef - -define Build/Compile/Target - $(MAKE) -s -C $(PKG_BUILD_DIR) \ - $(UBOOT_MAKE_OPTS) \ - O=$(PKG_BUILD_DIR)/$(1) \ - all -endef - -define Build/Compile - $(call Build/Compile/Target,$(BUILD_VARIANT)) -endef - -define Package/uboot-lantiq-$(BUILD_VARIANT)/install - mkdir -p $(1) -ifneq ($(findstring flash,$(BUILD_VARIANT)),) - dd \ - if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \ - of=$(1)/u-boot-bootstrap.bin \ - bs=64k conv=sync -else - dd \ - if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \ - of=$(1)/u-boot.bin \ - bs=64k conv=sync -endif -ifneq ($(findstring ramboot,$(BUILD_VARIANT)),) - if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \ - perl ./gct \ - $(DDR_CONFIG_$(BUILD_VARIANT)).conf \ - $(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.srec \ - $(1)/u-boot.asc; \ - fi -endif -endef - -$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_flash)) -$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_flash)) -$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-gigaSX76X_DDRsamsung166_flash)) -$(eval $(call BuildPackage,uboot-lantiq-gigaSX76X_DDRsamsung166_ramboot)) -#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_flash)) -#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_brnboot)) -#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4519PW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_ramboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_flash)) -$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_brnboot)) -$(eval $(call BuildPackage,uboot-lantiq-arv7518PW_ramboot)) - diff --git a/package/uboot-lantiq/arcadyan_psc166_32.conf b/package/uboot-lantiq/arcadyan_psc166_32.conf deleted file mode 100644 index 6f9ba0cbed..0000000000 --- a/package/uboot-lantiq/arcadyan_psc166_32.conf +++ /dev/null @@ -1,71 +0,0 @@ - 0xbf800060 0x7 - 0xbf800010 0x0 - 0xbf800020 0x0 - 0xbf800200 0x02 - 0xbf800210 0x0 - - 0xbf801000 0x1b1b - 0xbf801010 0x0 - 0xbf801020 0x0 - 0xbf801030 0x0 - 0xbf801040 0x0 - 0xbf801050 0x200 - 0xbf801060 0x605 - 0xbf801070 0x0303 - 0xbf801080 0x102 - 0xbf801090 0x70a - 0xbf8010a0 0x203 - 0xbf8010b0 0xc02 - 0xbf8010c0 0x1c8 - 0xbf8010d0 0x1 - 0xbf8010e0 0x0 - 0xbf8010f0 0x120 - 0xbf801100 0xc800 - 0xbf801110 0xd - 0xbf801120 0x301 - 0xbf801130 0x200 - 0xbf801140 0xa04 - 0xbf801150 0x1700 - 0xbf801160 0x1717 - 0xbf801170 0x0 - 0xbf801180 0x52 - 0xbf801190 0x0 - 0xbf8011a0 0x0 - 0xbf8011b0 0x0 - 0xbf8011c0 0x510 - 0xbf8011d0 0x4e20 - 0xbf8011e0 0x8235 - 0xbf8011f0 0x0 - 0xbf801200 0x0 - 0xbf801210 0x0 - 0xbf801220 0x0 - 0xbf801230 0x0 - 0xbf801240 0x0 - 0xbf801250 0x0 - 0xbf801260 0x0 - 0xbf801270 0x0 - 0xbf801280 0x0 - 0xbf801290 0x0 - 0xbf8012a0 0x0 - 0xbf8012b0 0x0 - 0xbf8012c0 0x0 - 0xbf8012d0 0x500 - 0xbf8012e0 0x0 - - 0xbf800060 0x05 - 0xbf801030 0x100 - - - - - - - - - - - - - - - diff --git a/package/uboot-lantiq/arcadyan_psc166_64.conf b/package/uboot-lantiq/arcadyan_psc166_64.conf deleted file mode 100644 index 8cae0c77e2..0000000000 --- a/package/uboot-lantiq/arcadyan_psc166_64.conf +++ /dev/null @@ -1,141 +0,0 @@ - 0xbf800060 0x7 - 0xbf800010 0x0 - 0xbf800020 0x0 - 0xbf800200 0x02 - 0xbf800210 0x0 - -;REG32(MC_DC0) = 0x00001B1B; - 0xbf801000 0x1b1b -;REG32(MC_DC1) = 0x00000000; - 0xbf801010 0x0 -;REG32(MC_DC2) = 0x00000000; - 0xbf801020 0x0 -;REG32(MC_DC3) = 0x00000000; - 0xbf801030 0x0 -;REG32(MC_DC4) = 0x00000000; - 0xbf801040 0x0 -;REG32(MC_DC5) = 0x00000200; - 0xbf801050 0x200 -;REG32(MC_DC6) = 0x00000306; -; 0xbf801060 0x0306 - 0xbf801060 0x0605 -;REG32(MC_DC7) = 0x00000303; -; 0xbf801070 0x302 -; 0xbf801070 0x0203 - 0xbf801070 0x0303 -;REG32(MC_DC8) = 0x00000102; - 0xbf801080 0x102 -;REG32(MC_DC9) = 0x0000070A; - 0xbf801090 0x70a -; 0xbf801090 0x608 -;REG32(MC_DC10) = 0x00000203; - 0xbf8010a0 0x203 -;REG32(MC_DC11) = 0x00000C02; - 0xbf8010b0 0xc02 -; 0xbf8010b0 0x0a02 -;REG32(MC_DC12) = 0x000001C8; - 0xbf8010c0 0x1c8 -;REG32(MC_DC13) = 0x00000001; - 0xbf8010d0 0x1 -;REG32(MC_DC14) = 0x00000000; - 0xbf8010e0 0x0 -;REG32(MC_DC15) = 0x00000F5F; -; 0xbf8010f0 0xf5f -; 0xbf8010f0 0xf3c - 0xbf8010f0 0x130 -;REG32(MC_DC16) = 0x0000C800; - 0xbf801100 0xc800 -;REG32(MC_DC17) = 0x0000000D; -; 0xbf801110 0xd - 0xbf801110 0xd -;REG32(MC_DC18) = 0x00000300; -; 0xbf801120 0x300 - 0xbf801120 0x301 -;REG32(MC_DC19) = 0x00000300; -; 0xbf801130 0x300 - 0xbf801130 0x200 -;REG32(MC_DC20) = 0x00000A04; -; 0xbf801140 0xa04 - 0xbf801140 0xa03 -;REG32(MC_DC21) = 0x00001c00; -; 0xbf801150 0xd00 -; 0xbf801150 0x1f00 - 0xbf801150 0x1b00 -;REG32(MC_DC22) = 0x00001E1E; -; 0xbf801160 0xd0d -; 0xbf801160 0x1f1f - 0xbf801160 0x1b1b -;REG32(MC_DC23) = 0x00000000; - 0xbf801170 0x0 -;//Disable ECC -;REG32(MC_DC24) = 0x0000007F; -; 0xbf801180 0x7f -; 0xbf801180 0x062 -; 0xbf801180 0x37f - 0xbf801180 0x59 -;REG32(MC_DC25) = 0x00000000; - 0xbf801190 0x0 -;REG32(MC_DC26) = 0x00000000; - 0xbf8011a0 0x0 -;REG32(MC_DC27) = 0x00000000; - 0xbf8011b0 0x0 -;REG32(MC_DC28) = 0x00000A24; -; 0xbf8011c0 0xa24 - 0xbf8011c0 0x510 -;REG32(MC_DC29) = 0x00002D89; -; 0xbf8011d0 0x2d89 -; 0xbf8011d0 0x2d92 - 0xbf8011d0 0x4e20 -;REG32(MC_DC30) = 0x00000022; -; 0xbf8011e0 0x8300 - 0xbf8011e0 0x8235 -;REG32(MC_DC31) = 0x00000000; - 0xbf8011f0 0x0 -;REG32(MC_DC32) = 0x00000000; - 0xbf801200 0x0 -;REG32(MC_DC33) = 0x00000000; - 0xbf801210 0x0 -;REG32(MC_DC34) = 0x00000000; - 0xbf801220 0x0 -;REG32(MC_DC35) = 0x00000000; - 0xbf801230 0x0 -;REG32(MC_DC36) = 0x00000000; - 0xbf801240 0x0 -;REG32(MC_DC37) = 0x00000000; - 0xbf801250 0x0 -;REG32(MC_DC38) = 0x00000000; - 0xbf801260 0x0 -;REG32(MC_DC39) = 0x00000000; - 0xbf801270 0x0 -;REG32(MC_DC40) = 0x00000000; - 0xbf801280 0x0 -;REG32(MC_DC41) = 0x00000000; - 0xbf801290 0x0 -;REG32(MC_DC42) = 0x00000000; - 0xbf8012a0 0x0 -;REG32(MC_DC43) = 0x00000000; - 0xbf8012b0 0x0 -;REG32(MC_DC44) = 0x00000000; - 0xbf8012c0 0x0 -;REG32(MC_DC45) = 0x00000600; - 0xbf8012d0 0x500 -;REG32(MC_DC46) = 0x00000000; - 0xbf8012e0 0x0 - - 0xbf800060 0x05 - 0xbf801030 0x100 - - - - - - - - - - - - - - - diff --git a/package/uboot-lantiq/easy50712_DDR166M.conf b/package/uboot-lantiq/easy50712_DDR166M.conf deleted file mode 100644 index 351d6a108f..0000000000 --- a/package/uboot-lantiq/easy50712_DDR166M.conf +++ /dev/null @@ -1,134 +0,0 @@ - 0xbf800060 0x7 - 0xbf800010 0x0 - 0xbf800020 0x0 - 0xbf800200 0x02 - 0xbf800210 0x0 - -;REG32(MC_DC0) = 0x00001B1B; - 0xbf801000 0x1b1b -;REG32(MC_DC1) = 0x00000000; - 0xbf801010 0x0 -;REG32(MC_DC2) = 0x00000000; - 0xbf801020 0x0 -;REG32(MC_DC3) = 0x00000000; - 0xbf801030 0x0 -;REG32(MC_DC4) = 0x00000000; - 0xbf801040 0x0 -;REG32(MC_DC5) = 0x00000200; - 0xbf801050 0x200 -;REG32(MC_DC6) = 0x00000306; -; 0xbf801060 0x0306 - 0xbf801060 0x0605 -;REG32(MC_DC7) = 0x00000303; - 0xbf801070 0x302 -; 0xbf801070 0x0203 -;REG32(MC_DC8) = 0x00000102; - 0xbf801080 0x102 -;REG32(MC_DC9) = 0x0000070A; - 0xbf801090 0x70a -; 0xbf801090 0x608 -;REG32(MC_DC10) = 0x00000203; - 0xbf8010a0 0x203 -;REG32(MC_DC11) = 0x00000C02; - 0xbf8010b0 0xc02 -; 0xbf8010b0 0x0a02 -;REG32(MC_DC12) = 0x000001C8; - 0xbf8010c0 0x1c8 -;REG32(MC_DC13) = 0x00000001; - 0xbf8010d0 0x1 -;REG32(MC_DC14) = 0x00000000; - 0xbf8010e0 0x0 -;REG32(MC_DC15) = 0x00000F5F; -; 0xbf8010f0 0xf5f - 0xbf8010f0 0xf3c -;REG32(MC_DC16) = 0x0000C800; - 0xbf801100 0xc800 -;REG32(MC_DC17) = 0x0000000D; -; 0xbf801110 0xd - 0xbf801110 0xd -;REG32(MC_DC18) = 0x00000300; - 0xbf801120 0x300 -;REG32(MC_DC19) = 0x00000300; -; 0xbf801130 0x300 - 0xbf801130 0x200 -;REG32(MC_DC20) = 0x00000A04; -; 0xbf801140 0xa04 - 0xbf801140 0xa04 -;REG32(MC_DC21) = 0x00001c00; - 0xbf801150 0xd00 -; 0xbf801150 0x1f00 -;REG32(MC_DC22) = 0x00001E1E; - 0xbf801160 0xd0d -; 0xbf801160 0x1f1f -;REG32(MC_DC23) = 0x00000000; - 0xbf801170 0x0 -;//Disable ECC -;REG32(MC_DC24) = 0x0000007F; -; 0xbf801180 0x7f - 0xbf801180 0x062 -; 0xbf801180 0x37f -;REG32(MC_DC25) = 0x00000000; - 0xbf801190 0x0 -;REG32(MC_DC26) = 0x00000000; - 0xbf8011a0 0x0 -;REG32(MC_DC27) = 0x00000000; - 0xbf8011b0 0x0 -;REG32(MC_DC28) = 0x00000A24; -; 0xbf8011c0 0xa24 - 0xbf8011c0 0x510 -;REG32(MC_DC29) = 0x00002D89; - 0xbf8011d0 0x2d89 -; 0xbf8011d0 0x2d92 -;REG32(MC_DC30) = 0x00000022; - 0xbf8011e0 0x8300 -; 0xbf8011e0 0x8235 -;REG32(MC_DC31) = 0x00000000; - 0xbf8011f0 0x0 -;REG32(MC_DC32) = 0x00000000; - 0xbf801200 0x0 -;REG32(MC_DC33) = 0x00000000; - 0xbf801210 0x0 -;REG32(MC_DC34) = 0x00000000; - 0xbf801220 0x0 -;REG32(MC_DC35) = 0x00000000; - 0xbf801230 0x0 -;REG32(MC_DC36) = 0x00000000; - 0xbf801240 0x0 -;REG32(MC_DC37) = 0x00000000; - 0xbf801250 0x0 -;REG32(MC_DC38) = 0x00000000; - 0xbf801260 0x0 -;REG32(MC_DC39) = 0x00000000; - 0xbf801270 0x0 -;REG32(MC_DC40) = 0x00000000; - 0xbf801280 0x0 -;REG32(MC_DC41) = 0x00000000; - 0xbf801290 0x0 -;REG32(MC_DC42) = 0x00000000; - 0xbf8012a0 0x0 -;REG32(MC_DC43) = 0x00000000; - 0xbf8012b0 0x0 -;REG32(MC_DC44) = 0x00000000; - 0xbf8012c0 0x0 -;REG32(MC_DC45) = 0x00000600; - 0xbf8012d0 0x500 -;REG32(MC_DC46) = 0x00000000; - 0xbf8012e0 0x0 - - 0xbf800060 0x05 - 0xbf801030 0x100 - - - - - - - - - - - - - - - diff --git a/package/uboot-lantiq/easy50812.conf b/package/uboot-lantiq/easy50812.conf deleted file mode 100644 index d28198c2f6..0000000000 --- a/package/uboot-lantiq/easy50812.conf +++ /dev/null @@ -1,55 +0,0 @@ -0xbf800060 0x0000000f -0xbf800010 0x00000000 -0xbf800020 0x00000000 -0xbf800200 0x00000002 -0xbf800210 0x00000000 -0xbf801000 0x00001b1b -0xbf801010 0x00000000 -0xbf801020 0x00000000 -0xbf801030 0x00000000 -0xbf801040 0x00000000 -0xbf801050 0x00000200 -0xbf801060 0x00000306 -0xbf801070 0x00000303 -0xbf801080 0x00000102 -0xbf801090 0x0000070a -0xbf8010a0 0x00000203 -0xbf8010b0 0x00000c02 -0xbf8010c0 0x000001c8 -0xbf8010d0 0x00000001 -0xbf8010e0 0x00000000 -0xbf8010f0 0x00000139 -0xbf801100 0x00002200 -0xbf801110 0x0000000d -0xbf801120 0x00000301 -0xbf801130 0x00000200 -0xbf801140 0x00000a04 -0xbf801150 0x00001800 -0xbf801160 0x00001818 -0xbf801170 0x00000000 -0xbf801180 0x00000059 -0xbf801190 0x00000000 -0xbf8011a0 0x00000000 -0xbf8011b0 0x00000000 -0xbf8011c0 0x00000514 -0xbf8011d0 0x00002d93 -0xbf8011e0 0x00008235 -0xbf8011f0 0x00000000 -0xbf801200 0x00000000 -0xbf801210 0x00000000 -0xbf801220 0x00000000 -0xbf801230 0x00000000 -0xbf801240 0x00000000 -0xbf801250 0x00000000 -0xbf801260 0x00000000 -0xbf801270 0x00000000 -0xbf801280 0x00000000 -0xbf801290 0x00000000 -0xbf8012a0 0x00000000 -0xbf8012b0 0x00000000 -0xbf8012c0 0x00000000 -0xbf8012d0 0x00000600 -0xbf8012e0 0x00000000 -0xbf800060 0x0000000d -0xbf801030 0x00000100 - diff --git a/package/uboot-lantiq/files/board/arcadyan/Makefile b/package/uboot-lantiq/files/board/arcadyan/Makefile deleted file mode 100644 index 0038ac4d2a..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a -BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a - -BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - -COBJS-y += board.o athrs26_phy.o - -SOBJS = lowlevel_init.o pmuenable.o - -BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o -BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o - -BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c) - -SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S)) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y)) -BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y)) - - -all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS) - $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c b/package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c deleted file mode 100644 index 11bf6d0b71..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2010 Industrie Dial Face S.p.A. - * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com - * - * (C) Copyright 2007 - * Vlad Lungu vlad.lungu@windriver.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/mipsregs.h> -#include <asm/io.h> - -phys_size_t bootstrap_initdram(int board_type) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - return CONFIG_SYS_MAX_RAM; -} - -int bootstrap_checkboard(void) -{ - return 0; -} - -int bootstrap_misc_init_r(void) -{ - set_io_port_base(0); - return 0; -} diff --git a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c b/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c deleted file mode 100644 index 663c4aa201..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c +++ /dev/null @@ -1,812 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright © 2003 Atheros Communications, Inc., All Rights Reserved. - */ - -/* - * Manage the atheros ethernet PHY. - * - * All definitions in this file are operating system independent! - */ - -#include <config.h> -#include <linux/types.h> -#include <common.h> -#include <miiphy.h> -//#include "phy.h" -//#include "ar7100_soc.h" -#include "athrs26_phy.h" - -#define phy_reg_read(base, addr, reg, datap) \ - miiphy_read("lq_cpe_eth", addr, reg, datap); -#define phy_reg_write(base, addr, reg, data) \ - miiphy_write("lq_cpe_eth", addr, reg, data); - - -/* PHY selections and access functions */ - -typedef enum { - PHY_SRCPORT_INFO, - PHY_PORTINFO_SIZE, -} PHY_CAP_TYPE; - -typedef enum { - PHY_SRCPORT_NONE, - PHY_SRCPORT_VLANTAG, - PHY_SRCPORT_TRAILER, -} PHY_SRCPORT_TYPE; - -#ifdef DEBUG -#define DRV_DEBUG 1 -#endif -//#define DRV_DEBUG 1 - -#define DRV_DEBUG_PHYERROR 0x00000001 -#define DRV_DEBUG_PHYCHANGE 0x00000002 -#define DRV_DEBUG_PHYSETUP 0x00000004 - -#if DRV_DEBUG -int athrPhyDebug = DRV_DEBUG_PHYERROR|DRV_DEBUG_PHYCHANGE|DRV_DEBUG_PHYSETUP; - -#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6) \ -{ \ - if (athrPhyDebug & (FLG)) { \ - logMsg(X0, X1, X2, X3, X4, X5, X6); \ - } \ -} - -#define DRV_MSG(x,a,b,c,d,e,f) \ - logMsg(x,a,b,c,d,e,f) - -#define DRV_PRINT(FLG, X) \ -{ \ - if (athrPhyDebug & (FLG)) { \ - printf X; \ - } \ -} - -#else /* !DRV_DEBUG */ -#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6) -#define DRV_MSG(x,a,b,c,d,e,f) -#define DRV_PRINT(DBG_SW,X) -#endif - -#define ATHR_LAN_PORT_VLAN 1 -#define ATHR_WAN_PORT_VLAN 2 - -#define ENET_UNIT_LAN 0 - -#define TRUE 1 -#define FALSE 0 - -#define ATHR_PHY0_ADDR 0x0 -#define ATHR_PHY1_ADDR 0x1 -#define ATHR_PHY2_ADDR 0x2 -#define ATHR_PHY3_ADDR 0x3 -#define ATHR_PHY4_ADDR 0x4 - -/* - * Track per-PHY port information. - */ -typedef struct { - BOOL isEnetPort; /* normal enet port */ - BOOL isPhyAlive; /* last known state of link */ - int ethUnit; /* MAC associated with this phy port */ - uint32_t phyBase; - uint32_t phyAddr; /* PHY registers associated with this phy port */ - uint32_t VLANTableSetting; /* Value to be written to VLAN table */ -} athrPhyInfo_t; - -/* - * Per-PHY information, indexed by PHY unit number. - */ -static athrPhyInfo_t athrPhyInfo[] = { - {TRUE, /* phy port 0 -- LAN port 0 */ - FALSE, - ENET_UNIT_LAN, - 0, - ATHR_PHY0_ADDR, - ATHR_LAN_PORT_VLAN - }, - - {TRUE, /* phy port 1 -- LAN port 1 */ - FALSE, - ENET_UNIT_LAN, - 0, - ATHR_PHY1_ADDR, - ATHR_LAN_PORT_VLAN - }, - - {TRUE, /* phy port 2 -- LAN port 2 */ - FALSE, - ENET_UNIT_LAN, - 0, - ATHR_PHY2_ADDR, - ATHR_LAN_PORT_VLAN - }, - - {TRUE, /* phy port 3 -- LAN port 3 */ - FALSE, - ENET_UNIT_LAN, - 0, - ATHR_PHY3_ADDR, - ATHR_LAN_PORT_VLAN - }, - - {TRUE, /* phy port 4 -- WAN port or LAN port 4 */ - FALSE, - 1, - 0, - ATHR_PHY4_ADDR, - ATHR_LAN_PORT_VLAN /* Send to all ports */ - }, - - {FALSE, /* phy port 5 -- CPU port (no RJ45 connector) */ - TRUE, - ENET_UNIT_LAN, - 0, - 0x00, - ATHR_LAN_PORT_VLAN /* Send to all ports */ - }, -}; - -#ifdef CFG_ATHRHDR_EN -typedef struct { - uint8_t data[ATHRHDR_MAX_DATA]; - uint8_t len; - uint32_t seq; -} cmd_resp_t; - -typedef struct { - uint16_t reg_addr; - uint16_t cmd_len; - uint8_t *reg_data; -}cmd_write_t; - -static cmd_write_t cmd_write,cmd_read; -static cmd_resp_t cmd_resp; -static struct eth_device *lan_mac; -//static atomic_t seqcnt = ATOMIC_INIT(0); -static int seqcnt = 0; -static int cmd = 1; -//volatile uchar AthrHdrPkt[60]; -#endif - -#define ATHR_GLOBALREGBASE 0 - -//#define ATHR_PHY_MAX (sizeof(athrPhyInfo) / sizeof(athrPhyInfo[0])) -#define ATHR_PHY_MAX 5 - -/* Range of valid PHY IDs is [MIN..MAX] */ -#define ATHR_ID_MIN 0 -#define ATHR_ID_MAX (ATHR_PHY_MAX-1) - -/* Convenience macros to access myPhyInfo */ -#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort) -#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive) -#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit) -#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase) -#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr) -#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting) - - -#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \ - (ATHR_IS_ENET_PORT(phyUnit) && \ - ATHR_ETHUNIT(phyUnit) == (ethUnit)) - -#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN)) - -/* Forward references */ -BOOL athrs26_phy_is_link_alive(int phyUnit); -//static uint32_t athrs26_reg_read(uint16_t reg_addr); -static void athrs26_reg_write(uint16_t reg_addr, - uint32_t reg_val); - -/****************************************************************************** -* -* athrs26_phy_is_link_alive - test to see if the specified link is alive -* -* RETURNS: -* TRUE --> link is alive -* FALSE --> link is down -*/ - -void athrs26_reg_init(void) -{ - - athrs26_reg_write(0x200, 0x200); - athrs26_reg_write(0x300, 0x200); - athrs26_reg_write(0x400, 0x200); - athrs26_reg_write(0x500, 0x200); - athrs26_reg_write(0x600, 0x7d); - -#ifdef S26_VER_1_0 - phy_reg_write(0, 0, 29, 41); - phy_reg_write(0, 0, 30, 0); - phy_reg_write(0, 1, 29, 41); - phy_reg_write(0, 1, 30, 0); - phy_reg_write(0, 2, 29, 41); - phy_reg_write(0, 2, 30, 0); - phy_reg_write(0, 3, 29, 41); - phy_reg_write(0, 3, 30, 0); - phy_reg_write(0, 4, 29, 41); - phy_reg_write(0, 4, 30, 0); -#endif - - athrs26_reg_write(0x38, 0xc000050e); - -#ifdef CFG_ATHRHDR_EN - athrs26_reg_write(0x104, 0x4804); -#else - athrs26_reg_write(0x104, 0x4004); -#endif - - athrs26_reg_write(0x60, 0xffffffff); - athrs26_reg_write(0x64, 0xaaaaaaaa); - athrs26_reg_write(0x68, 0x55555555); - athrs26_reg_write(0x6c, 0x0); - - athrs26_reg_write(0x70, 0x41af); -} - -BOOL -athrs26_phy_is_link_alive(int phyUnit) -{ - uint16_t phyHwStatus; - uint32_t phyBase; - uint32_t phyAddr; - - phyBase = ATHR_PHYBASE(phyUnit); - phyAddr = ATHR_PHYADDR(phyUnit); - - phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus); - - if (phyHwStatus & ATHR_STATUS_LINK_PASS) - return TRUE; - - return FALSE; -} - - -/****************************************************************************** -* -* athrs26_phy_setup - reset and setup the PHY associated with -* the specified MAC unit number. -* -* Resets the associated PHY port. -* -* RETURNS: -* TRUE --> associated PHY is alive -* FALSE --> no LINKs on this ethernet unit -*/ - -BOOL -athrs26_phy_setup(int ethUnit) -{ - int phyUnit; - uint16_t phyHwStatus; - uint16_t timeout; - int liveLinks = 0; - uint32_t phyBase = 0; - BOOL foundPhy = FALSE; - uint32_t phyAddr = 0; - uint32_t regVal; - - - /* See if there's any configuration data for this enet */ - /* start auto negogiation on each phy */ - for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { - if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { - continue; - } - - - foundPhy = TRUE; - phyBase = ATHR_PHYBASE(phyUnit); - phyAddr = ATHR_PHYADDR(phyUnit); - - phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT, - ATHR_ADVERTISE_ALL); - - /* Reset PHYs*/ - phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL, - ATHR_CTRL_AUTONEGOTIATION_ENABLE - | ATHR_CTRL_SOFTWARE_RESET); - - } - - if (!foundPhy) { - return FALSE; /* No PHY's configured for this ethUnit */ - } - - /* - * After the phy is reset, it takes a little while before - * it can respond properly. - */ - sysMsDelay(1000); - - /* - * Wait up to .75 seconds for ALL associated PHYs to finish - * autonegotiation. The only way we get out of here sooner is - * if ALL PHYs are connected AND finish autonegotiation. - */ - for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) { - if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { - continue; - } - - timeout=20; - for (;;) { - phyHwStatus = 0; - phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL, &phyHwStatus); - - if (ATHR_RESET_DONE(phyHwStatus)) { - DRV_PRINT(DRV_DEBUG_PHYSETUP, - ("Port %d, Neg Success\n", phyUnit)); - break; - } - if (timeout == 0) { - DRV_PRINT(DRV_DEBUG_PHYSETUP, - ("Port %d, Negogiation timeout\n", phyUnit)); - break; - } - if (--timeout == 0) { - DRV_PRINT(DRV_DEBUG_PHYSETUP, - ("Port %d, Negogiation timeout\n", phyUnit)); - break; - } - - sysMsDelay(150); - } - } - - /* - * All PHYs have had adequate time to autonegotiate. - * Now initialize software status. - * - * It's possible that some ports may take a bit longer - * to autonegotiate; but we can't wait forever. They'll - * get noticed by mv_phyCheckStatusChange during regular - * polling activities. - */ - for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { - if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { - continue; - } - - if (athrs26_phy_is_link_alive(phyUnit)) { - liveLinks++; - ATHR_IS_PHY_ALIVE(phyUnit) = TRUE; - } else { - ATHR_IS_PHY_ALIVE(phyUnit) = FALSE; - } - - phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit), - ATHR_PHY_SPEC_STATUS, ®Val); - DRV_PRINT(DRV_DEBUG_PHYSETUP, - ("eth%d: Phy Specific Status=%4.4x\n", ethUnit, regVal)); - } -#if 0 - /* if using header for register configuration, we have to */ - /* configure s26 register after frame transmission is enabled */ - - athrs26_reg_write(0x200, 0x200); - athrs26_reg_write(0x300, 0x200); - athrs26_reg_write(0x400, 0x200); - athrs26_reg_write(0x500, 0x200); - athrs26_reg_write(0x600, 0x200); - athrs26_reg_write(0x38, 0x50e); -#endif -#ifndef CFG_ATHRHDR_EN -/* if using header for register configuration, we have to */ - /* configure s26 register after frame transmission is enabled */ - athrs26_reg_init(); -#endif - - return (liveLinks > 0); -} - -/****************************************************************************** -* -* athrs26_phy_is_fdx - Determines whether the phy ports associated with the -* specified device are FULL or HALF duplex. -* -* RETURNS: -* 1 --> FULL -* 0 --> HALF -*/ -int -athrs26_phy_is_fdx(int ethUnit) -{ - int phyUnit; - uint32_t phyBase; - uint32_t phyAddr; - uint16_t phyHwStatus; - int ii = 200; - - if (ethUnit == ENET_UNIT_LAN) - return TRUE; - - for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { - if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { - continue; - } - - if (athrs26_phy_is_link_alive(phyUnit)) { - - phyBase = ATHR_PHYBASE(phyUnit); - phyAddr = ATHR_PHYADDR(phyUnit); - - do { - phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus); - sysMsDelay(10); - } while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii); - - if (phyHwStatus & ATHER_STATUS_FULL_DEPLEX) - return TRUE; - } - } - - return FALSE; -} - - -/****************************************************************************** -* -* athrs26_phy_speed - Determines the speed of phy ports associated with the -* specified device. -* -* RETURNS: -* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX; -* AG7100_PHY_SPEED_1000T; -*/ - -BOOL -athrs26_phy_speed(int ethUnit) -{ - int phyUnit; - uint16_t phyHwStatus; - uint32_t phyBase; - uint32_t phyAddr; - int ii = 200; - - if (ethUnit == ENET_UNIT_LAN) - return _100BASET; - - for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { - if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { - continue; - } - - if (athrs26_phy_is_link_alive(phyUnit)) { - - phyBase = ATHR_PHYBASE(phyUnit); - phyAddr = ATHR_PHYADDR(phyUnit); - - do { - phy_reg_read(phyBase, phyAddr, - ATHR_PHY_SPEC_STATUS, &phyHwStatus); - sysMsDelay(10); - }while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii); - - phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >> - ATHER_STATUS_LINK_SHIFT); - - switch(phyHwStatus) { - case 0: - return _10BASET; - case 1: - return _100BASET; - case 2: - return _1000BASET; - default: - DRV_PRINT(DRV_DEBUG_PHYERROR, ("Unkown speed read!\n")); - } - } - } - - return _10BASET; -} - -/***************************************************************************** -* -* athr_phy_is_up -- checks for significant changes in PHY state. -* -* A "significant change" is: -* dropped link (e.g. ethernet cable unplugged) OR -* autonegotiation completed + link (e.g. ethernet cable plugged in) -* -* When a PHY is plugged in, phyLinkGained is called. -* When a PHY is unplugged, phyLinkLost is called. -*/ - -int -athrs26_phy_is_up(int ethUnit) -{ - int phyUnit; - uint16_t phyHwStatus; - athrPhyInfo_t *lastStatus; - int linkCount = 0; - int lostLinks = 0; - int gainedLinks = 0; - uint32_t phyBase; - uint32_t phyAddr; -#ifdef CFG_ATHRHDR_REG - /* if using header to config s26, the link of MAC0 should always be up */ - if (ethUnit == ENET_UNIT_LAN) - return 1; -#endif - - for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { - if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { - continue; - } - - phyBase = ATHR_PHYBASE(phyUnit); - phyAddr = ATHR_PHYADDR(phyUnit); - - - lastStatus = &athrPhyInfo[phyUnit]; - phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus); - - if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */ - /* See if we've lost link */ - if (phyHwStatus & ATHR_STATUS_LINK_PASS) { - linkCount++; - } else { - lostLinks++; - DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n", - ethUnit, phyUnit)); - lastStatus->isPhyAlive = FALSE; - } - } else { /* last known link status was DEAD */ - /* Check for reset complete */ - phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS, &phyHwStatus); - if (!ATHR_RESET_DONE(phyHwStatus)) - continue; - - /* Check for AutoNegotiation complete */ - if (ATHR_AUTONEG_DONE(phyHwStatus)) { - //printk("autoneg done\n"); - gainedLinks++; - linkCount++; - DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n", - ethUnit, phyUnit)); - lastStatus->isPhyAlive = TRUE; - } - } - } - - return (linkCount); - -#if 0 - if (linkCount == 0) { - if (lostLinks) { - /* We just lost the last link for this MAC */ - phyLinkLost(ethUnit); - } - } else { - if (gainedLinks == linkCount) { - /* We just gained our first link(s) for this MAC */ - phyLinkGained(ethUnit); - } - } -#endif -} - -#ifdef CFG_ATHRHDR_EN -void athr_hdr_timeout(void){ - eth_halt(); - NetState = NETLOOP_FAIL; -} - -void athr_hdr_handler(uchar *recv_pkt, unsigned dest, unsigned src, unsigned len){ - header_receive_pkt(recv_pkt); - NetState = NETLOOP_SUCCESS; -} -static int -athrs26_header_config_reg (struct eth_device *dev, uint8_t wr_flag, - uint16_t reg_addr, uint16_t cmd_len, - uint8_t *val) -{ - at_header_t at_header; - reg_cmd_t reg_cmd; - uchar *AthrHdrPkt; - - AthrHdrPkt = NetTxPacket; - - if(AthrHdrPkt == NULL) { - printf("Null packet\n"); - return; - } - memset(AthrHdrPkt,0,60); - - /*fill at_header*/ - at_header.reserved0 = 0x10; //default - at_header.priority = 0; - at_header.type = 0x5; - at_header.broadcast = 0; - at_header.from_cpu = 1; - at_header.reserved1 = 0x01; //default - at_header.port_num = 0; - - AthrHdrPkt[0] = at_header.port_num; - AthrHdrPkt[0] |= at_header.reserved1 << 4; - AthrHdrPkt[0] |= at_header.from_cpu << 6; - AthrHdrPkt[0] |= at_header.broadcast << 7; - - AthrHdrPkt[1] = at_header.type; - AthrHdrPkt[1] |= at_header.priority << 4; - AthrHdrPkt[1] |= at_header.reserved0 << 6; - - - /*fill reg cmd*/ - if(cmd_len > 4) - cmd_len = 4;//only support 32bits register r/w - - reg_cmd.reg_addr = reg_addr&0x3FFFC; - reg_cmd.cmd_len = cmd_len; - reg_cmd.cmd = wr_flag; - reg_cmd.reserved2 = 0x5; //default - reg_cmd.seq_num = seqcnt; - - AthrHdrPkt[2] = reg_cmd.reg_addr & 0xff; - AthrHdrPkt[3] = (reg_cmd.reg_addr & 0xff00) >> 8; - AthrHdrPkt[4] = (reg_cmd.reg_addr & 0x30000) >> 16; - AthrHdrPkt[4] |= reg_cmd.cmd_len << 4; - AthrHdrPkt[5] = reg_cmd.cmd << 4; - AthrHdrPkt[5] |= reg_cmd.reserved2 << 5; - AthrHdrPkt[6] = (reg_cmd.seq_num & 0x7f) << 1; - AthrHdrPkt[7] = (reg_cmd.seq_num & 0x7f80) >> 7; - AthrHdrPkt[8] = (reg_cmd.seq_num & 0x7f8000) >> 15; - AthrHdrPkt[9] = (reg_cmd.seq_num & 0x7f800000) >> 23; - - /*fill reg data*/ - if(!wr_flag)//write - memcpy((AthrHdrPkt + 10), val, cmd_len); - - /*start xmit*/ - if(dev == NULL) { - printf("ERROR device not found\n"); - return -1; - } - header_xmit(dev, AthrHdrPkt ,60); - return 0; -} -void athr_hdr_func(void) { - - NetSetTimeout (1 * CFG_HZ,athr_hdr_timeout ); - NetSetHandler (athr_hdr_handler); - - if(cmd) - athrs26_header_config_reg(lan_mac, cmd, cmd_read.reg_addr, cmd_read.cmd_len, cmd_read.reg_data); - else - athrs26_header_config_reg(lan_mac, cmd, cmd_write.reg_addr, cmd_write.cmd_len, cmd_write.reg_data); -} -static int -athrs26_header_write_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data) -{ - int i = 2; - cmd_write.reg_addr = reg_addr; - cmd_write.cmd_len = cmd_len; - cmd_write.reg_data = reg_data; - cmd = 0; - seqcnt++; - - do { - if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */ - break; - } while (i--); - - return i; -} - -static int -athrs26_header_read_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data) -{ - int i = 2; - - cmd_read.reg_addr = reg_addr; - cmd_read.cmd_len = cmd_len; - cmd_read.reg_data = reg_data; - cmd = 1; - seqcnt++; - - do { - if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */ - break; - } while (i--); - - if ((i==0) || (seqcnt != cmd_resp.seq) || (cmd_len != cmd_resp.len)) { - return -1; - } - memcpy (cmd_read.reg_data, cmd_resp.data, cmd_len); - return 0; -} -int header_receive_pkt(uchar *recv_pkt) -{ - cmd_resp.len = recv_pkt[4] >> 4; - if (cmd_resp.len > 10) - goto out; - - cmd_resp.seq = recv_pkt[6] >> 1; - cmd_resp.seq |= recv_pkt[7] << 7; - cmd_resp.seq |= recv_pkt[8] << 15; - cmd_resp.seq |= recv_pkt[9] << 23; - - if (cmd_resp.seq < seqcnt) - goto out; - memcpy (cmd_resp.data, (recv_pkt + 10), cmd_resp.len); -out: - return 0; -} - -void athrs26_reg_dev(struct eth_device *mac) -{ - lan_mac = mac; -} - -#endif - -/*static uint32_t -athrs26_reg_read(uint16_t reg_addr) -{ -#ifndef CFG_ATHRHDR_REG - uint16_t reg_word_addr = reg_addr / 2, phy_val; - uint32_t phy_addr; - uint8_t phy_reg; - - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (reg_word_addr >> 8) & 0x1ff; - phy_reg_write (0, phy_addr, phy_reg, phy_val); - - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); - phy_reg = reg_word_addr & 0x1f; - phy_reg_read(0, phy_addr, phy_reg, &phy_val); - - return phy_val; -#else - uint8_t reg_data[4]; - - memset (reg_data, 0, 4); - athrs26_header_read_reg(reg_addr, 4, reg_data); - return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24)); -#endif -} -*/ -static void -athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val) -{ -#ifndef CFG_ATHRHDR_REG - uint16_t reg_word_addr = reg_addr / 2, phy_val; - uint32_t phy_addr; - uint8_t phy_reg; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/ - phy_reg_write (0, phy_addr, phy_reg, phy_val); - - /* read register with low address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address */ - phy_reg_write (0, phy_addr, phy_reg, reg_val); -#else - uint8_t reg_data[4]; - - memset (reg_data, 0, 4); - reg_data[0] = (uint8_t)(0x00ff & reg_val); - reg_data[1] = (uint8_t)((0xff00 & reg_val) >> 8); - reg_data[2] = (uint8_t)((0xff0000 & reg_val) >> 16); - reg_data[3] = (uint8_t)((0xff000000 & reg_val) >> 24); - - athrs26_header_write_reg (reg_addr, 4, reg_data); -#endif - -} - diff --git a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h b/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h deleted file mode 100644 index 0fdde376eb..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/athrs26_phy.h +++ /dev/null @@ -1,134 +0,0 @@ -#ifndef _ATHRS26_PHY_H -#define _ATHRS26_PHY_H - -/*****************/ -/* PHY Registers */ -/*****************/ -#define ATHR_PHY_CONTROL 0 -#define ATHR_PHY_STATUS 1 -#define ATHR_PHY_ID1 2 -#define ATHR_PHY_ID2 3 -#define ATHR_AUTONEG_ADVERT 4 -#define ATHR_LINK_PARTNER_ABILITY 5 -#define ATHR_AUTONEG_EXPANSION 6 -#define ATHR_NEXT_PAGE_TRANSMIT 7 -#define ATHR_LINK_PARTNER_NEXT_PAGE 8 -#define ATHR_1000BASET_CONTROL 9 -#define ATHR_1000BASET_STATUS 10 -#define ATHR_PHY_SPEC_CONTROL 16 -#define ATHR_PHY_SPEC_STATUS 17 -#define ATHR_DEBUG_PORT_ADDRESS 29 -#define ATHR_DEBUG_PORT_DATA 30 - -/* ATHR_PHY_CONTROL fields */ -#define ATHR_CTRL_SOFTWARE_RESET 0x8000 -#define ATHR_CTRL_SPEED_LSB 0x2000 -#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000 -#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200 -#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100 -#define ATHR_CTRL_SPEED_MSB 0x0040 - -#define ATHR_RESET_DONE(phy_control) \ - (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0) - -/* Phy status fields */ -#define ATHR_STATUS_AUTO_NEG_DONE 0x0020 - -#define ATHR_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & \ - (ATHR_STATUS_AUTO_NEG_DONE)) == \ - (ATHR_STATUS_AUTO_NEG_DONE)) - -/* Link Partner ability */ -#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100 -#define ATHR_LINK_100BASETX 0x0080 -#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040 -#define ATHR_LINK_10BASETX 0x0020 - -/* Advertisement register. */ -#define ATHR_ADVERTISE_NEXT_PAGE 0x8000 -#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800 -#define ATHR_ADVERTISE_PAUSE 0x0400 -#define ATHR_ADVERTISE_100FULL 0x0100 -#define ATHR_ADVERTISE_100HALF 0x0080 -#define ATHR_ADVERTISE_10FULL 0x0040 -#define ATHR_ADVERTISE_10HALF 0x0020 - -#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \ - ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL) - -/* 1000BASET_CONTROL */ -#define ATHR_ADVERTISE_1000FULL 0x0200 - -/* Phy Specific status fields */ -#define ATHER_STATUS_LINK_MASK 0xC000 -#define ATHER_STATUS_LINK_SHIFT 14 -#define ATHER_STATUS_FULL_DEPLEX 0x2000 -#define ATHR_STATUS_LINK_PASS 0x0400 -#define ATHR_STATUS_RESOVLED 0x0800 - -/*phy debug port register */ -#define ATHER_DEBUG_SERDES_REG 5 - -/* Serdes debug fields */ -#define ATHER_SERDES_BEACON 0x0100 - -#ifndef BOOL -#define BOOL int -#define TRUE 1 -#define FALSE 0 -#endif - -#define sysMsDelay(_x) udelay((_x) * 1000) - -#undef S26_VER_1_0 - -#ifdef CFG_ATHRHDR_EN - -#include <net.h> -#define header_xmit(dev,pkt,len) dev->send(dev,pkt,len) //dev_queue_xmit(skb) -#define header_recv_ack(dev) dev->recv(dev) //dev_queue_xmit(skb) - -typedef enum { - NORMAL_PACKET, - RESERVED0, - MIB_1ST, - RESERVED1, - RESERVED2, - READ_WRITE_REG, - READ_WRITE_REG_ACK, - RESERVED3 -} ATHR_HDR_TYPE; - -typedef struct { - uint16_t reserved0; - uint16_t priority; - uint16_t type ; - uint16_t broadcast; - uint16_t from_cpu; - uint16_t reserved1; - uint16_t port_num; -}at_header_t; - -typedef struct { - uint64_t reg_addr; - uint64_t reserved0; - uint64_t cmd_len; - uint64_t reserved1; - uint64_t cmd; - uint64_t reserved2; - uint64_t seq_num; -}reg_cmd_t; -void athrs26_reg_init(void); -int header_receive_pkt(uchar *pkt); -void athrs26_reg_dev(struct eth_device *mac); - -#endif - -int athrs26_phy_is_up(int unit); -int athrs26_phy_is_fdx(int unit); -int athrs26_phy_speed(int unit); -BOOL athrs26_phy_setup(int unit); - -#endif /* _ATHRS26_PHY_H */ - diff --git a/package/uboot-lantiq/files/board/arcadyan/board.c b/package/uboot-lantiq/files/board/arcadyan/board.c deleted file mode 100644 index 57f4603628..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/board.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2010 - * Thomas Langer, Ralph Hempel - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <miiphy.h> -#include <asm/addrspace.h> -#include <asm/danube.h> -#include <asm/reboot.h> -#include <asm/io.h> -#if defined(CONFIG_CMD_HTTPD) -#include <httpd.h> -#endif -#if defined(CONFIG_PCI) -#include <pci.h> -#endif -#if defined(CONFIG_AR8216_SWITCH) -#include "athrs26_phy.h" -#endif - -extern ulong ifx_get_ddr_hz(void); -extern ulong ifx_get_cpuclk(void); - -/* IDs and registers of known external switches */ -void _machine_restart(void) -{ - *DANUBE_RCU_RST_REQ |=1<<30; -} - -#ifdef CONFIG_SYS_RAMBOOT -phys_size_t initdram(int board_type) -{ - return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM); -} -#elif defined(CONFIG_USE_DDR_RAM) -phys_size_t initdram(int board_type) -{ - return (CONFIG_SYS_MAX_RAM); -} -#else - -static ulong max_sdram_size(void) /* per Chip Select */ -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 4 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - */ - -static long int dram_size(long int *base, long int maxsize) -{ - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - -phys_size_t initdram(int board_type) -{ - int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - /* load t9 into our_address */ - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - * find out whether running from DRAM or Flash. - */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *DANUBE_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *DANUBE_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} -#endif - -static void gpio_default(void) -{ -#ifdef CONFIG_SWITCH_PORT0 - *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN); -#elif defined(CONFIG_SWITCH_PORT1) - *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN); -#endif -#ifdef CONFIG_EBU_GPIO - { - int i = 0; - printf ("bring up ebu gpio\n"); - *DANUBE_EBU_BUSCON1 = 0x1e7ff; - *DANUBE_EBU_ADDSEL1 = 0x14000001; - - *((volatile u16*)0xb4000000) = 0x0; - for(i = 0; i < 1000; i++) - udelay(1000); - *((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO; - *DANUBE_EBU_BUSCON1 = 0x8001e7ff; - } -#endif -#ifdef CONFIG_BUTTON_PORT0 - *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN); - if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL) - { - printf("button is pressed\n"); - setenv("bootdelay", "0"); - setenv("bootcmd", "httpd"); - } -#elif defined(CONFIG_BUTTON_PORT1) - *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN); - if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL) - { - printf("button is pressed\n"); - setenv("bootdelay", "0"); - setenv("bootcmd", "httpd"); - } -#endif -#ifdef CONFIG_ARV4525 - *DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9)); - *DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9)); - *DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9)); - *DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9)); - *DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9)); -#endif -} - -int checkboard (void) -{ - unsigned long chipid = *DANUBE_MPS_CHIPID; - int part_num; - - puts ("Board: "CONFIG_ARCADYAN"\n"); - puts ("SoC: "); - - part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid); - switch (part_num) - { - case 0x129: - case 0x12D: - case 0x12b: - puts("Danube/Twinpass/Vinax-VE "); - break; - default: - printf ("unknown, chip part number 0x%03X ", part_num); - break; - } - printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid)); - - printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000); - printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000); - - - return 0; -} - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -int board_early_init_f(void) -{ -#ifdef CONFIG_EBU_ADDSEL0 - (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0; -#endif -#ifdef CONFIG_EBU_ADDSEL1 - (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1; -#endif -#ifdef CONFIG_EBU_ADDSEL2 - (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2; -#endif -#ifdef CONFIG_EBU_ADDSEL3 - (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3; -#endif -#ifdef CONFIG_EBU_BUSCON0 - (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0; -#endif -#ifdef CONFIG_EBU_BUSCON1 - (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1; -#endif -#ifdef CONFIG_EBU_BUSCON2 - (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2; -#endif -#ifdef CONFIG_EBU_BUSCON3 - (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3; -#endif - - return 0; -} -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifdef CONFIG_RTL8306_SWITCH -#define ID_RTL8306 0x5988 -static int external_switch_rtl8306(void) -{ - unsigned short chipid; - static char * const name = "lq_cpe_eth"; - - udelay(100000); - - puts("\nsearching for rtl8306 switch ... "); - if (miiphy_read(name, 4, 30, &chipid) == 0) { - if (chipid == ID_RTL8306) { - puts("found"); - /* set led mode */ - miiphy_write(name, 0, 19, 0xffff); - /* magic */ - miiphy_write(name, 4, 22, 0x877f); - puts("\n"); - return 0; - } - puts("failed\n"); - } - puts("\nno known switch found ... \n"); - - return 0; -} -#endif - -#ifdef CONFIG_RTL8306G_SWITCH -#define ID_RTL8306 0x5988 - -static int external_switch_rtl8306G(void) -{ - unsigned short chipid,val; - int i; - static char * const name = "lq_cpe_eth"; - unsigned int chipid2, chipver, chiptype; - char str[128]; - int cpu_mask = 1 << 5; - udelay(100000); - - puts("\nsearching for rtl8306 switch ... "); - if (miiphy_read(name, 4, 30, &chipid) == 0) { - if (chipid == ID_RTL8306) { - puts("found\nReset Hard\n"); -#ifdef CONFIG_ARV752DPW - //gpio 19 - //reset reset ping to high - *DANUBE_GPIO_P1_DIR |= 8; - *DANUBE_GPIO_P1_OUT |= 8; - udelay(500*1000); - *DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms - udelay(500*1000); - *DANUBE_GPIO_P1_OUT |= 8; - udelay(500*1000); - puts("Done\n"); -#endif - /* set led mode */ - - miiphy_write(name, 0, 0, 0x3100); - miiphy_write(name, 0, 18, 0x7fff); - miiphy_write(name, 0, 19, 0xffff); - miiphy_write(name, 0, 22, 0x877f); - miiphy_write(name, 0, 24, 0x0ed1); - - miiphy_write(name, 1, 0, 0x3100); - miiphy_write(name, 1, 22, 0x877f); - miiphy_write(name, 1, 24, 0x1ed2); - - miiphy_write(name, 2, 0, 0x3100); - miiphy_write(name, 2, 22, 0x877f); - miiphy_write(name, 2, 23, 0x0020); - miiphy_write(name, 2, 24, 0x2ed4); - - miiphy_write(name, 3, 0, 0x3100); - miiphy_write(name, 3, 22, 0x877f); - miiphy_write(name, 3, 24, 0x3ed8); - - miiphy_write(name, 4, 0, 0x3100); - miiphy_write(name, 4, 22, 0x877f); - miiphy_write(name, 4, 24, 0x4edf); - - miiphy_write(name, 5, 0, 0x3100); - miiphy_write(name, 6, 0, 0x2100); - - //important. enable phy 5 link status, for rmii - miiphy_write(name, 6, 22, 0x873f); - - miiphy_write(name, 6, 24, 0x8eff); - //disable ports - for (i=0;i<5;i++) { - miiphy_read(name, 0, 24, &val); - val&=~(1<<10); - val&=~(1<<11); - miiphy_write(name, 0, 24, val); - } - - puts("Reset Soft\n"); - miiphy_write(name,0 ,0 ,1<<15); - for (i=0;i<1000;i++) - { - miiphy_read(name,0 ,0 ,&val); - if (!(val&1<<15)) - break; - udelay(1000); - } - if (i==1000) - puts("Failed\n"); - else - puts("Success\n"); - //enable ports egain - for (i=0;i<5;i++) // enable ports - { - miiphy_read(name, 0, 24, &val); - val|=(1<<10); - val|=(1<<11); - miiphy_write(name, 0, 24, val); - } - puts("\n"); - return 0; - } - puts("failed\n"); - } - puts("\nno known switch found ... \n"); - - return 0; -} -#endif - -#ifdef CONFIG_AR8216_SWITCH -static int external_switch_ar8216(void) -{ - puts("initializing ar8216 switch... "); - if (athrs26_phy_setup(0)==0) { - printf("initialized\n"); - return 0; - } - puts("failed ... \n"); - return 0; -} -#endif - -int board_eth_init(bd_t *bis) -{ - gpio_default(); - -#if defined(CONFIG_IFX_ETOP) - uchar enetaddr[6]; - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016); - - *DANUBE_PMU_PWDCR &= 0xFFFFEFDF; - *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/ - - if (lq_eth_initialize(bis)) - return -1; - - *DANUBE_RCU_RST_REQ |=1; - udelay(200000); - *DANUBE_RCU_RST_REQ &=(unsigned long)~1; - udelay(1000); - -#ifdef CONFIG_RTL8306G_SWITCH - if (external_switch_rtl8306G()<0) - return -1; -#endif -#ifdef CONFIG_RTL8306_SWITCH - if (external_switch_rtl8306()<0) - return -1; -#endif -#ifdef CONFIG_AR8216_SWITCH - if (external_switch_ar8216()<0) - return -1; -#endif -#endif - return 0; -} - -#if defined(CONFIG_CMD_HTTPD) -int do_http_upgrade(const unsigned char *data, const ulong size) -{ - char buf[128]; - - if(getenv ("ram_addr") == NULL) - return -1; - if(getenv ("kernel_addr") == NULL) - return -1; - /* check the image */ - if(run_command("imi ${ram_addr}", 0) < 0) { - return -1; - } - /* write the image to the flash */ - puts("http ugrade ...\n"); - sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size); - return run_command(buf, 0); -} - -int do_http_progress(const int state) -{ - /* toggle LED's here */ - switch(state) { - case HTTP_PROGRESS_START: - puts("http start\n"); - break; - case HTTP_PROGRESS_TIMEOUT: - puts("."); - break; - case HTTP_PROGRESS_UPLOAD_READY: - puts("http upload ready\n"); - break; - case HTTP_PROGRESS_UGRADE_READY: - puts("http ugrade ready\n"); - break; - case HTTP_PROGRESS_UGRADE_FAILED: - puts("http ugrade failed\n"); - break; - } - return 0; -} - -unsigned long do_http_tmp_address(void) -{ - char *s = getenv ("ram_addr"); - if (s) { - ulong tmp = simple_strtoul (s, NULL, 16); - return tmp; - } - return 0 /*0x80a00000*/; -} - -#endif diff --git a/package/uboot-lantiq/files/board/arcadyan/config.mk b/package/uboot-lantiq/files/board/arcadyan/config.mk deleted file mode 100644 index cc8cd30906..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifdef CONFIG_BOOTSTRAP -TEXT_BASE = 0x80001000 -CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000 -CONFIG_SYS_RAMBOOT = y -else - -ifndef TEXT_BASE -$(info redefine TEXT_BASE = 0xB0000000 ) -TEXT_BASE = 0xB0000000 -endif - -endif diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h deleted file mode 100644 index 4df6f1170c..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x130 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1b00 -#define MC_DC22_VALUE 0x1b1b -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h deleted file mode 100644 index 445b7dac1f..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1700 -#define MC_DC22_VALUE 0x1717 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h deleted file mode 100644 index c5afb8e21c..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h +++ /dev/null @@ -1,47 +0,0 @@ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x134 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1400 -#define MC_DC22_VALUE 0x1414 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5b /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S b/package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S deleted file mode 100644 index 4747ad6db2..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Memory sub-system initialization code for Danube board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#if defined(CONFIG_USE_DDR_PSC_32) -#include "ddr_settings_psc_32.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_PSC_64) -#include "ddr_settings_psc_64.h" -#define DDR166 -#else -#error "missing definition for RAM" -#endif - -#define EBU_MODUL_BASE 0xBE105300 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(void) - */ - .globl ebu_init - .ent ebu_init -ebu_init: - -#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \ - defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \ - defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \ - defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3) - - li t1, EBU_MODUL_BASE -#if defined(CONFIG_EBU_ADDSEL0) - li t2, CONFIG_EBU_ADDSEL0 - sw t2, EBU_ADDSEL0(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL1) - li t2, CONFIG_EBU_ADDSEL1 - sw t2, EBU_ADDSEL1(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL2) - li t2, CONFIG_EBU_ADDSEL2 - sw t2, EBU_ADDSEL2(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL3) - li t2, CONFIG_EBU_ADDSEL3 - sw t2, EBU_ADDSEL3(t1) -#endif - -#if defined(CONFIG_EBU_BUSCON0) - li t2, CONFIG_EBU_BUSCON0 - sw t2, EBU_BUSCON0(t1) -#endif -#if defined(CONFIG_EBU_BUSCON1) - li t2, CONFIG_EBU_BUSCON1 - sw t2, EBU_BUSCON1(t1) -#endif -#if defined(CONFIG_EBU_BUSCON2) - li t2, CONFIG_EBU_BUSCON2 - sw t2, EBU_BUSCON2(t1) -#endif -#if defined(CONFIG_EBU_BUSCON3) - li t2, CONFIG_EBU_BUSCON3 - sw t2, EBU_BUSCON3(t1) -#endif - -#endif - - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - - .end cgu_init - -#ifndef CONFIG_USE_DDR_RAM -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - j ra - nop - - .end sdram_init - -#endif /* !CONFIG_USE_DDR_RAM */ - -#ifdef CONFIG_USE_DDR_RAM -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - .end ddrram_init -#endif /* CONFIG_USE_DDR_RAM */ - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that non of the following ..._init() functions - * modify t0 - */ -#if defined(DDR166) - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 -#elif defined(DDR133) - /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */ - li a0,0xe9 -#else /* defined(DDR111) */ - /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */ - li a0,0xea -#endif - bal cgu_init - nop - - bal ebu_init - nop - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef CONFIG_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S b/package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S deleted file mode 100644 index d9fe38bc67..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Memory sub-system initialization code for Danube board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#if defined(CONFIG_USE_DDR_PSC_32) -#include "ddr_settings_psc_32.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_PSC_64) -#include "ddr_settings_psc_64.h" -#define DDR166 -#else -#error "missing definition for RAM" -#endif - -#define EBU_MODUL_BASE 0xBE105300 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(void) - */ - .globl ebu_init - .ent ebu_init -ebu_init: - - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - - .end cgu_init - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that non of the following ..._init() functions - * modify t0 - */ - - bal ebu_init - nop - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-lantiq/files/board/arcadyan/pmuenable.S b/package/uboot-lantiq/files/board/arcadyan/pmuenable.S deleted file mode 100644 index e0d7971d89..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/pmuenable.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power Management unit initialization code for AMAZON development board. - * - * Copyright (c) 2003 Ou Ke, Infineon. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#define PMU_PWDCR 0xBF10201C -#define PMU_SR 0xBF102020 - - .globl pmuenable - -pmuenable: - li t0, PMU_PWDCR - li t1, 0x2 /* enable everything */ - sw t1, 0(t0) -#if 0 -1: - li t0, PMU_SR - lw t2, 0(t0) - bne t1, t2, 1b - nop -#endif - j ra - nop - - diff --git a/package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds b/package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds deleted file mode 100644 index 52d7dafadb..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2010 Industrie Dial Face S.p.A. - * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com - * - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = .; - _gp = ALIGN(16) +0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - . = .; - . = ALIGN(4); - .payload : { *(.payload) } - . = ALIGN(4); - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) . = ALIGN(4); } - uboot_end = .; -} - diff --git a/package/uboot-lantiq/files/board/arcadyan/u-boot.lds b/package/uboot-lantiq/files/board/arcadyan/u-boot.lds deleted file mode 100644 index 9a6cd1b8a3..0000000000 --- a/package/uboot-lantiq/files/board/arcadyan/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - .sdata : { *(.sdata) } - - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - uboot_end = .; -} diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/Makefile b/package/uboot-lantiq/files/board/infineon/easy50712/Makefile deleted file mode 100644 index 67570505d9..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a -BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a - -BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - -COBJS-y += danube.o - -SOBJS = lowlevel_init.o pmuenable.o - -BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o -BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o - -BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c) - -SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S)) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y)) -BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y)) - - -all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS) - $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/config.mk b/package/uboot-lantiq/files/board/infineon/easy50712/config.mk deleted file mode 100644 index b110f6f329..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Danube board with MIPS 24Kc CPU core -# -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifdef CONFIG_BOOTSTRAP -TEXT_BASE = 0x80001000 -CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000 -CONFIG_SYS_RAMBOOT = y -else - -ifndef TEXT_BASE -$(info redefine TEXT_BASE = 0xB0000000 ) -TEXT_BASE = 0xB0000000 -endif - -endif diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c b/package/uboot-lantiq/files/board/infineon/easy50712/danube.c deleted file mode 100644 index e3845cb38f..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2010 - * Thomas Langer, Ralph Hempel - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <miiphy.h> -#include <asm/addrspace.h> -#include <asm/danube.h> -#include <asm/reboot.h> -#include <asm/io.h> -#if defined(CONFIG_CMD_HTTPD) -#include <httpd.h> -#endif - -extern ulong ifx_get_ddr_hz(void); -extern ulong ifx_get_cpuclk(void); - -/* definitions for external PHYs / Switches */ -/* Split values into phy address and register address */ -#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) - -/* IDs and registers of known external switches */ -#define ID_SAMURAI_0 0x1020 -#define ID_SAMURAI_1 0x0007 -#define SAMURAI_ID_REG0 0xA0 -#define SAMURAI_ID_REG1 0xA1 - -#define ID_TANTOS 0x2599 - -void _machine_restart(void) -{ - *DANUBE_RCU_RST_REQ |=1<<30; -} - -#ifdef CONFIG_SYS_RAMBOOT -phys_size_t initdram(int board_type) -{ - return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM); -} -#elif defined(CONFIG_USE_DDR_RAM) -phys_size_t initdram(int board_type) -{ - return (CONFIG_SYS_MAX_RAM); -} -#else - -static ulong max_sdram_size(void) /* per Chip Select */ -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 4 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - */ - -static long int dram_size(long int *base, long int maxsize) -{ - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - -phys_size_t initdram(int board_type) -{ - int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - /* load t9 into our_address */ - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - * find out whether running from DRAM or Flash. - */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *DANUBE_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *DANUBE_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} -#endif - -int checkboard (void) -{ - unsigned long chipid = *DANUBE_MPS_CHIPID; - int part_num; - - puts ("Board: "); - - part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid); - switch (part_num) - { - case 0x129: - case 0x12B: - case 0x12D: - puts("Danube/Twinpass/Vinax-VE "); - break; - default: - printf ("unknown, chip part number 0x%03X ", part_num); - break; - } - printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid)); - - printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000); - printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000); - - return 0; -} - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -int board_early_init_f(void) -{ -#ifdef CONFIG_EBU_ADDSEL0 - (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0; -#endif -#ifdef CONFIG_EBU_ADDSEL1 - (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1; -#endif -#ifdef CONFIG_EBU_ADDSEL2 - (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2; -#endif -#ifdef CONFIG_EBU_ADDSEL3 - (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3; -#endif -#ifdef CONFIG_EBU_BUSCON0 - (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0; -#endif -#ifdef CONFIG_EBU_BUSCON1 - (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1; -#endif -#ifdef CONFIG_EBU_BUSCON2 - (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2; -#endif -#ifdef CONFIG_EBU_BUSCON3 - (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3; -#endif - - return 0; -} -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifdef CONFIG_EXTRA_SWITCH -static int external_switch_init(void) -{ - unsigned short chipid0=0xdead, chipid1=0xbeef; - static char * const name = "lq_cpe_eth"; - -#ifdef CONFIG_SWITCH_PORT0 - *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN); -#elif defined(CONFIG_SWITCH_PORT1) - *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN); - *DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN); -#endif -#ifdef CLK_OUT2_25MHZ - *DANUBE_GPIO_P0_DIR=0x0000ae78; - *DANUBE_GPIO_P0_ALTSEL0=0x00008078; - //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080; - *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1 - *DANUBE_CGU_IFCCR=0x00400010; - *DANUBE_GPIO_P0_OD=0x0000ae78; -#endif - - /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */ - udelay(100000); - - debug("\nsearching for Samurai switch ... "); - if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) && - (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) { - if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) && - ((chipid1 & 0x000F) == ID_SAMURAI_1)) { - debug("found"); - - /* enable "Crossover Auto Detect" + defaults */ - /* P0 */ - miiphy_write(name, PHYADDR(0x01), 0x840F); - /* P1 */ - miiphy_write(name, PHYADDR(0x03), 0x840F); - /* P2 */ - miiphy_write(name, PHYADDR(0x05), 0x840F); - /* P3 */ - miiphy_write(name, PHYADDR(0x07), 0x840F); - /* P4 */ - miiphy_write(name, PHYADDR(0x08), 0x840F); - /* P5 */ - miiphy_write(name, PHYADDR(0x09), 0x840F); - /* System Control 4: CPU on port 1 and other */ - miiphy_write(name, PHYADDR(0x12), 0x3602); - #ifdef CLK_OUT2_25MHZ - /* Bandwidth Control Enable Register: enable */ - miiphy_write(name, PHYADDR(0x33), 0x4000); - #endif - } - } - - debug("\nsearching for TANTOS switch ... "); - if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) { - if (chipid0 == ID_TANTOS) { - debug("found"); - - /* P5 Basic Control: Force Link Up */ - miiphy_write(name, PHYADDR(0xA1), 0x0004); - /* P6 Basic Control: Force Link Up */ - miiphy_write(name, PHYADDR(0xC1), 0x0004); - /* RGMII/MII Port Control (P4/5/6) */ - miiphy_write(name, PHYADDR(0xF5), 0x0773); - - /* Software workaround. */ - /* PHY reset from P0 to P4. */ - - /* set data for indirect write */ - miiphy_write(name, PHYADDR(0x121), 0x8000); - - /* P0 */ - miiphy_write(name, PHYADDR(0x120), 0x0400); - udelay(1000); - /* P1 */ - miiphy_write(name, PHYADDR(0x120), 0x0420); - udelay(1000); - /* P2 */ - miiphy_write(name, PHYADDR(0x120), 0x0440); - udelay(1000); - /* P3 */ - miiphy_write(name, PHYADDR(0x120), 0x0460); - udelay(1000); - /* P4 */ - miiphy_write(name, PHYADDR(0x120), 0x0480); - udelay(1000); - } - } - debug("\n"); - - return 0; -} -#endif /* CONFIG_EXTRA_SWITCH */ - -int board_gpio_init(void) -{ -#ifdef CONFIG_BUTTON_PORT0 - *DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN); - if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL) - { - printf("button is pressed\n"); - setenv("bootdelay", "0"); - setenv("bootcmd", "httpd"); - } -#elif defined(CONFIG_BUTTON_PORT1) - *DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN); - *DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN); - if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL) - { - printf("button is pressed\n"); - setenv("bootdelay", "0"); - setenv("bootcmd", "httpd"); - } -#endif -} - -int board_eth_init(bd_t *bis) -{ - - board_gpio_init(); - -#if defined(CONFIG_IFX_ETOP) - - *DANUBE_PMU_PWDCR &= 0xFFFFEFDF; - *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/ - - if (lq_eth_initialize(bis)<0) - return -1; - - *DANUBE_RCU_RST_REQ |=1; - udelay(200000); - *DANUBE_RCU_RST_REQ &=(unsigned long)~1; - udelay(1000); - -#ifdef CONFIG_EXTRA_SWITCH - if (external_switch_init()<0) - return -1; -#endif /* CONFIG_EXTRA_SWITCH */ -#endif /* CONFIG_IFX_ETOP */ - - return 0; -} - -#if defined(CONFIG_CMD_HTTPD) -int do_http_upgrade(const unsigned char *data, const ulong size) -{ - char buf[128]; - - if(getenv ("ram_addr") == NULL) - return -1; - if(getenv ("kernel_addr") == NULL) - return -1; - /* check the image */ - if(run_command("imi ${ram_addr}", 0) < 0) { - return -1; - } - /* write the image to the flash */ - puts("http ugrade ...\n"); - sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size); - return run_command(buf, 0); -} - -int do_http_progress(const int state) -{ - /* toggle LED's here */ - switch(state) { - case HTTP_PROGRESS_START: - puts("http start\n"); - break; - case HTTP_PROGRESS_TIMEOUT: - puts("."); - break; - case HTTP_PROGRESS_UPLOAD_READY: - puts("http upload ready\n"); - break; - case HTTP_PROGRESS_UGRADE_READY: - puts("http ugrade ready\n"); - break; - case HTTP_PROGRESS_UGRADE_FAILED: - puts("http ugrade failed\n"); - break; - } - return 0; -} - -unsigned long do_http_tmp_address(void) -{ - char *s = getenv ("ram_addr"); - if (s) { - ulong tmp = simple_strtoul (s, NULL, 16); - return tmp; - } - return 0 /*0x80a00000*/; -} - -#endif diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h deleted file mode 100644 index 3a4b1350e4..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 -#define MC_DC21_VALUE 0x1d00 -#define MC_DC22_VALUE 0x1d1d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* was 0x7f */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h deleted file mode 100644 index 54bb6c9e37..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_PROMOSDDR400.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xa02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x0 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h deleted file mode 100644 index 7975c3ec0d..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_Samsung_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1400 -#define MC_DC22_VALUE 0x1414 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d93 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h deleted file mode 100644 index b655ca2898..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h deleted file mode 100644 index b655ca2898..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_e166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h deleted file mode 100644 index 445b7dac1f..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_psc_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1700 -#define MC_DC22_VALUE 0x1717 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h deleted file mode 100644 index fd155973ee..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h deleted file mode 100644 index 742d34f1d3..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0xd00 -#define MC_DC22_VALUE 0xd0d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c b/package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c deleted file mode 100644 index 11bf6d0b71..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/easy50712_bootstrap.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2010 Industrie Dial Face S.p.A. - * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com - * - * (C) Copyright 2007 - * Vlad Lungu vlad.lungu@windriver.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/mipsregs.h> -#include <asm/io.h> - -phys_size_t bootstrap_initdram(int board_type) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - return CONFIG_SYS_MAX_RAM; -} - -int bootstrap_checkboard(void) -{ - return 0; -} - -int bootstrap_misc_init_r(void) -{ - set_io_port_base(0); - return 0; -} diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S b/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S deleted file mode 100644 index 216c381455..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_bootstrap_init.S +++ /dev/null @@ -1,606 +0,0 @@ -/* - * Memory sub-system initialization code for Danube board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#if defined(CONFIG_USE_DDR_RAM) - -#if defined(CONFIG_USE_DDR_RAM_CFG_111M) -#include "ddr_settings_r111.h" -#define DDR111 -#elif defined(CONFIG_USE_DDR_RAM_CFG_166M) -#include "ddr_settings_r166.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M) -#include "ddr_settings_e111.h" -#define DDR111 -#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M) -#include "ddr_settings_e166.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400) -#include "ddr_settings_PROMOSDDR400.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166) -#include "ddr_settings_Samsung_166.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166) -#include "ddr_settings_psc_166.h" -#define DDR166 -#else -#warning "missing definition for ddr_settings.h, use default!" -#include "ddr_settings.h" -#endif -#endif /* CONFIG_USE_DDR_RAM */ - -#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE) -#error "missing include of ddr_settings.h" -#endif - -#define EBU_MODUL_BASE 0xBE105300 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(void) - */ - .globl ebu_init - .ent ebu_init -ebu_init: - -#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \ - defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \ - defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \ - defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3) - - li t1, EBU_MODUL_BASE -#if defined(CONFIG_EBU_ADDSEL0) - li t2, CONFIG_EBU_ADDSEL0 - sw t2, EBU_ADDSEL0(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL1) - li t2, CONFIG_EBU_ADDSEL1 - sw t2, EBU_ADDSEL1(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL2) - li t2, CONFIG_EBU_ADDSEL2 - sw t2, EBU_ADDSEL2(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL3) - li t2, CONFIG_EBU_ADDSEL3 - sw t2, EBU_ADDSEL3(t1) -#endif - -#if defined(CONFIG_EBU_BUSCON0) - li t2, CONFIG_EBU_BUSCON0 - sw t2, EBU_BUSCON0(t1) -#endif -#if defined(CONFIG_EBU_BUSCON1) - li t2, CONFIG_EBU_BUSCON1 - sw t2, EBU_BUSCON1(t1) -#endif -#if defined(CONFIG_EBU_BUSCON2) - li t2, CONFIG_EBU_BUSCON2 - sw t2, EBU_BUSCON2(t1) -#endif -#if defined(CONFIG_EBU_BUSCON3) - li t2, CONFIG_EBU_BUSCON3 - sw t2, EBU_BUSCON3(t1) -#endif - -#endif - - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - - .end cgu_init - -#ifndef CONFIG_USE_DDR_RAM -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - j ra - nop - - .end sdram_init - -#endif /* !CONFIG_USE_DDR_RAM */ - -#ifdef CONFIG_USE_DDR_RAM -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - .end ddrram_init -#endif /* CONFIG_USE_DDR_RAM */ - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that non of the following ..._init() functions - * modify t0 - */ -#if defined(DDR166) - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 -#elif defined(DDR133) - /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */ - li a0,0xe9 -#else /* defined(DDR111) */ - /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */ - li a0,0xea -#endif - bal cgu_init - nop - - bal ebu_init - nop - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef CONFIG_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S b/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S deleted file mode 100644 index 4dc179fc05..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/lowlevel_init.S +++ /dev/null @@ -1,613 +0,0 @@ -/* - * Memory sub-system initialization code for Danube board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#if defined(CONFIG_USE_DDR_RAM) - -#if defined(CONFIG_USE_DDR_RAM_CFG_111M) -#include "ddr_settings_r111.h" -#define DDR111 -#elif defined(CONFIG_USE_DDR_RAM_CFG_166M) -#include "ddr_settings_r166.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M) -#include "ddr_settings_e111.h" -#define DDR111 -#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M) -#include "ddr_settings_e166.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400) -#include "ddr_settings_PROMOSDDR400.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166) -#include "ddr_settings_Samsung_166.h" -#define DDR166 -#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166) -#include "ddr_settings_psc_166.h" -#define DDR166 -#else -#warning "missing definition for ddr_settings.h, use default!" -#include "ddr_settings.h" -#endif -#endif /* CONFIG_USE_DDR_RAM */ - -#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE) -#error "missing include of ddr_settings.h" -#endif - -#define EBU_MODUL_BASE 0xBE105300 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(void) - */ - .globl ebu_init - .ent ebu_init -ebu_init: - -#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \ - defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \ - defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \ - defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3) - - li t1, EBU_MODUL_BASE -#if defined(CONFIG_EBU_ADDSEL0) - li t2, CONFIG_EBU_ADDSEL0 - sw t2, EBU_ADDSEL0(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL1) - li t2, CONFIG_EBU_ADDSEL1 - sw t2, EBU_ADDSEL1(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL2) - li t2, CONFIG_EBU_ADDSEL2 - sw t2, EBU_ADDSEL2(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL3) - li t2, CONFIG_EBU_ADDSEL3 - sw t2, EBU_ADDSEL3(t1) -#endif - -#if defined(CONFIG_EBU_BUSCON0) - li t2, CONFIG_EBU_BUSCON0 - sw t2, EBU_BUSCON0(t1) -#endif -#if defined(CONFIG_EBU_BUSCON1) - li t2, CONFIG_EBU_BUSCON1 - sw t2, EBU_BUSCON1(t1) -#endif -#if defined(CONFIG_EBU_BUSCON2) - li t2, CONFIG_EBU_BUSCON2 - sw t2, EBU_BUSCON2(t1) -#endif -#if defined(CONFIG_EBU_BUSCON3) - li t2, CONFIG_EBU_BUSCON3 - sw t2, EBU_BUSCON3(t1) -#endif - -#endif - - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - - .end cgu_init - -#ifndef CONFIG_USE_DDR_RAM -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - j ra - nop - - .end sdram_init - -#endif /* !CONFIG_USE_DDR_RAM */ - -#ifdef CONFIG_USE_DDR_RAM -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - .end ddrram_init -#endif /* CONFIG_USE_DDR_RAM */ - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that non of the following ..._init() functions - * modify t0 - */ -#if defined(CONFIG_SYS_EBU_BOOT) -#if defined(DDR166) - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 -#elif defined(DDR133) - /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */ - li a0,0xe9 -#else /* defined(DDR111) */ - /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */ - li a0,0xea -#endif - bal cgu_init - nop -#endif /* CONFIG_SYS_EBU_BOOT */ - - bal ebu_init - nop - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef CONFIG_SYS_EBU_BOOT -#ifndef CONFIG_SYS_RAMBOOT -#ifdef CONFIG_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif -#endif /* CONFIG_SYS_RAMBOOT */ -#endif /* CONFIG_SYS_EBU_BOOT */ - - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S b/package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S deleted file mode 100644 index e0d7971d89..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/pmuenable.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power Management unit initialization code for AMAZON development board. - * - * Copyright (c) 2003 Ou Ke, Infineon. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#define PMU_PWDCR 0xBF10201C -#define PMU_SR 0xBF102020 - - .globl pmuenable - -pmuenable: - li t0, PMU_PWDCR - li t1, 0x2 /* enable everything */ - sw t1, 0(t0) -#if 0 -1: - li t0, PMU_SR - lw t2, 0(t0) - bne t1, t2, 1b - nop -#endif - j ra - nop - - diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds b/package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds deleted file mode 100644 index 52d7dafadb..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot-bootstrap.lds +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2010 Industrie Dial Face S.p.A. - * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com - * - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = .; - _gp = ALIGN(16) +0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - . = .; - . = ALIGN(4); - .payload : { *(.payload) } - . = ALIGN(4); - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) . = ALIGN(4); } - uboot_end = .; -} - diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds b/package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds deleted file mode 100644 index 9a6cd1b8a3..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50712/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - .sdata : { *(.sdata) } - - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - uboot_end = .; -} diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/Makefile b/package/uboot-lantiq/files/board/infineon/easy50812/Makefile deleted file mode 100644 index 97d1898954..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a -BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a - -BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - -COBJS-y += ar9.o - -SOBJS = lowlevel_init.o pmuenable.o - -BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o -BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o - -BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c) - -SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S)) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y)) -BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y)) - - -all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS) - $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9.c b/package/uboot-lantiq/files/board/infineon/easy50812/ar9.c deleted file mode 100644 index d4cd049afe..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9.c +++ /dev/null @@ -1,619 +0,0 @@ -/* -* (C) Copyright 2003 -* Wolfgang Denk, DENX Software Engineering, wd@denx.de. -* -* (C) Copyright 2010 -* Thomas Langer, Ralph Hempel -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <miiphy.h> -#include <asm/addrspace.h> -#include <asm/ar9.h> -#include <asm/reboot.h> -#include <asm/io.h> -#if defined(CONFIG_CMD_HTTPD) -#include <httpd.h> -#endif - -extern ulong ifx_get_ddr_hz(void); -extern ulong ifx_get_cpuclk(void); - -/* definitions for external PHYs / Switches */ -/* Split values into phy address and register address */ -#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) - -/* IDs and registers of known external switches */ -#define ID_SAMURAI_0 0x1020 -#define ID_SAMURAI_1 0x0007 -#define SAMURAI_ID_REG0 0xA0 -#define SAMURAI_ID_REG1 0xA1 -#define ID_TANTOS 0x2599 - -#define RGMII_MODE 0 -#define MII_MODE 1 -#define REV_MII_MODE 2 -#define RED_MII_MODE_IC 3 /*Input clock */ -#define RGMII_MODE_100MB 4 -#define TURBO_REV_MII_MODE 6 /*Turbo Rev Mii mode */ -#define RED_MII_MODE_OC 7 /*Output clock */ -#define RGMII_MODE_10MB 8 - -#define mdelay(n) udelay((n)*1000) - -static void ar9_sw_chip_init(u8 port, u8 mode); -static void ar9_enable_sw_port(u8 port, u8 state); -static void ar9_configure_sw_port(u8 port, u8 mode); -static u16 ar9_smi_reg_read(u16 reg); -static u16 ar9_smi_reg_write(u16 reg, u16 data); -static char * const name = "lq_cpe_eth"; -static int external_switch_init(void); - -void _machine_restart(void) -{ - *AR9_RCU_RST_REQ |= AR9_RST_ALL; -} - -#ifdef CONFIG_SYS_RAMBOOT -phys_size_t initdram(int board_type) -{ - return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM); -} -#elif defined(CONFIG_USE_DDR_RAM) -phys_size_t initdram(int board_type) -{ - return (CONFIG_SYS_MAX_RAM); -} -#else - -static ulong max_sdram_size(void) /* per Chip Select */ -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 4 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -/* -* Check memory range for valid RAM. A simple memory test determines -* the actually available RAM size between addresses `base' and -* `base + maxsize'. -*/ - -static long int dram_size(long int *base, long int maxsize) -{ - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - -phys_size_t initdram(int board_type) -{ - int rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - /* load t9 into our_address */ - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - * find out whether running from DRAM or Flash. - */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *AR9_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *AR9_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} -#endif - -int checkboard (void) -{ - unsigned long chipid = *AR9_MPS_CHIPID; - int part_num; - - puts ("Board: "); - - part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid); - switch (part_num) - { - case 0x16C: - puts("ARX188 "); - break; - case 0x16D: - puts("ARX168 "); - break; - case 0x16F: - puts("ARX182 "); - break; - case 0x170: - puts("GRX188 "); - break; - case 0x171: - puts("GRX168 "); - break; - default: - printf ("unknown, chip part number 0x%03X ", part_num); - break; - } - printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid)); - - printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000); - printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000); - - return 0; -} - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -int board_early_init_f(void) -{ -#ifdef CONFIG_EBU_ADDSEL0 - (*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0; -#endif -#ifdef CONFIG_EBU_ADDSEL1 - (*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1; -#endif -#ifdef CONFIG_EBU_ADDSEL2 - (*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2; -#endif -#ifdef CONFIG_EBU_ADDSEL3 - (*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3; -#endif -#ifdef CONFIG_EBU_BUSCON0 - (*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0; -#endif -#ifdef CONFIG_EBU_BUSCON1 - (*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1; -#endif -#ifdef CONFIG_EBU_BUSCON2 - (*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2; -#endif -#ifdef CONFIG_EBU_BUSCON3 - (*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3; -#endif - - return 0; -} -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_IFX_ETOP) - - *AR9_PMU_PWDCR &= 0xFFFFEFDF; - *AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */ - - if (lq_eth_initialize(bis) < 0) - return -1; - - *AR9_RCU_RST_REQ |= 1; - udelay(200000); - *AR9_RCU_RST_REQ &= (unsigned long)~1; - udelay(1000); - -#ifdef CONFIG_EXTRA_SWITCH - if (external_switch_init()<0) - return -1; -#endif /* CONFIG_EXTRA_SWITCH */ -#endif /* CONFIG_IFX_ETOP */ - - return 0; -} - -static void ar9_configure_sw_port(u8 port, u8 mode) -{ - if(port) - { - if (mode == 1) //MII mode - { - *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000); - *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000); - *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000; - *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000; - } - else if(mode == 2 || mode == 6) //Rev Mii mode - { - *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000); - *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000); - *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000; - *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000; - } - } - else //Port 0 - { - if (mode == 1) //MII mode - { - *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303); - *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303); - *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100; - *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100; - } - else if(mode ==2 || mode ==6) //Rev Mii mode - { - *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303); - *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303); - *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100; - *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203; - } - } -} - -/* -Call this function to place either MAC port 0 or 1 into working mode. -Parameters: -port - select ports 0 or 1. -state of interface : state -0: RGMII -1: MII -2: Rev MII -3: Reduce MII (input clock) -4: RGMII 100mb -5: Reserve -6: Turbo Rev MII -7: Reduce MII (output clock) -*/ -void ar9_enable_sw_port(u8 port, u8 state) -{ - REG32(AR9_SW_GCTL0) |= 0x80000000; - if (port == 0) - { - REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ; - //#if AR9_REFBOARD_TANTOS - REG32(0xbf20302c) &= 0xffff81ff; - REG32(0xbf20302c) |= 4<<9 ; - //#endif - REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8; - if((state &0x3) == 0) - { - REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3; - if(state == 4) - REG32(AR9_SW_RGMII_CTL) |= 0x4; - else - REG32(AR9_SW_RGMII_CTL) |= 0x8; - } - if(state == 6) - REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20)); - if(state == 7) - REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21)); - } -// *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe; - else - { - REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ; - REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18; - if((state &0x3) == 0) - { - REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff; - if(state == 4) - REG32(AR9_SW_RGMII_CTL) |= 0x1000; - else - REG32(AR9_SW_RGMII_CTL) |= 0x2000; - } - if(state == 6) - REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22)); - if(state == 7) - REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23)); - } -} - -void pci_reset(void) -{ - int i,j; -#define AR9_V1_PCI_RST_FIX 1 -#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST - *AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8; - *AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8; - *AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8; - *AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8; - *AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8; - *AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000; - *AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000; - *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000; - *AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000; - for(j=0;j<5;j++) { - *AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000; - for(i=0;i<0x10000;i++); - *AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000; - for(i=0;i<0x10000;i++); - } - *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR & ~0x4000; - *AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR & ~0x8; -#endif -} - -static u16 ar9_smi_reg_read(u16 reg) -{ - int i; - while(REG32(AR9_SW_MDIO_CTL) & 0x8000); - REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/ - for(i=0;i<0x3fff;i++); - udelay(50); - while(REG32(AR9_SW_MDIO_CTL) & 0x8000); - return((u16) (REG32(AR9_SW_MDIO_DATA))); -} - -static u16 ar9_smi_reg_write(u16 reg, u16 data) -{ - int i; - while(REG32(AR9_SW_MDIO_CTL) & 0x8000); - REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/ - for(i=0;i<0x3fff;i++); - udelay(50); - return 0; -} - -static void ar9_sw_chip_init(u8 port, u8 mode) -{ - int i; - u16 chipid; - - debug("\nsearching for switches ... "); - - asm("sync"); - pci_reset(); - - /* 25mhz clock out */ - *AR9_CGU_IFCCR &= ~(3<<10); - *AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3); - *AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3); - *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | (1<<3); - *AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3); - *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0); - *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0); - *AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | (1<<0); - *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0); - - *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ; - *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH)); - *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P); - - *AR9_GPIO_P2_OUT &= ~(1<<0); - asm("sync"); - - ar9_configure_sw_port(port, mode); - ar9_enable_sw_port(port, mode); - REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */ - asm("sync"); - - /*GPIO 55(P3.7) used as output, set high*/ - *AR9_GPIO_P3_OD |=(1<<7); - *AR9_GPIO_P3_DIR |= (1<<7); - *AR9_GPIO_P3_ALTSEL0 &=~(1<<7); - *AR9_GPIO_P3_ALTSEL1 &=~(1<<7); - asm("sync"); - udelay(10); - - *AR9_GPIO_P3_OUT &= ~(1<<7); - for(i=0;i<1000;i++) - udelay(110); - *AR9_GPIO_P3_OUT |=(1<<7); - udelay(100); - - if(port==0) - REG32(AR9_SW_P0_CTL) |= 0x40001; - else - REG32(AR9_SW_P1_CTL) |= 0x40001; - - REG32(AR9_SW_P2_CTL) |= 0x40001; - REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */ - - *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00); - *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00); - *AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | 0xc00; - *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00; - - asm("sync"); - chipid = (unsigned short)(ar9_smi_reg_read(0x101)); - printf("\nswitch chip id=%08x\n",chipid); - if (chipid != ID_TANTOS) { - debug("whatever detected\n"); - ar9_smi_reg_write(0x1,0x840f); - ar9_smi_reg_write(0x3,0x840f); - ar9_smi_reg_write(0x5,0x840f); - ar9_smi_reg_write(0x7,0x840f); - ar9_smi_reg_write(0x8,0x840f); - ar9_smi_reg_write(0x12,0x3602); -#ifdef CLK_OUT2_25MHZ - ar9_smi_reg_write(0x33,0x4000); -#endif - } else { // Tantos switch ship - debug("Tantos switch detected\n"); - ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/ - ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/ - ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/ - /*port 5 duplex mode, flow control enable, 1000Mbit/s*/ - /*port 6 duplex mode, flow control enable, 1000Mbit/s*/ - } - asm("sync"); - - /*reset GPHY*/ - mdelay(200); - *AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ; - udelay(50); - *AR9_GPIO_P2_OUT |= (1<<0); -} - -static void ar9_dma_init(void) -{ - /* select port */ - *AR9_DMA_PS = 0; - - /* - TXWGT 14:12 rw Port Weight for Transmit Direction (the default value “001”) - - TXENDI 11:10 rw Endianness for Transmit Direction - Determine a byte swap between memory interface (left hand side) and - peripheral interface (right hand side). - 00B B0_B1_B2_B3 No byte switching - 01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2 - 10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1 - - RXENDI 9:8 rw Endianness for Receive Direction - Determine a byte swap between peripheral (left hand side) and memory - interface (right hand side). - 00B B0_B1_B2_B3 No byte switching - 01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2 - 10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1 - 11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0 - - TXBL 5:4 rw Burst Length for Transmit Direction - Selects burst length for TX direction. - Others are reserved and will result in 2_WORDS burst length. - 01B 2_WORDS 2 words - 10B 4_WORDS 4 words - 11B 8_WORDS 8 words - - RXBL 3:2 rw Burst Length for Receive Direction - Selects burst length for RX direction. - Others are reserved and will result in 2_WORDS burst length. - 01B 2_WORDS 2 words - 10B 4_WORDS 4 words - 11B 8_WORDS 8 words - */ - *AR9_DMA_PCTRL = 0x1f28; -} - -#ifdef CONFIG_EXTRA_SWITCH -static int external_switch_init(void) -{ - ar9_sw_chip_init(0, RGMII_MODE); - - ar9_dma_init(); - - return 0; -} -#endif /* CONFIG_EXTRA_SWITCH */ - -#if defined(CONFIG_CMD_HTTPD) -int do_http_upgrade(const unsigned char *data, const ulong size) -{ - char buf[128]; - - if(getenv ("ram_addr") == NULL) - return -1; - if(getenv ("kernel_addr") == NULL) - return -1; - /* check the image */ - if(run_command("imi ${ram_addr}", 0) < 0) { - return -1; - } - /* write the image to the flash */ - puts("http ugrade ...\n"); - sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size); - return run_command(buf, 0); -} - -int do_http_progress(const int state) -{ - /* toggle LED's here */ - switch(state) { - case HTTP_PROGRESS_START: - puts("http start\n"); - break; - case HTTP_PROGRESS_TIMEOUT: - puts("."); - break; - case HTTP_PROGRESS_UPLOAD_READY: - puts("http upload ready\n"); - break; - case HTTP_PROGRESS_UGRADE_READY: - puts("http ugrade ready\n"); - break; - case HTTP_PROGRESS_UGRADE_FAILED: - puts("http ugrade failed\n"); - break; - } - return 0; -} - -unsigned long do_http_tmp_address(void) -{ - char *s = getenv ("ram_addr"); - if (s) { - ulong tmp = simple_strtoul (s, NULL, 16); - return tmp; - } - return 0 /*0x80a00000*/; -} - -#endif diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h deleted file mode 100644 index 766f1e00da..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x139 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0x2200 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x514 -#define MC_DC29_VALUE 0x2d93 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h deleted file mode 100644 index 6d940ac6cb..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr166_settings.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x13f /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0x2200 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1600 -#define MC_DC22_VALUE 0x1616 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5d /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x514 -#define MC_DC29_VALUE 0x2d93 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h deleted file mode 100644 index 45daa188d3..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x80B -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xD02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xF -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x5FB -#define MC_DC29_VALUE 0x35DF -#define MC_DC30_VALUE 0x99E9 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h deleted file mode 100644 index 7f87d43f76..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x403 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x90c -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xf02 -#define MC_DC12_VALUE 0x2c8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x12f /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xc800 -#define MC_DC17_VALUE 0xf -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1500 -#define MC_DC22_VALUE 0x1515 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x57 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x6b8 -#define MC_DC29_VALUE 0x3c84 -#define MC_DC30_VALUE 0xace5 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h deleted file mode 100644 index 2e49db99d1..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr250_settings.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x403 -#define MC_DC8_VALUE 0x103 -#define MC_DC9_VALUE 0xb0e -#define MC_DC10_VALUE 0x204 -#define MC_DC11_VALUE 0x1102 -#define MC_DC12_VALUE 0x2c8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x155 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xc800 -#define MC_DC17_VALUE 0x13 -#define MC_DC18_VALUE 0x401 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0xc00 -#define MC_DC22_VALUE 0xc0c -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x74 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x798 -#define MC_DC29_VALUE 0x445d -#define MC_DC30_VALUE 0xc351 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/config.mk b/package/uboot-lantiq/files/board/infineon/easy50812/config.mk deleted file mode 100644 index b110f6f329..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Danube board with MIPS 24Kc CPU core -# -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifdef CONFIG_BOOTSTRAP -TEXT_BASE = 0x80001000 -CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000 -CONFIG_SYS_RAMBOOT = y -else - -ifndef TEXT_BASE -$(info redefine TEXT_BASE = 0xB0000000 ) -TEXT_BASE = 0xB0000000 -endif - -endif diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c b/package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c deleted file mode 100644 index 11bf6d0b71..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/easy50812_bootstrap.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2010 Industrie Dial Face S.p.A. - * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com - * - * (C) Copyright 2007 - * Vlad Lungu vlad.lungu@windriver.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/mipsregs.h> -#include <asm/io.h> - -phys_size_t bootstrap_initdram(int board_type) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - return CONFIG_SYS_MAX_RAM; -} - -int bootstrap_checkboard(void) -{ - return 0; -} - -int bootstrap_misc_init_r(void) -{ - set_io_port_base(0); - return 0; -} diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S b/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S deleted file mode 100644 index ec82e231c2..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S +++ /dev/null @@ -1,597 +0,0 @@ -/* - * Memory sub-system initialization code for Danube board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#if defined(CONFIG_USE_DDR_RAM) - -#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M) -# include "ar9_ddr111_settings.h" -#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M) -# include "ar9_ddr166_settings.h" -#elif defined(CONFIG_CPU_442M_RAM_147M) -# include "ar9_ddr166_settings.h" -#elif defined(CONFIG_CPU_393M_RAM_196M) -# ifdef CONFIG_ETRON_RAM -# include "etron_ddr196_settings.h" -# else -# include "ar9_ddr196_settings.h" -# endif -#elif defined(CONFIG_CPU_442M_RAM_221M) -# include "ar9_ddr221_settings.h" -#elif defined(CONFIG_CPU_500M_RAM_250M) -# include "ar9_ddr250_settings.h" -#else -# warning "missing definition for ddr_settings.h, use default!" -# include "ar9_ddr_settings.h" -#endif -#endif /* CONFIG_USE_DDR_RAM */ - -#define EBU_MODUL_BASE 0xBE105300 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(void) - */ - .globl ebu_init - .ent ebu_init -ebu_init: - -#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \ - defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \ - defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \ - defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3) - - li t1, EBU_MODUL_BASE -#if defined(CONFIG_EBU_ADDSEL0) - li t2, CONFIG_EBU_ADDSEL0 - sw t2, EBU_ADDSEL0(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL1) - li t2, CONFIG_EBU_ADDSEL1 - sw t2, EBU_ADDSEL1(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL2) - li t2, CONFIG_EBU_ADDSEL2 - sw t2, EBU_ADDSEL2(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL3) - li t2, CONFIG_EBU_ADDSEL3 - sw t2, EBU_ADDSEL3(t1) -#endif - -#if defined(CONFIG_EBU_BUSCON0) - li t2, CONFIG_EBU_BUSCON0 - sw t2, EBU_BUSCON0(t1) -#endif -#if defined(CONFIG_EBU_BUSCON1) - li t2, CONFIG_EBU_BUSCON1 - sw t2, EBU_BUSCON1(t1) -#endif -#if defined(CONFIG_EBU_BUSCON2) - li t2, CONFIG_EBU_BUSCON2 - sw t2, EBU_BUSCON2(t1) -#endif -#if defined(CONFIG_EBU_BUSCON3) - li t2, CONFIG_EBU_BUSCON3 - sw t2, EBU_BUSCON3(t1) -#endif - -#endif - - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - - .end cgu_init - -#ifndef CONFIG_USE_DDR_RAM -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - j ra - nop - - .end sdram_init - -#endif /* !CONFIG_USE_DDR_RAM */ - -#ifdef CONFIG_USE_DDR_RAM -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - .end ddrram_init -#endif /* CONFIG_USE_DDR_RAM */ - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that non of the following ..._init() functions - * modify t0 - */ -#if defined(DDR166) - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 -#elif defined(DDR133) - /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */ - li a0,0xe9 -#else /* defined(DDR111) */ - /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */ - li a0,0xea -#endif - bal cgu_init - nop - - bal ebu_init - nop - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef CONFIG_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S b/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S deleted file mode 100644 index 58f7a16eae..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_init.S +++ /dev/null @@ -1,543 +0,0 @@ -/* - * Memory sub-system initialization code for AR9 board. - * - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * Copyright (c) 2005 Andre Messerschmidt Infineon - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#if defined(CONFIG_USE_DDR_RAM) - -#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M) -# include "ar9_ddr111_settings.h" -#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M) -# include "ar9_ddr166_settings.h" -#elif defined(CONFIG_CPU_442M_RAM_147M) -# include "ar9_ddr166_settings.h" -#elif defined(CONFIG_CPU_393M_RAM_196M) -# ifdef CONFIG_ETRON_RAM -# include "etron_ddr196_settings.h" -# else -# include "ar9_ddr196_settings.h" -# endif -#elif defined(CONFIG_CPU_442M_RAM_221M) -# include "ar9_ddr221_settings.h" -#elif defined(CONFIG_CPU_500M_RAM_250M) -# include "ar9_ddr250_settings.h" -#else -# warning "missing definition for ddr_settings.h, use default!" -# include "ar9_ddr_settings.h" -#endif -#endif /* CONFIG_USE_DDR_RAM */ - -#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE) -#error "missing include of ddr_settings.h" -#endif - -#define EBU_MODUL_BASE 0xBE105300 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -#define pll1_36MHz_CONFIG 0x9800f25f - - .set noreorder - - -/* - * void ebu_init(void) - */ - .globl ebu_init - .ent ebu_init -ebu_init: - -#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \ - defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \ - defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \ - defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3) - - li t1, EBU_MODUL_BASE -#if defined(CONFIG_EBU_ADDSEL0) - li t2, CONFIG_EBU_ADDSEL0 - sw t2, EBU_ADDSEL0(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL1) - li t2, CONFIG_EBU_ADDSEL1 - sw t2, EBU_ADDSEL1(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL2) - li t2, CONFIG_EBU_ADDSEL2 - sw t2, EBU_ADDSEL2(t1) -#endif -#if defined(CONFIG_EBU_ADDSEL3) - li t2, CONFIG_EBU_ADDSEL3 - sw t2, EBU_ADDSEL3(t1) -#endif - -#if defined(CONFIG_EBU_BUSCON0) - li t2, CONFIG_EBU_BUSCON0 - sw t2, EBU_BUSCON0(t1) -#endif -#if defined(CONFIG_EBU_BUSCON1) - li t2, CONFIG_EBU_BUSCON1 - sw t2, EBU_BUSCON1(t1) -#endif -#if defined(CONFIG_EBU_BUSCON2) - li t2, CONFIG_EBU_BUSCON2 - sw t2, EBU_BUSCON2(t1) -#endif -#if defined(CONFIG_EBU_BUSCON3) - li t2, CONFIG_EBU_BUSCON3 - sw t2, EBU_BUSCON3(t1) -#endif - -#endif - - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - li t1, CGU_SYS - sw a0,0(t1) - -#if defined(CONFIG_CPU_333M_RAM_166M) && defined(CONFIG_USE_PLL1) - li t1, PLL1_CFG - li a1, pll1_36MHz_CONFIG - sw a1, 0(t1) -#endif - -#if defined(CONFIG_CLASS_II_DDR_PAD) - li t1, CGU_SMD - li a1, 0x200000 - sw a1, 0(t1) // Turn on DDR PAD Class II to INC drive. -#endif - - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop - -wait_reset: - b wait_reset - nop - -freq_up2date: - j ra - nop - .end cgu_init - - -#ifndef CONFIG_USE_DDR_RAM -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - j ra - nop - - .end sdram_init - -#endif /* !CONFIG_USE_DDR_RAM */ - -#ifdef CONFIG_USE_DDR_RAM -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - .end ddrram_init -#endif /* CONFIG_USE_DDR_RAM */ - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that non of the following ..._init() functions - * modify t0 - */ -#if defined(CONFIG_SYS_EBU_BOOT) -/* - using PPL1 value -*/ - li a0,0x90 - bal cgu_init - nop -#endif /* CONFIG_SYS_EBU_BOOT */ - - bal ebu_init - nop - -#ifdef CONFIG_SYS_EBU_BOOT -#ifndef CONFIG_SYS_RAMBOOT -#ifdef CONFIG_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif -#endif /* CONFIG_SYS_RAMBOOT */ -#endif /* CONFIG_SYS_EBU_BOOT */ - - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S b/package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S deleted file mode 100644 index e0d7971d89..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/pmuenable.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power Management unit initialization code for AMAZON development board. - * - * Copyright (c) 2003 Ou Ke, Infineon. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#define PMU_PWDCR 0xBF10201C -#define PMU_SR 0xBF102020 - - .globl pmuenable - -pmuenable: - li t0, PMU_PWDCR - li t1, 0x2 /* enable everything */ - sw t1, 0(t0) -#if 0 -1: - li t0, PMU_SR - lw t2, 0(t0) - bne t1, t2, 1b - nop -#endif - j ra - nop - - diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds b/package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds deleted file mode 100644 index 52d7dafadb..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot-bootstrap.lds +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2010 Industrie Dial Face S.p.A. - * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com - * - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = .; - _gp = ALIGN(16) +0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - . = .; - . = ALIGN(4); - .payload : { *(.payload) } - . = ALIGN(4); - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) . = ALIGN(4); } - uboot_end = .; -} - diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds b/package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds deleted file mode 100644 index 9a6cd1b8a3..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - .sdata : { *(.sdata) } - - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - uboot_end = .; -} diff --git a/package/uboot-lantiq/files/cpu/mips/ar9-clock.c b/package/uboot-lantiq/files/cpu/mips/ar9-clock.c deleted file mode 100644 index a8aecb4225..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/ar9-clock.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/ar9.h> - -ulong ifx_get_ddr_hz(void) -{ - switch((*AR9_CGU_SYS) & 0x05) { - case 0x01: - case 0x05: - return CLOCK_111M; - - case 0x00: - case 0x04: - return CLOCK_166M; - } - - return 0; -} - -ulong ifx_get_cpuclk(void) -{ - switch((*AR9_CGU_SYS) & 0x05) { - case 0x00: - case 0x01: - return CLOCK_333M; - - case 0x04: - return CLOCK_166M; - - case 0x05: - return CLOCK_111M; - } - - return 0; -} - -ulong get_bus_freq(ulong dummy) -{ - unsigned int ddr_clock=ifx_get_ddr_hz(); - if((*AR9_CGU_SYS) & 0x40){ - return ddr_clock/2; - } else { - return ddr_clock; - } -} diff --git a/package/uboot-lantiq/files/cpu/mips/ar9/Makefile b/package/uboot-lantiq/files/cpu/mips/ar9/Makefile deleted file mode 100644 index c48d02eaaa..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/ar9/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -######################################################################### -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = clock.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-lantiq/files/cpu/mips/ar9/clock.c b/package/uboot-lantiq/files/cpu/mips/ar9/clock.c deleted file mode 100644 index a8aecb4225..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/ar9/clock.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/ar9.h> - -ulong ifx_get_ddr_hz(void) -{ - switch((*AR9_CGU_SYS) & 0x05) { - case 0x01: - case 0x05: - return CLOCK_111M; - - case 0x00: - case 0x04: - return CLOCK_166M; - } - - return 0; -} - -ulong ifx_get_cpuclk(void) -{ - switch((*AR9_CGU_SYS) & 0x05) { - case 0x00: - case 0x01: - return CLOCK_333M; - - case 0x04: - return CLOCK_166M; - - case 0x05: - return CLOCK_111M; - } - - return 0; -} - -ulong get_bus_freq(ulong dummy) -{ - unsigned int ddr_clock=ifx_get_ddr_hz(); - if((*AR9_CGU_SYS) & 0x40){ - return ddr_clock/2; - } else { - return ddr_clock; - } -} diff --git a/package/uboot-lantiq/files/cpu/mips/ar9/ifx_cache.S b/package/uboot-lantiq/files/cpu/mips/ar9/ifx_cache.S deleted file mode 100644 index fc482dcd61..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/ar9/ifx_cache.S +++ /dev/null @@ -1,60 +0,0 @@ - -#define IFX_CACHE_EXTRA_INVALID_TAG \ - mtc0 zero, CP0_TAGLO, 1; \ - mtc0 zero, CP0_TAGLO, 2; \ - mtc0 zero, CP0_TAGLO, 3; \ - mtc0 zero, CP0_TAGLO, 4; - -#define IFX_CACHE_EXTRA_OPERATION \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t2; /* icacheSize */ \ - move a3, t4; /* icacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - /* 1: initialise dcache tags. */ \ - \ - /* cache line size */ \ - li a2, CFG_CACHELINE_SIZE; \ - /* kseg0 mem address */ \ - li a1, 0; \ - li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \ -1: \ - /* store tag (invalid, not locked) */ \ - cache 0x8, 0(a1); \ - cache 0x9, 0(a1); \ - \ - add a3, -1; \ - bne a3, zero, 1b; \ - add a1, a2; \ - \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t3; /* dcacheSize */ \ - move a3, t5; /* dcacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; - diff --git a/package/uboot-lantiq/files/cpu/mips/danube-clock.c b/package/uboot-lantiq/files/cpu/mips/danube-clock.c deleted file mode 100644 index 4219f8f921..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/danube-clock.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/danube.h> - -ulong ifx_get_ddr_hz(void) -{ - static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333}; - return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)]; -} - -ulong ifx_get_cpuclk(void) -{ -#ifdef CONFIG_USE_EMULATOR - return EMULATOR_CPU_SPEED; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=ifx_get_ddr_hz(); - switch((*DANUBE_CGU_SYS) & 0xc){ - case 0: - default: - return 323333333; - case 4: - return ddr_clock; - case 8: - return ddr_clock << 1; - } -#endif -} - -ulong get_bus_freq(ulong dummy) -{ -#ifdef CONFIG_USE_EMULATOR - unsigned int clkCPU; - clkCPU = ifx_get_cpuclk(); - return clkCPU >> 2; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=ifx_get_ddr_hz(); - if ((*DANUBE_CGU_SYS) & 0x40){ - return ddr_clock >> 1; - } - return ddr_clock; -#endif -} - diff --git a/package/uboot-lantiq/files/cpu/mips/danube/Makefile b/package/uboot-lantiq/files/cpu/mips/danube/Makefile deleted file mode 100644 index c48d02eaaa..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/danube/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -######################################################################### -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = clock.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-lantiq/files/cpu/mips/danube/clock.c b/package/uboot-lantiq/files/cpu/mips/danube/clock.c deleted file mode 100644 index 4219f8f921..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/danube/clock.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/danube.h> - -ulong ifx_get_ddr_hz(void) -{ - static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333}; - return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)]; -} - -ulong ifx_get_cpuclk(void) -{ -#ifdef CONFIG_USE_EMULATOR - return EMULATOR_CPU_SPEED; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=ifx_get_ddr_hz(); - switch((*DANUBE_CGU_SYS) & 0xc){ - case 0: - default: - return 323333333; - case 4: - return ddr_clock; - case 8: - return ddr_clock << 1; - } -#endif -} - -ulong get_bus_freq(ulong dummy) -{ -#ifdef CONFIG_USE_EMULATOR - unsigned int clkCPU; - clkCPU = ifx_get_cpuclk(); - return clkCPU >> 2; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=ifx_get_ddr_hz(); - if ((*DANUBE_CGU_SYS) & 0x40){ - return ddr_clock >> 1; - } - return ddr_clock; -#endif -} - diff --git a/package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S b/package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S deleted file mode 100644 index fc482dcd61..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S +++ /dev/null @@ -1,60 +0,0 @@ - -#define IFX_CACHE_EXTRA_INVALID_TAG \ - mtc0 zero, CP0_TAGLO, 1; \ - mtc0 zero, CP0_TAGLO, 2; \ - mtc0 zero, CP0_TAGLO, 3; \ - mtc0 zero, CP0_TAGLO, 4; - -#define IFX_CACHE_EXTRA_OPERATION \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t2; /* icacheSize */ \ - move a3, t4; /* icacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - /* 1: initialise dcache tags. */ \ - \ - /* cache line size */ \ - li a2, CFG_CACHELINE_SIZE; \ - /* kseg0 mem address */ \ - li a1, 0; \ - li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \ -1: \ - /* store tag (invalid, not locked) */ \ - cache 0x8, 0(a1); \ - cache 0x9, 0(a1); \ - \ - add a3, -1; \ - bne a3, zero, 1b; \ - add a1, a2; \ - \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t3; /* dcacheSize */ \ - move a3, t5; /* dcacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; - diff --git a/package/uboot-lantiq/files/cpu/mips/ifx_asc.c b/package/uboot-lantiq/files/cpu/mips/ifx_asc.c deleted file mode 100644 index 5c13f26622..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/ifx_asc.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2009 - * Infineon Technologies AG, http://www.infineon.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <asm/addrspace.h> - -#include "ifx_asc.h" - -#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask)) -#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask)) -#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) ) - -#undef DEBUG_ASC_RAW -#ifdef DEBUG_ASC_RAW -#define DEBUG_ASC_RAW_RX_BUF 0xA0800000 -#define DEBUG_ASC_RAW_TX_BUF 0xA0900000 -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE); - -/* - * FDV fASC - * BaudRate = ----- * -------------------- - * 512 16 * (ReloadValue+1) - */ - -/* - * FDV fASC - * ReloadValue = ( ----- * --------------- ) - 1 - * 512 16 * BaudRate - */ -static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload) -{ - u32 clock = fasc / 16; - - u32 fdv; /* best fdv */ - u32 reload = 0; /* best reload */ - u32 diff; /* smallest diff */ - u32 idiff; /* current diff */ - u32 ireload; /* current reload */ - u32 i; /* current fdv */ - u32 result; /* current resulting baudrate */ - - if (clock > 0x7FFFFF) - clock /= 512; - else - baudrate *= 512; - - fdv = 512; /* start with 1:1 fraction */ - diff = baudrate; /* highest possible */ - - /* i is the test fdv value -- start with the largest possible */ - for (i = 512; i > 0; i--) - { - ireload = (clock * i) / baudrate; - if (ireload < 1) - break; /* already invalid */ - result = (clock * i) / ireload; - - idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result); - if (idiff == 0) - { - fdv = i; - reload = ireload; - break; /* can't do better */ - } - else if (idiff < diff) - { - fdv = i; /* best so far */ - reload = ireload; - diff = idiff; /* update lowest diff*/ - } - } - - *pfdv = (fdv == 512) ? 0 : fdv; - *preload = reload - 1; -} - - -void serial_setbrg (void) -{ - u32 ReloadValue, fdv; - - serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue); - - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(asc_con, ASCCON_R); - - /* Enable Fractional Divider */ - SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK); - - /* Set reload value in BG */ - asc_writel(asc_bg, ReloadValue); - - /* Enable Baud Rate Generator */ - SET_BIT(asc_con, ASCCON_R); /* R = 1 */ -} - - -int serial_init (void) -{ - - /* and we have to set CLC register*/ - CLEAR_BIT(asc_clc, ASCCLC_DISS); - SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - asc_writel(asc_con, ASCCON_M_8ASYNC); - - /* select input port */ - asc_writel(asc_pisel, CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN); - - /* set baud rate */ - serial_setbrg(); - - /* enable error signals & Receiver enable */ - SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN); - - return 0; -} - - -void serial_putc (const char c) -{ - u32 txFl = 0; -#ifdef DEBUG_ASC_RAW - static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF; - *debug++=c; -#endif - if (c == '\n') - serial_putc ('\r'); - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do { - txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == ASC_TXFIFO_FULL ); - - asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( asc_readl(asc_state) & ASCSTATE_TOE ) { - SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE); - return; - } -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - char c; - while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ); - c = (char)(asc_readl(asc_rbuf) & 0xff); - -#ifdef DEBUG_ASC_RAW - static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF); - *debug++=c; -#endif - return c; -} - - -int serial_tstc (void) -{ - int res = 1; - - if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) { - res = 0; - } - return res; -} diff --git a/package/uboot-lantiq/files/cpu/mips/ifx_asc.h b/package/uboot-lantiq/files/cpu/mips/ifx_asc.h deleted file mode 100644 index 2d3a49e1e5..0000000000 --- a/package/uboot-lantiq/files/cpu/mips/ifx_asc.h +++ /dev/null @@ -1,199 +0,0 @@ -/***************************************************************************** - * DANUBE BootROM - * Copyright (c) 2005, Infineon Technologies AG, All rights reserved - * IFAP DC COM SD - *****************************************************************************/ -#ifndef __ASC_H -#define __ASC_H - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -#define ASC_TXFIFO_FL 1 -#define ASC_RXFIFO_FL 1 -#define ASC_TXFIFO_FULL 16 - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0000000f -#define ASCCON_M_8ASYNC 0x0 -#define ASCCON_M_8IRDA 0x1 -#define ASCCON_M_7ASYNC 0x2 -#define ASCCON_M_7IRDA 0x3 -#define ASCCON_WLSMASK 0x0000000c -#define ASCCON_WLSOFFSET 2 -#define ASCCON_WLS_8BIT 0x0 -#define ASCCON_WLS_7BIT 0x1 -#define ASCCON_PEN 0x00000010 -#define ASCCON_ODD 0x00000020 -#define ASCCON_SP 0x00000040 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_ERRCLK 0x00000400 -#define ASCCON_EMMASK 0x00001800 -#define ASCCON_EMOFFSET 11 -#define ASCCON_EM_ECHO_OFF 0x0 -#define ASCCON_EM_ECHO_AB 0x1 -#define ASCCON_EM_ECHO_ON 0x2 -#define ASCCON_LB 0x00002000 -#define ASCCON_ACO 0x00004000 -#define ASCCON_R 0x00008000 -#define ASCCON_PAL 0x00010000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_RUEN 0x00040000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCCON_BEN 0x00200000 -#define ASCCON_TXINV 0x01000000 -#define ASCCON_RXINV 0x02000000 -#define ASCCON_TXMSB 0x04000000 -#define ASCCON_RXMSB 0x08000000 - -/* STATE register's bits and bitfields */ -#define ASCSTATE_REN 0x00000001 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 -#define ASCSTATE_RUE 0x00040000 -#define ASCSTATE_ROE 0x00080000 -#define ASCSTATE_TOE 0x00100000 -#define ASCSTATE_BE 0x00200000 -#define ASCSTATE_TXBVMASK 0x07000000 -#define ASCSTATE_TXBVOFFSET 24 -#define ASCSTATE_TXEOM 0x08000000 -#define ASCSTATE_RXBVMASK 0x70000000 -#define ASCSTATE_RXBVOFFSET 28 -#define ASCSTATE_RXEOM 0x80000000 - -/* WHBSTATE register's bits and bitfields */ -#define ASCWHBSTATE_CLRREN 0x00000001 -#define ASCWHBSTATE_SETREN 0x00000002 -#define ASCWHBSTATE_CLRPE 0x00000004 -#define ASCWHBSTATE_CLRFE 0x00000008 -#define ASCWHBSTATE_CLRRUE 0x00000010 -#define ASCWHBSTATE_CLRROE 0x00000020 -#define ASCWHBSTATE_CLRTOE 0x00000040 -#define ASCWHBSTATE_CLRBE 0x00000080 -#define ASCWHBSTATE_SETPE 0x00000100 -#define ASCWHBSTATE_SETFE 0x00000200 -#define ASCWHBSTATE_SETRUE 0x00000400 -#define ASCWHBSTATE_SETROE 0x00000800 -#define ASCWHBSTATE_SETTOE 0x00001000 -#define ASCWHBSTATE_SETBE 0x00002000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_CLRABEN 0x0001 -#define ASCWHBABCON_SETABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_CLRSCCDET 0x0040 -#define ASCWHBABSTAT_SETSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFIFO1 0x00000400 -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFIFO1 0x00000400 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -typedef struct IfxAsc_s -{ - unsigned long asc_clc; /*0x0000*/ - unsigned long asc_pisel; /*0x0004*/ - unsigned long asc_id; /*0x0008*/ - unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/ - unsigned long asc_con; /*0x0010*/ - unsigned long asc_state; /*0x0014*/ - unsigned long asc_whbstate; /*0x0018*/ - unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/ - unsigned long asc_tbuf; /*0x0020*/ - unsigned long asc_rbuf; /*0x0024*/ - unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/ - unsigned long asc_abcon; /*0x0030*/ - unsigned long asc_abstat; /* not used */ /*0x0034*/ - unsigned long asc_whbabcon; /*0x0038*/ - unsigned long asc_whbabstat; /* not used */ /*0x003C*/ - unsigned long asc_rxfcon; /*0x0040*/ - unsigned long asc_txfcon; /*0x0044*/ - unsigned long asc_fstat; /*0x0048*/ - unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/ - unsigned long asc_bg; /*0x0050*/ - unsigned long asc_bg_timer; /*0x0054*/ - unsigned long asc_fdv; /*0x0058*/ - unsigned long asc_pmw; /*0x005C*/ - unsigned long asc_modcon; /*0x0060*/ - unsigned long asc_modstat; /*0x0064*/ - unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/ - unsigned long asc_sfcc; /*0x0070*/ - unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/ - unsigned long asc_eomcon; /*0x0080*/ - unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/ - unsigned long asc_dmacon; /*0x00EC*/ - unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/ - unsigned long asc_irnen; /*0x00F4*/ - unsigned long asc_irnicr; /*0x00F8*/ - unsigned long asc_irncr; /*0x00FC*/ -} IfxAsc_t; - - -/* Register access macros */ -#define asc_readl(reg) \ - readl(&pAsc->reg) -#define asc_writel(reg,value) \ - writel((value), &pAsc->reg) - - -#endif /* __ASC_H */ diff --git a/package/uboot-lantiq/files/drivers/net/ifx_etop.c b/package/uboot-lantiq/files/drivers/net/ifx_etop.c deleted file mode 100644 index 8a03683c0c..0000000000 --- a/package/uboot-lantiq/files/drivers/net/ifx_etop.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Lantiq CPE device ethernet driver. - * Supposed to work on Twinpass/Danube. - * - * Based on INCA-IP driver: - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2010 - * Thomas Langer, Ralph Hempel - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#include <malloc.h> -#include <net.h> -#include <miiphy.h> -#include <asm/types.h> -#include <asm/io.h> -#include <asm/addrspace.h> -#include <config.h> - -#include "ifx_etop.h" - -#if defined(CONFIG_AR9) -#define TX_CHAN_NO 1 -#define RX_CHAN_NO 0 -#else -#define TX_CHAN_NO 7 -#define RX_CHAN_NO 6 -#endif - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 8 -#define TOUT_LOOP 100 - -typedef struct -{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved :3; - volatile u32 Byteoffset :2; - volatile u32 reserve :7; - volatile u32 DataLen :16; - }field; - - volatile u32 word; - }status; - - volatile u32 DataPtr; -} dma_rx_descriptor_t; - -typedef struct -{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 Byteoffset :5; - volatile u32 reserved :7; - volatile u32 DataLen :16; - }field; - - volatile u32 word; - }status; - - volatile u32 DataPtr; -} dma_tx_descriptor_t; - -static volatile dma_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8))); -static volatile dma_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8))); -static int tx_num, rx_num; - -static volatile IfxDMA_t *pDma = (IfxDMA_t *)CKSEG1ADDR(DANUBE_DMA_BASE); - -static int lq_eth_init(struct eth_device *dev, bd_t * bis); -static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length); -static int lq_eth_recv(struct eth_device *dev); -static void lq_eth_halt(struct eth_device *dev); -static void lq_eth_init_chip(void); -static void lq_eth_init_dma(void); - -static int lq_eth_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal) -{ - u32 timeout = 50000; - u32 phy, reg; - - if ((phyAddr > 0x1F) || (regAddr > 0x1F) || (retVal == NULL)) - return -1; - - phy = (phyAddr & 0x1F) << 21; - reg = (regAddr & 0x1F) << 16; - - *ETOP_MDIO_ACC = 0xC0000000 | phy | reg; - while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000)) - udelay(10); - - if (timeout==0) { - *retVal = 0; - return -1; - } - *retVal = *ETOP_MDIO_ACC & 0xFFFF; - return 0; -} - -static int lq_eth_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data) -{ - u32 timeout = 50000; - u32 phy, reg; - - if ((phyAddr > 0x1F) || (regAddr > 0x1F)) - return -1; - - phy = (phyAddr & 0x1F) << 21; - reg = (regAddr & 0x1F) << 16; - - *ETOP_MDIO_ACC = 0x80000000 | phy | reg | data; - while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000)) - udelay(10); - - if (timeout==0) - return -1; - return 0; -} - - -int lq_eth_initialize(bd_t * bis) -{ - struct eth_device *dev; - - debug("Entered lq_eth_initialize()\n"); - - if (!(dev = malloc (sizeof *dev))) { - printf("Failed to allocate memory\n"); - return -1; - } - memset(dev, 0, sizeof(*dev)); - - sprintf(dev->name, "lq_cpe_eth"); - dev->init = lq_eth_init; - dev->halt = lq_eth_halt; - dev->send = lq_eth_send; - dev->recv = lq_eth_recv; - - eth_register(dev); - -#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) - /* register mii command access routines */ - miiphy_register(dev->name, - lq_eth_miiphy_read, lq_eth_miiphy_write); -#endif - - lq_eth_init_dma(); - lq_eth_init_chip(); - - return 0; -} - -static int lq_eth_init(struct eth_device *dev, bd_t * bis) -{ - int i; - uchar *enetaddr = dev->enetaddr; - - debug("lq_eth_init %x:%x:%x:%x:%x:%x\n", - enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]); - - *ENET_MAC_DA0 = (enetaddr[0]<<24) + (enetaddr[1]<<16) + (enetaddr[2]<< 8) + enetaddr[3]; - *ENET_MAC_DA1 = (enetaddr[4]<<24) + (enetaddr[5]<<16); - *ENETS_CFG |= 1<<28; /* enable filter for unicast packets */ - - tx_num=0; - rx_num=0; - - for(i=0;i < NUM_RX_DESC; i++) { - dma_rx_descriptor_t * rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[i]); - rx_desc->status.word=0; - rx_desc->status.field.OWN=1; - rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */ - rx_desc->DataPtr=(u32)CKSEG1ADDR(NetRxPackets[i]); - NetRxPackets[i][0] = 0xAA; - } - - /* Reset DMA */ - dma_writel(dma_cs, RX_CHAN_NO); - dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/ - dma_writel(dma_cpoll, 0x80000040); - /*set descriptor base*/ - dma_writel(dma_cdba, (u32)rx_des_ring); - dma_writel(dma_cdlen, NUM_RX_DESC); - dma_writel(dma_cie, 0); - dma_writel(dma_cctrl, 0x30000); - - for(i=0;i < NUM_TX_DESC; i++) { - dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[i]); - memset(tx_desc, 0, sizeof(tx_des_ring[0])); - } - - dma_writel(dma_cs, TX_CHAN_NO); - dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/ - dma_writel(dma_cpoll, 0x80000040); - dma_writel(dma_cdba, (u32)tx_des_ring); - dma_writel(dma_cdlen, NUM_TX_DESC); - dma_writel(dma_cie, 0); - dma_writel(dma_cctrl, 0x30100); - - /* turn on DMA rx & tx channel - */ - dma_writel(dma_cs, RX_CHAN_NO); - dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); /*reset and turn on the channel*/ - - return 0; -} - -static void lq_eth_halt(struct eth_device *dev) -{ - int i; - - debug("lq_eth_halt()\n"); - - for(i=0;i<8;i++) { - dma_writel(dma_cs, i); - dma_writel(dma_cctrl, dma_readl(dma_cctrl) & ~1);/*stop the dma channel*/ - } -} - -#ifdef DEBUG -static void lq_dump(const u8 *data, const u32 length) -{ - u32 i; - debug("\n"); - for(i=0;i<length;i++) { - debug("%02x ", data[i]); - } - debug("\n"); -} -#endif - -static int lq_eth_send(struct eth_device *dev, volatile void *packet, int length) -{ - int i; - int res = -1; - volatile dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[tx_num]); - - if (length <= 0) { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - for(i=0; tx_desc->status.field.OWN==1; i++) { - if (i>=TOUT_LOOP) { - printf("NO Tx Descriptor..."); - goto Done; - } - } - - tx_desc->status.field.Sop=1; - tx_desc->status.field.Eop=1; - tx_desc->status.field.C=0; - tx_desc->DataPtr = (u32)CKSEG1ADDR(packet); - if (length<60) - tx_desc->status.field.DataLen = 60; - else - tx_desc->status.field.DataLen = (u32)length; - - flush_cache((u32)packet, tx_desc->status.field.DataLen); - asm("SYNC"); - tx_desc->status.field.OWN=1; - - res=length; - tx_num++; - if (tx_num==NUM_TX_DESC) tx_num=0; - -#ifdef DEBUG - lq_dump(tx_desc->DataPtr, tx_desc->status.field.DataLen); -#endif - - dma_writel(dma_cs, TX_CHAN_NO); - if (!(dma_readl(dma_cctrl) & 1)) { - dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); - } - -Done: - return res; -} - -static int lq_eth_recv(struct eth_device *dev) -{ - int length = 0; - volatile dma_rx_descriptor_t * rx_desc; - - rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[rx_num]); - - if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) { - return 0; - } - debug("rx"); -#ifdef DEBUG - lq_dump(rx_desc->DataPtr, rx_desc->status.field.DataLen); -#endif - length = rx_desc->status.field.DataLen; - if (length > 4) { - invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length); - NetReceive(NetRxPackets[rx_num], length); - } else { - printf("ERROR: Invalid rx packet length.\n"); - } - - rx_desc->status.field.Sop=0; - rx_desc->status.field.Eop=0; - rx_desc->status.field.C=0; - rx_desc->status.field.DataLen=PKTSIZE_ALIGN; - rx_desc->status.field.OWN=1; - - rx_num++; - if (rx_num == NUM_RX_DESC) - rx_num=0; - - return length; -} - -static void lq_eth_init_chip(void) -{ - *ETOP_MDIO_CFG &= ~0x6; - *ENET_MAC_CFG = 0x187; - - // turn on port0, set to rmii and turn off port1. -#ifdef CONFIG_RMII - *ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A; -#else - *ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008; -#endif - - *ETOP_IG_PLEN_CTRL = 0x004005EE; // set packetlen. - *ENET_MAC_CFG |= 1<<11; /*enable the crc*/ - return; -} - -static void lq_eth_init_dma(void) -{ - /* Reset DMA */ - dma_writel(dma_ctrl, dma_readl(dma_ctrl) | 1); - dma_writel(dma_irnen, 0);/*disable all the interrupts first*/ - - /* Clear Interrupt Status Register */ - dma_writel(dma_irncr, 0xfffff); - /*disable all the dma interrupts*/ - dma_writel(dma_irnen, 0); - /*disable channel 0 and channel 1 interrupts*/ - - dma_writel(dma_cs, RX_CHAN_NO); - dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/ - dma_writel(dma_cpoll, 0x80000040); - /*set descriptor base*/ - dma_writel(dma_cdba, (u32)rx_des_ring); - dma_writel(dma_cdlen, NUM_RX_DESC); - dma_writel(dma_cie, 0); - dma_writel(dma_cctrl, 0x30000); - - dma_writel(dma_cs, TX_CHAN_NO); - dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/ - dma_writel(dma_cpoll, 0x80000040); - dma_writel(dma_cdba, (u32)tx_des_ring); - dma_writel(dma_cdlen, NUM_TX_DESC); - dma_writel(dma_cie, 0); - dma_writel(dma_cctrl, 0x30100); - /*enable the poll function and set the poll counter*/ - //dma_writel(DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4); - /*set port properties, enable endian conversion for switch*/ - dma_writel(dma_ps, 0); - dma_writel(dma_pctrl, dma_readl(dma_pctrl) | (0xf<<8));/*enable 32 bit endian conversion*/ - - return; -} diff --git a/package/uboot-lantiq/files/drivers/net/ifx_etop.h b/package/uboot-lantiq/files/drivers/net/ifx_etop.h deleted file mode 100644 index 99708684e5..0000000000 --- a/package/uboot-lantiq/files/drivers/net/ifx_etop.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Lantiq switch ethernet driver for Danube family. - * - * Based on INCA-IP driver: - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __DRIVERS_IFX_SW_H__ -#define __DRIVERS_IFX_SW_H__ - -#define DANUBE_PPE32_BASE 0xBE180000 -#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) - -#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) - - - -#define DANUBE_DMA_BASE 0xBE104100 - -typedef struct IfxDMA_s -{ - unsigned long dma_clc; /*0x0000*/ - unsigned long dma_rsvd1[1]; /* for mapping */ /*0x0004*/ - unsigned long dma_id; /*0x0008*/ - unsigned long dma_rsvd2[1]; /* for mapping */ /*0x000C*/ - unsigned long dma_ctrl; /*0x0010*/ - unsigned long dma_cpoll; /*0x0014*/ - unsigned long dma_cs; /*0x0018*/ - unsigned long dma_cctrl; /*0x001C*/ - unsigned long dma_cdba; /*0x0020*/ - unsigned long dma_cdlen; /*0x0024*/ - unsigned long dma_cis; /*0x0028*/ - unsigned long dma_cie; /*0x002C*/ - unsigned long dma_rsvd3[4]; /* for mapping */ /*0x0030*/ - unsigned long dma_ps; /*0x0040*/ - unsigned long dma_pctrl; /*0x0044*/ - unsigned long dma_rsvd4[43]; /* for mapping */ /*0x0048*/ - unsigned long dma_irnen; /*0x00F4*/ - unsigned long dma_irncr; /*0x00F8*/ - unsigned long dma_irnicr; /*0x00FC*/ -} IfxDMA_t; - -/* Register access macros */ -#define dma_readl(reg) \ - readl(&pDma->reg) -#define dma_writel(reg,value) \ - writel((value), &pDma->reg) - -int lq_eth_initialize(bd_t * bis); - -#endif /* __DRIVERS_IFX_SW_H__ */ diff --git a/package/uboot-lantiq/files/drivers/serial/ifx_asc.c b/package/uboot-lantiq/files/drivers/serial/ifx_asc.c deleted file mode 100644 index 5c13f26622..0000000000 --- a/package/uboot-lantiq/files/drivers/serial/ifx_asc.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2009 - * Infineon Technologies AG, http://www.infineon.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <asm/addrspace.h> - -#include "ifx_asc.h" - -#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask)) -#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask)) -#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) ) - -#undef DEBUG_ASC_RAW -#ifdef DEBUG_ASC_RAW -#define DEBUG_ASC_RAW_RX_BUF 0xA0800000 -#define DEBUG_ASC_RAW_TX_BUF 0xA0900000 -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE); - -/* - * FDV fASC - * BaudRate = ----- * -------------------- - * 512 16 * (ReloadValue+1) - */ - -/* - * FDV fASC - * ReloadValue = ( ----- * --------------- ) - 1 - * 512 16 * BaudRate - */ -static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload) -{ - u32 clock = fasc / 16; - - u32 fdv; /* best fdv */ - u32 reload = 0; /* best reload */ - u32 diff; /* smallest diff */ - u32 idiff; /* current diff */ - u32 ireload; /* current reload */ - u32 i; /* current fdv */ - u32 result; /* current resulting baudrate */ - - if (clock > 0x7FFFFF) - clock /= 512; - else - baudrate *= 512; - - fdv = 512; /* start with 1:1 fraction */ - diff = baudrate; /* highest possible */ - - /* i is the test fdv value -- start with the largest possible */ - for (i = 512; i > 0; i--) - { - ireload = (clock * i) / baudrate; - if (ireload < 1) - break; /* already invalid */ - result = (clock * i) / ireload; - - idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result); - if (idiff == 0) - { - fdv = i; - reload = ireload; - break; /* can't do better */ - } - else if (idiff < diff) - { - fdv = i; /* best so far */ - reload = ireload; - diff = idiff; /* update lowest diff*/ - } - } - - *pfdv = (fdv == 512) ? 0 : fdv; - *preload = reload - 1; -} - - -void serial_setbrg (void) -{ - u32 ReloadValue, fdv; - - serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue); - - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(asc_con, ASCCON_R); - - /* Enable Fractional Divider */ - SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK); - - /* Set reload value in BG */ - asc_writel(asc_bg, ReloadValue); - - /* Enable Baud Rate Generator */ - SET_BIT(asc_con, ASCCON_R); /* R = 1 */ -} - - -int serial_init (void) -{ - - /* and we have to set CLC register*/ - CLEAR_BIT(asc_clc, ASCCLC_DISS); - SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - asc_writel(asc_con, ASCCON_M_8ASYNC); - - /* select input port */ - asc_writel(asc_pisel, CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN); - - /* set baud rate */ - serial_setbrg(); - - /* enable error signals & Receiver enable */ - SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN); - - return 0; -} - - -void serial_putc (const char c) -{ - u32 txFl = 0; -#ifdef DEBUG_ASC_RAW - static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF; - *debug++=c; -#endif - if (c == '\n') - serial_putc ('\r'); - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do { - txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == ASC_TXFIFO_FULL ); - - asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( asc_readl(asc_state) & ASCSTATE_TOE ) { - SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE); - return; - } -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - char c; - while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ); - c = (char)(asc_readl(asc_rbuf) & 0xff); - -#ifdef DEBUG_ASC_RAW - static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF); - *debug++=c; -#endif - return c; -} - - -int serial_tstc (void) -{ - int res = 1; - - if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) { - res = 0; - } - return res; -} diff --git a/package/uboot-lantiq/files/drivers/serial/ifx_asc.h b/package/uboot-lantiq/files/drivers/serial/ifx_asc.h deleted file mode 100644 index 2d3a49e1e5..0000000000 --- a/package/uboot-lantiq/files/drivers/serial/ifx_asc.h +++ /dev/null @@ -1,199 +0,0 @@ -/***************************************************************************** - * DANUBE BootROM - * Copyright (c) 2005, Infineon Technologies AG, All rights reserved - * IFAP DC COM SD - *****************************************************************************/ -#ifndef __ASC_H -#define __ASC_H - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -#define ASC_TXFIFO_FL 1 -#define ASC_RXFIFO_FL 1 -#define ASC_TXFIFO_FULL 16 - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0000000f -#define ASCCON_M_8ASYNC 0x0 -#define ASCCON_M_8IRDA 0x1 -#define ASCCON_M_7ASYNC 0x2 -#define ASCCON_M_7IRDA 0x3 -#define ASCCON_WLSMASK 0x0000000c -#define ASCCON_WLSOFFSET 2 -#define ASCCON_WLS_8BIT 0x0 -#define ASCCON_WLS_7BIT 0x1 -#define ASCCON_PEN 0x00000010 -#define ASCCON_ODD 0x00000020 -#define ASCCON_SP 0x00000040 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_ERRCLK 0x00000400 -#define ASCCON_EMMASK 0x00001800 -#define ASCCON_EMOFFSET 11 -#define ASCCON_EM_ECHO_OFF 0x0 -#define ASCCON_EM_ECHO_AB 0x1 -#define ASCCON_EM_ECHO_ON 0x2 -#define ASCCON_LB 0x00002000 -#define ASCCON_ACO 0x00004000 -#define ASCCON_R 0x00008000 -#define ASCCON_PAL 0x00010000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_RUEN 0x00040000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCCON_BEN 0x00200000 -#define ASCCON_TXINV 0x01000000 -#define ASCCON_RXINV 0x02000000 -#define ASCCON_TXMSB 0x04000000 -#define ASCCON_RXMSB 0x08000000 - -/* STATE register's bits and bitfields */ -#define ASCSTATE_REN 0x00000001 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 -#define ASCSTATE_RUE 0x00040000 -#define ASCSTATE_ROE 0x00080000 -#define ASCSTATE_TOE 0x00100000 -#define ASCSTATE_BE 0x00200000 -#define ASCSTATE_TXBVMASK 0x07000000 -#define ASCSTATE_TXBVOFFSET 24 -#define ASCSTATE_TXEOM 0x08000000 -#define ASCSTATE_RXBVMASK 0x70000000 -#define ASCSTATE_RXBVOFFSET 28 -#define ASCSTATE_RXEOM 0x80000000 - -/* WHBSTATE register's bits and bitfields */ -#define ASCWHBSTATE_CLRREN 0x00000001 -#define ASCWHBSTATE_SETREN 0x00000002 -#define ASCWHBSTATE_CLRPE 0x00000004 -#define ASCWHBSTATE_CLRFE 0x00000008 -#define ASCWHBSTATE_CLRRUE 0x00000010 -#define ASCWHBSTATE_CLRROE 0x00000020 -#define ASCWHBSTATE_CLRTOE 0x00000040 -#define ASCWHBSTATE_CLRBE 0x00000080 -#define ASCWHBSTATE_SETPE 0x00000100 -#define ASCWHBSTATE_SETFE 0x00000200 -#define ASCWHBSTATE_SETRUE 0x00000400 -#define ASCWHBSTATE_SETROE 0x00000800 -#define ASCWHBSTATE_SETTOE 0x00001000 -#define ASCWHBSTATE_SETBE 0x00002000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_CLRABEN 0x0001 -#define ASCWHBABCON_SETABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_CLRSCCDET 0x0040 -#define ASCWHBABSTAT_SETSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFIFO1 0x00000400 -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFIFO1 0x00000400 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -typedef struct IfxAsc_s -{ - unsigned long asc_clc; /*0x0000*/ - unsigned long asc_pisel; /*0x0004*/ - unsigned long asc_id; /*0x0008*/ - unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/ - unsigned long asc_con; /*0x0010*/ - unsigned long asc_state; /*0x0014*/ - unsigned long asc_whbstate; /*0x0018*/ - unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/ - unsigned long asc_tbuf; /*0x0020*/ - unsigned long asc_rbuf; /*0x0024*/ - unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/ - unsigned long asc_abcon; /*0x0030*/ - unsigned long asc_abstat; /* not used */ /*0x0034*/ - unsigned long asc_whbabcon; /*0x0038*/ - unsigned long asc_whbabstat; /* not used */ /*0x003C*/ - unsigned long asc_rxfcon; /*0x0040*/ - unsigned long asc_txfcon; /*0x0044*/ - unsigned long asc_fstat; /*0x0048*/ - unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/ - unsigned long asc_bg; /*0x0050*/ - unsigned long asc_bg_timer; /*0x0054*/ - unsigned long asc_fdv; /*0x0058*/ - unsigned long asc_pmw; /*0x005C*/ - unsigned long asc_modcon; /*0x0060*/ - unsigned long asc_modstat; /*0x0064*/ - unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/ - unsigned long asc_sfcc; /*0x0070*/ - unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/ - unsigned long asc_eomcon; /*0x0080*/ - unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/ - unsigned long asc_dmacon; /*0x00EC*/ - unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/ - unsigned long asc_irnen; /*0x00F4*/ - unsigned long asc_irnicr; /*0x00F8*/ - unsigned long asc_irncr; /*0x00FC*/ -} IfxAsc_t; - - -/* Register access macros */ -#define asc_readl(reg) \ - readl(&pAsc->reg) -#define asc_writel(reg,value) \ - writel((value), &pAsc->reg) - - -#endif /* __ASC_H */ diff --git a/package/uboot-lantiq/files/include/asm-mips/ar9.h b/package/uboot-lantiq/files/include/asm-mips/ar9.h deleted file mode 100644 index cfafe44906..0000000000 --- a/package/uboot-lantiq/files/include/asm-mips/ar9.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * (C) Copyright 2010 - * Ralph Hempel - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ -#define AR9_PMU (0xBF102000) -/* PMU Power down Control Register */ -#define AR9_PMU_PWDCR ((volatile u32*)(AR9_PMU + 0x001C)) -/* PMU Status Register */ -#define AR9_PMU_SR ((volatile u32*)(AR9_PMU + 0x0020)) -/** DMA block */ -#define AR9_PMU_DMA (1<<5) -#define AR9_PMU_SDIO (1<<16) -#define AR9_PMU_USB0 (1<<6) -#define AR9_PMU_USB0_P (1<<0) -#define AR9_PMU_SWITCH (1<<28) - - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ -#define AR9_RCU_BASE_ADDR (0xBF203000) -#define AR9_RCU_RST_REQ ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0010)) -#define AR9_RCU_RST_STAT ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0014)) -#define AR9_RST_ALL (1 << 30) - -/*** Reset Request Register Bits ***/ -#define AR9_RCU_RST_REQ_SRST (1 << 30) -#define AR9_RCU_RST_REQ_ARC_JTAG (1 << 20) -#define AR9_RCU_RST_REQ_PCI (1 << 13) -#define AR9_RCU_RST_REQ_AFE (1 << 11) -#define AR9_RCU_RST_REQ_SDIO (1 << 19) -#define AR9_RCU_RST_REQ_DMA (1 << 9) -#define AR9_RCU_RST_REQ_PPE (1 << 8) -#define AR9_RCU_RST_REQ_DFE (1 << 7) - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ -#define AR9_GPIO (0xBE100B00) -/***Port 0 Data Output Register (0010H)***/ -#define AR9_GPIO_P0_OUT ((volatile u32 *)(AR9_GPIO+ 0x0010)) -/***Port 1 Data Output Register (0040H)***/ -#define AR9_GPIO_P1_OUT ((volatile u32 *)(AR9_GPIO+ 0x0040)) -/***Port 2 Data Output Register (0070H)***/ -#define AR9_GPIO_P2_OUT ((volatile u32 *)(AR9_GPIO+ 0x0070)) -/***Port 3 Data Output Register (00A0H)***/ -#define AR9_GPIO_P3_OUT ((volatile u32 *)(AR9_GPIO+ 0x00A0)) -/***Port 0 Data Input Register (0014H)***/ -#define AR9_GPIO_P0_IN ((volatile u32 *)(AR9_GPIO+ 0x0014)) -/***Port 1 Data Input Register (0044H)***/ -#define AR9_GPIO_P1_IN ((volatile u32 *)(AR9_GPIO+ 0x0044)) -/***Port 2 Data Input Register (0074H)***/ -#define AR9_GPIO_P2_IN ((volatile u32 *)(AR9_GPIO+ 0x0074)) -/***Port 3 Data Input Register (00A4H)***/ -#define AR9_GPIO_P3_IN ((volatile u32 *)(AR9_GPIO+ 0x00A4)) -/***Port 0 Direction Register (0018H)***/ -#define AR9_GPIO_P0_DIR ((volatile u32 *)(AR9_GPIO+ 0x0018)) -/***Port 1 Direction Register (0048H)***/ -#define AR9_GPIO_P1_DIR ((volatile u32 *)(AR9_GPIO+ 0x0048)) -/***Port 2 Direction Register (0078H)***/ -#define AR9_GPIO_P2_DIR ((volatile u32 *)(AR9_GPIO+ 0x0078)) -/***Port 3 Direction Register (0048H)***/ -#define AR9_GPIO_P3_DIR ((volatile u32 *)(AR9_GPIO+ 0x00A8)) -/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -#define AR9_GPIO_P0_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x001C)) -/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -#define AR9_GPIO_P1_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x004C)) -/***Port 2 Alternate Function Select Register 0 (007C H) ***/ -#define AR9_GPIO_P2_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x007C)) -/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ -#define AR9_GPIO_P3_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x00AC)) -/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -#define AR9_GPIO_P0_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0020)) -/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -#define AR9_GPIO_P1_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0050)) -/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ -#define AR9_GPIO_P2_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0080)) -/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ -#define AR9_GPIO_P3_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0064)) -/***Port 0 Open Drain Control Register (0024H)***/ -#define AR9_GPIO_P0_OD ((volatile u32 *)(AR9_GPIO+ 0x0024)) -/***Port 1 Open Drain Control Register (0054H)***/ -#define AR9_GPIO_P1_OD ((volatile u32 *)(AR9_GPIO+ 0x0054)) -/***Port 2 Open Drain Control Register (0084H)***/ -#define AR9_GPIO_P2_OD ((volatile u32 *)(AR9_GPIO+ 0x0084)) -/***Port 3 Open Drain Control Register (0034H)***/ -#define AR9_GPIO_P3_OD ((volatile u32 *)(AR9_GPIO+ 0x0034)) -/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -#define AR9_GPIO_P0_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0028)) -/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -#define AR9_GPIO_P1_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0058)) -/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ -#define AR9_GPIO_P2_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0088)) -/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ -//#define AR9_GPIO_P3_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0094)) -/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -#define AR9_GPIO_P0_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x002C)) -/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -#define AR9_GPIO_P1_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x005C)) -/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ -#define AR9_GPIO_P2_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x008C)) -/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ -#define AR9_GPIO_P3_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x0038)) -/***Port 0 Pull Up Device Enable Register (0030 H)***/ -#define AR9_GPIO_P0_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0030)) -/***Port 1 Pull Up Device Enable Register (0060 H)***/ -#define AR9_GPIO_P1_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0060)) -/***Port 2 Pull Up Device Enable Register (0090 H)***/ -#define AR9_GPIO_P2_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0090)) -/***Port 3 Pull Up Device Enable Register (003c H)***/ -#define AR9_GPIO_P3_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x003C)) - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ -#define AR9_CGU (0xBF103000) -/***CGU Clock PLL0 ***/ -#define AR9_CGU_PLL0_CFG ((volatile u32*)(AR9_CGU+ 0x0004)) -/***CGU Clock PLL1 ***/ -#define AR9_CGU_PLL1_CFG ((volatile u32*)(AR9_CGU+ 0x0008)) -/***CGU Clock SYS Mux Register***/ -#define AR9_CGU_SYS ((volatile u32*)(AR9_CGU+ 0x0010)) -/***CGU Interface Clock Control Register***/ -#define AR9_CGU_IFCCR ((volatile u32*)(AR9_CGU+ 0x0018)) -/***CGU PCI Clock Control Register**/ -#define AR9_CGU_PCICR ((volatile u32*)(AR9_CGU+ 0x0034)) -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_166M 166666667 -#define CLOCK_196M 196666667 -#define CLOCK_333M 333333333 -#define CLOCK_366M 366666667 -#define CLOCK_500M 500000000 - -/***********************************************************************/ -/* Module : MPS register address and bits */ -/***********************************************************************/ -#define AR9_MPS (KSEG1+0x1F107000) -#define AR9_MPS_CHIPID ((volatile u32*)(AR9_MPS + 0x0344)) -#define AR9_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define AR9_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define AR9_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ -#define AR9_EBU (0xBE105300) - -#define AR9_EBU_CLC ((volatile u32*)(AR9_EBU+ 0x0000)) -#define AR9_EBU_CLC_DISS (1 << 1) -#define AR9_EBU_CLC_DISR (1 << 0) - -#define AR9_EBU_ID ((volatile u32*)(AR9_EBU+ 0x0008)) - -/***EBU Global Control Register***/ -#define AR9_EBU_CON ((volatile u32*)(AR9_EBU+ 0x0010)) -#define AR9_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define AR9_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define AR9_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define AR9_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define AR9_EBU_CON_ARBSYNC (1 << 5) -//#define AR9_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define AR9_EBU_ADDSEL0 ((volatile u32*)(AR9_EBU + 0x0020)) -/***EBU Address Select Register 1***/ -#define AR9_EBU_ADDSEL1 ((volatile u32*)(AR9_EBU + 0x0024)) -/***EBU Address Select Register 2***/ -#define AR9_EBU_ADDSEL2 ((volatile u32*)(AR9_EBU + 0x0028)) -/***EBU Address Select Register 3***/ -#define AR9_EBU_ADDSEL3 ((volatile u32*)(AR9_EBU + 0x002C)) -#define AR9_EBU_ADDSEL_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define AR9_EBU_ADDSEL_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define AR9_EBU_ADDSEL_MIRRORE (1 << 1) -#define AR9_EBU_ADDSEL_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define AR9_EBU_BUSCON0 ((volatile u32*)(AR9_EBU+ 0x0060)) -#define AR9_EBU_BUSCON0_WRDIS (1 << 31) -#define AR9_EBU_BUSCON0_ADSWP (value) (1 << 30) -#define AR9_EBU_BUSCON0_PG_EN (value) (1 << 29) -#define AR9_EBU_BUSCON0_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24) -#define AR9_EBU_BUSCON0_SETUP (1 << 22) -#define AR9_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define AR9_EBU_BUSCON0_WAITINV (1 << 19) -#define AR9_EBU_BUSCON0_VN_EN (1 << 18) -#define AR9_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define AR9_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14) -#define AR9_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12) -#define AR9_EBU_BUSCON0_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8) -#define AR9_EBU_BUSCON0_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6) -#define AR9_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define AR9_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define AR9_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define AR9_EBU_BUSCON1 ((volatile u32*)(AR9_EBU+ 0x0064)) -#define AR9_EBU_BUSCON1_WRDIS (1 << 31) -#define AR9_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define AR9_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define AR9_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define AR9_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define AR9_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define AR9_EBU_BUSCON1_WAITINV (1 << 19) -#define AR9_EBU_BUSCON1_SETUP (1 << 18) -#define AR9_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define AR9_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define AR9_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define AR9_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define AR9_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define AR9_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define AR9_EBU_BUSCON2 ((volatile u32*)(AR9_EBU+ 0x0068)) -#define AR9_EBU_BUSCON2_WRDIS (1 << 31) -#define AR9_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define AR9_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define AR9_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define AR9_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define AR9_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define AR9_EBU_BUSCON2_WAITINV (1 << 19) -#define AR9_EBU_BUSCON2_SETUP (1 << 18) -#define AR9_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define AR9_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define AR9_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define AR9_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define AR9_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define AR9_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define AR9_EBU_BUSCON3 ((volatile u32*)(AR9_EBU+ 0x006C)) -#define AR9_EBU_BUSCON3_WRDIS (1 << 31) -#define AR9_EBU_BUSCON3_ADSWP (value) (1 << 30) -#define AR9_EBU_BUSCON3_PG_EN (value) (1 << 29) -#define AR9_EBU_BUSCON3_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24) -#define AR9_EBU_BUSCON3_SETUP (1 << 22) -#define AR9_EBU_BUSCON3_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define AR9_EBU_BUSCON3_WAITINV (1 << 19) -#define AR9_EBU_BUSCON3_VN_EN (1 << 18) -#define AR9_EBU_BUSCON3_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define AR9_EBU_BUSCON3_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14) -#define AR9_EBU_BUSCON3_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12) -#define AR9_EBU_BUSCON3_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8) -#define AR9_EBU_BUSCON3_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6) -#define AR9_EBU_BUSCON3_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define AR9_EBU_BUSCON3_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define AR9_EBU_BUSCON3_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ -#define AR9_SDRAM (0xBF800000) - -/***********************************************************************/ -/* Module : ASC0 register address and bits */ -/***********************************************************************/ -#define AR9_ASC0 (KSEG1 | 0x1E100400) -#define AR9_ASC0_TBUF ((volatile u32*)(AR9_ASC0 + 0x0020)) -#define AR9_ASC0_RBUF ((volatile u32*)(AR9_ASC0 + 0x0024)) -#define AR9_ASC0_FSTAT ((volatile u32*)(AR9_ASC0 + 0x0048)) - -/***********************************************************************/ -/* Module : ASC1 register address and bits */ -/***********************************************************************/ -#define AR9_ASC1 (KSEG1 | 0x1E100C00) -#define AR9_ASC1_TBUF ((volatile u32*)(AR9_ASC1 + 0x0020)) -#define AR9_ASC1_RBUF ((volatile u32*)(AR9_ASC1 + 0x0024)) -#define AR9_ASC1_FSTAT ((volatile u32*)(AR9_ASC1 + 0x0048)) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ -#define AR9_DMA_OFFSET (0xBE104100) -/***********************************************************************/ -#define AR9_DMA_CLC ((volatile u32*)(AR9_DMA_OFFSET + 0x0000)) -#define AR9_DMA_ID ((volatile u32*)(AR9_DMA_OFFSET + 0x0008)) -#define AR9_DMA_CTRL (volatile u32*)(AR9_DMA_BASE + 0x10) - -/** DMA Port Select Register */ -#define AR9_DMA_PS ((volatile u32*)(AR9_DMA_OFFSET + 0x0040)) -/** DMA Port Control Register */ -#define AR9_DMA_PCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x0044)) -#define AR9_DMA_IRNEN ((volatile u32*)(AR9_DMA_OFFSET + 0x00F4)) -#define AR9_DMA_IRNCR ((volatile u32*)(AR9_DMA_OFFSET + 0x00F8)) -#define AR9_DMA_IRNICR ((volatile u32*)(AR9_DMA_OFFSET + 0x00FC)) - -#define AR9_DMA_CS ((volatile u32*)(AR9_DMA_OFFSET + 0x0018)) -#define AR9_DMA_CCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x001C)) -#define AR9_DMA_CDBA ((volatile u32*)(AR9_DMA_OFFSET + 0x0020)) -#define AR9_DMA_CIE ((volatile u32*)(AR9_DMA_OFFSET + 0x002C)) -#define AR9_DMA_CIS ((volatile u32*)(AR9_DMA_OFFSET + 0x0028)) -#define AR9_DMA_CDLEN ((volatile u32*)(AR9_DMA_OFFSET + 0x0024)) -#define AR9_DMA_CPOLL ((volatile u32*)(AR9_DMA_OFFSET + 0x0014)) - -/***********************************************************************/ -/* Module : GPORT switch register */ -/***********************************************************************/ -#define AR9_SW (0xBE108000) -#define AR9_SW_PS (AR9_SW + 0x000) -#define AR9_SW_P0_CTL (AR9_SW + 0x004) -#define AR9_SW_P1_CTL (AR9_SW + 0x008) -#define AR9_SW_P2_CTL (AR9_SW + 0x00C) -#define AR9_SW_P0_VLAN (AR9_SW + 0x010) -#define AR9_SW_P1_VLAN (AR9_SW + 0x014) -#define AR9_SW_P2_VLAN (AR9_SW + 0x018) -#define AR9_SW_P0_INCTL (AR9_SW + 0x020) -#define AR9_SW_P1_INCTL (AR9_SW + 0x024) -#define AR9_SW_P2_INCTL (AR9_SW + 0x028) -#define AR9_SW_DF_PORTMAP (AR9_SW + 0x02C) -#define AR9_SW_P0_ECS_Q32 (AR9_SW + 0x030) -#define AR9_SW_P0_ECS_Q10 (AR9_SW + 0x034) -#define AR9_SW_P0_ECW_Q32 (AR9_SW + 0x038) -#define AR9_SW_P0_ECW_Q10 (AR9_SW + 0x03C) -#define AR9_SW_P1_ECS_Q32 (AR9_SW + 0x040) -#define AR9_SW_P1_ECS_Q10 (AR9_SW + 0x044) -#define AR9_SW_P1_ECW_Q32 (AR9_SW + 0x048) -#define AR9_SW_P1_ECW_Q10 (AR9_SW + 0x04C) -#define AR9_SW_P2_ECS_Q32 (AR9_SW + 0x050) -#define AR9_SW_P2_ECS_Q10 (AR9_SW + 0x054) -#define AR9_SW_P2_ECW_Q32 (AR9_SW + 0x058) -#define AR9_SW_P2_ECW_Q10 (AR9_SW + 0x05C) -#define AR9_SW_INT_ENA (AR9_SW + 0x060) -#define AR9_SW_INT_ST (AR9_SW + 0x064) -#define AR9_SW_GCTL0 (AR9_SW + 0x068) -#define AR9_SW_GCTL1 (AR9_SW + 0x06C) -#define AR9_SW_ARP (AR9_SW + 0x070) -#define AR9_SW_STRM_CTL (AR9_SW + 0x074) -#define AR9_SW_RGMII_CTL (AR9_SW + 0x078) -#define AR9_SW_1P_PRT (AR9_SW + 0x07C) -#define AR9_SW_GBKT_SZBS (AR9_SW + 0x080) -#define AR9_SW_GBKT_SZEBS (AR9_SW + 0x084) -#define AR9_SW_BF_TH (AR9_SW + 0x088) -#define AR9_SW_PMAC_HD_CTL (AR9_SW + 0x08C) -#define AR9_SW_PMAC_SA1 (AR9_SW + 0x090) -#define AR9_SW_PMAC_SA2 (AR9_SW + 0x094) -#define AR9_SW_PMAC_DA1 (AR9_SW + 0x098) -#define AR9_SW_PMAC_DA2 (AR9_SW + 0x09C) -#define AR9_SW_PMAC_VLAN (AR9_SW + 0x0A0) -#define AR9_SW_PMAC_TX_IPG (AR9_SW + 0x0A4) -#define AR9_SW_PMAC_RX_IPG (AR9_SW + 0x0A8) -#define AR9_SW_ADR_TB_CTL0 (AR9_SW + 0x0AC) -#define AR9_SW_ADR_TB_CTL1 (AR9_SW + 0x0B0) -#define AR9_SW_ADR_TB_CTL2 (AR9_SW + 0x0B4) -#define AR9_SW_ADR_TB_ST0 (AR9_SW + 0x0B8) -#define AR9_SW_ADR_TB_ST1 (AR9_SW + 0x0BC) -#define AR9_SW_ADR_TB_ST2 (AR9_SW + 0x0C0) -#define AR9_SW_RMON_CTL (AR9_SW + 0x0C4) -#define AR9_SW_RMON_ST (AR9_SW + 0x0C8) -#define AR9_SW_MDIO_CTL (AR9_SW + 0x0CC) -#define AR9_SW_MDIO_DATA (AR9_SW + 0x0D0) -#define AR9_SW_TP_FLT_ACT (AR9_SW + 0x0D4) -#define AR9_SW_PRTCL_FLT_ACT (AR9_SW + 0x0D8) -#define AR9_SW_VLAN_FLT0 (AR9_SW + 0x100) -#define AR9_SW_VLAN_FLT1 (AR9_SW + 0x104) -#define AR9_SW_VLAN_FLT2 (AR9_SW + 0x108) -#define AR9_SW_VLAN_FLT3 (AR9_SW + 0x10C) -#define AR9_SW_VLAN_FLT4 (AR9_SW + 0x110) -#define AR9_SW_VLAN_FLT5 (AR9_SW + 0x114) -#define AR9_SW_VLAN_FLT6 (AR9_SW + 0x118) -#define AR9_SW_VLAN_FLT7 (AR9_SW + 0x11C) -#define AR9_SW_VLAN_FLT8 (AR9_SW + 0x120) -#define AR9_SW_VLAN_FLT9 (AR9_SW + 0x124) -#define AR9_SW_VLAN_FLT10 (AR9_SW + 0x128) -#define AR9_SW_VLAN_FLT11 (AR9_SW + 0x12C) -#define AR9_SW_VLAN_FLT12 (AR9_SW + 0x130) -#define AR9_SW_VLAN_FLT13 (AR9_SW + 0x134) -#define AR9_SW_VLAN_FLT14 (AR9_SW + 0x138) -#define AR9_SW_VLAN_FLT15 (AR9_SW + 0x13C) -#define AR9_SW_TP_FLT10 (AR9_SW + 0x140) -#define AR9_SW_TP_FLT32 (AR9_SW + 0x144) -#define AR9_SW_TP_FLT54 (AR9_SW + 0x148) -#define AR9_SW_TP_FLT76 (AR9_SW + 0x14C) -#define AR9_SW_DFSRV_MAP0 (AR9_SW + 0x150) -#define AR9_SW_DFSRV_MAP1 (AR9_SW + 0x154) -#define AR9_SW_DFSRV_MAP2 (AR9_SW + 0x158) -#define AR9_SW_DFSRV_MAP3 (AR9_SW + 0x15C) -#define AR9_SW_TCP_PF0 (AR9_SW + 0x160) -#define AR9_SW_TCP_PF1 (AR9_SW + 0x164) -#define AR9_SW_TCP_PF2 (AR9_SW + 0x168) -#define AR9_SW_TCP_PF3 (AR9_SW + 0x16C) -#define AR9_SW_TCP_PF4 (AR9_SW + 0x170) -#define AR9_SW_TCP_PF5 (AR9_SW + 0x174) -#define AR9_SW_TCP_PF6 (AR9_SW + 0x178) -#define AR9_SW_TCP_PF7 (AR9_SW + 0x17C) -#define AR9_SW_RA_03_00 (AR9_SW + 0x180) -#define AR9_SW_RA_07_04 (AR9_SW + 0x184) -#define AR9_SW_RA_0B_08 (AR9_SW + 0x188) -#define AR9_SW_RA_0F_0C (AR9_SW + 0x18C) -#define AR9_SW_RA_13_10 (AR9_SW + 0x190) -#define AR9_SW_RA_17_14 (AR9_SW + 0x194) -#define AR9_SW_RA_1B_18 (AR9_SW + 0x198) -#define AR9_SW_RA_1F_1C (AR9_SW + 0x19C) -#define AR9_SW_RA_23_20 (AR9_SW + 0x1A0) -#define AR9_SW_RA_27_24 (AR9_SW + 0x1A4) -#define AR9_SW_RA_2B_28 (AR9_SW + 0x1A8) -#define AR9_SW_RA_2F_2C (AR9_SW + 0x1AC) -#define AR9_SW_F0 (AR9_SW + 0x1B0) -#define AR9_SW_F1 (AR9_SW + 0x1B4) - -#define REG32(addr) *((volatile u32 *)(addr)) diff --git a/package/uboot-lantiq/files/include/asm-mips/danube.h b/package/uboot-lantiq/files/include/asm-mips/danube.h deleted file mode 100644 index 7caf8f7aa0..0000000000 --- a/package/uboot-lantiq/files/include/asm-mips/danube.h +++ /dev/null @@ -1,2015 +0,0 @@ -#ifndef DANUBE_H -#define DANUBE_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - -/***********************************************************************/ -/* Module : MEI register address and bits */ -/***********************************************************************/ -#define MEI_SPACE_ACCESS 0xB0100C00 -#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS) -#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS) -#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS) -#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS) -#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS) -#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS) -#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS) -#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS) -#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS) -#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS) -#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS) - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ -#define DANUBE_BIU_WDT_BASE (0xBf8803F0) -#define DANUBE_BIU_WDT_CR (0x0000 + DANUBE_BIU_WDT_BASE) -#define DANUBE_BIU_WDT_SR (0x0008 + DANUBE_BIU_WDT_BASE) - - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ -#define DANUBE_PMU_BASE_ADDR (KSEG1+0x1F102000) - -/***PM Control Register***/ -#define DANUBE_PMU_CR ((volatile u32*)(0x001C + DANUBE_PMU_BASE_ADDR)) -#define DANUBE_PMU_PWDCR DANUBE_PMU_CR -#define DANUBE_PMU_SR ((volatile u32*)(0x0020 + DANUBE_PMU_BASE_ADDR)) - -#define DANUBE_PMU_DMA_SHIFT 5 -#define DANUBE_PMU_PPE_SHIFT 13 -#define DANUBE_PMU_ETOP_SHIFT 22 -#define DANUBE_PMU_ENET0_SHIFT 24 -#define DANUBE_PMU_ENET1_SHIFT 25 - - -#define DANUBE_PMU DANUBE_PMU_BASE_ADDR -/***PM Global Enable Register***/ -#define DANUBE_PMU_PM_GEN ((volatile u32*)(DANUBE_PMU+ 0x0000)) -#define DANUBE_PMU_PM_GEN_EN16 (1 << 16) -#define DANUBE_PMU_PM_GEN_EN15 (1 << 15) -#define DANUBE_PMU_PM_GEN_EN14 (1 << 14) -#define DANUBE_PMU_PM_GEN_EN13 (1 << 13) -#define DANUBE_PMU_PM_GEN_EN12 (1 << 12) -#define DANUBE_PMU_PM_GEN_EN11 (1 << 11) -#define DANUBE_PMU_PM_GEN_EN10 (1 << 10) -#define DANUBE_PMU_PM_GEN_EN9 (1 << 9) -#define DANUBE_PMU_PM_GEN_EN8 (1 << 8) -#define DANUBE_PMU_PM_GEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_GEN_EN6 (1 << 6) -#define DANUBE_PMU_PM_GEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_GEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_GEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_GEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define DANUBE_PMU_PM_PDEN ((volatile u32*)(DANUBE_PMU+ 0x0008)) -#define DANUBE_PMU_PM_PDEN_EN16 (1 << 16) -#define DANUBE_PMU_PM_PDEN_EN15 (1 << 15) -#define DANUBE_PMU_PM_PDEN_EN14 (1 << 14) -#define DANUBE_PMU_PM_PDEN_EN13 (1 << 13) -#define DANUBE_PMU_PM_PDEN_EN12 (1 << 12) -#define DANUBE_PMU_PM_PDEN_EN11 (1 << 11) -#define DANUBE_PMU_PM_PDEN_EN10 (1 << 10) -#define DANUBE_PMU_PM_PDEN_EN9 (1 << 9) -#define DANUBE_PMU_PM_PDEN_EN8 (1 << 8) -#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010)) -#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16) -#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15) -#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14) -#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13) -#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12) -#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11) -#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10) -#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9) -#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8) -#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010)) -#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16) -#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15) -#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14) -#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13) -#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12) -#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11) -#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10) -#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9) -#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8) -#define DANUBE_PMU_PM_WUP_WUP7 (1 << 7) -#define DANUBE_PMU_PM_WUP_WUP5 (1 << 5) -#define DANUBE_PMU_PM_WUP_WUP4 (1 << 4) -#define DANUBE_PMU_PM_WUP_WUP3 (1 << 3) -#define DANUBE_PMU_PM_WUP_WUP2 (1 << 2) -#define DANUBE_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define DANUBE_PMU_PM_CR ((volatile u32*)(DANUBE_PMU+ 0x0014)) -#define DANUBE_PMU_PM_CR_AWEN (1 << 31) -#define DANUBE_PMU_PM_CR_SWRST (1 << 30) -#define DANUBE_PMU_PM_CR_SWCR (1 << 2) -#define DANUBE_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ -#define DANUBE_RCU_BASE_ADDR (0xBF203000) - -#define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR) -#define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_REQ)) -#define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR) -#define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT)) -#define DANUBE_RCU_PCI_RDY ( (volatile u32 *)(DANUBE_RCU_BASE_ADDR+0x28)) -#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR) - - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ -#define DANUBE_BCU_BASE_ADDR (0xB0100000) -/***BCU Control Register (0010H)***/ -#define DANUBE_BCU_CON (0x0010 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define DANUBE_BCU_BCU_CON_SPE (1 << 19) -#define DANUBE_BCU_BCU_CON_PSE (1 << 18) -#define DANUBE_BCU_BCU_CON_DBG (1 << 16) -#define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - - -/***BCU Error Control Capture Register (0020H)***/ -#define DANUBE_BCU_ECON (0x0020 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define DANUBE_BCU_BCU_ECON_RDN (1 << 23) -#define DANUBE_BCU_BCU_ECON_WRN (1 << 22) -#define DANUBE_BCU_BCU_ECON_SVM (1 << 21) -#define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define DANUBE_BCU_BCU_ECON_ABT (1 << 18) -#define DANUBE_BCU_BCU_ECON_RDY (1 << 17) -#define DANUBE_BCU_BCU_ECON_TOUT (1 << 16) -#define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define DANUBE_BCU_EADD (0x0024 + DANUBE_BCU_BASE_ADDR) - -/***BCU Error Data Capture Register (0028H)***/ -#define DANUBE_BCU_EDAT (0x0028 + DANUBE_BCU_BASE_ADDR) - -#define DANUBE_BCU_IRNEN (0x00F4 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_IRNICR (0x00F8 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_IRNCR (0x00FC + DANUBE_BCU_BASE_ADDR) - - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define DANUBE_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080)) -#define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_MBC_MBC_CFG_RES (1 << 5) -#define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define DANUBE_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084)) -#define DANUBE_MBC_MBC_ISR_B3DA (1 << 31) -#define DANUBE_MBC_MBC_ISR_B2DA (1 << 30) -#define DANUBE_MBC_MBC_ISR_B1E (1 << 29) -#define DANUBE_MBC_MBC_ISR_B0E (1 << 28) -#define DANUBE_MBC_MBC_ISR_WDT (1 << 27) -#define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088)) -#define DANUBE_MBC_MBC_MSK_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C)) -#define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK01_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK01_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK01_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090)) -#define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK10_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK10_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK10_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094)) -#define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000)) -#define DANUBE_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020)) -#define DANUBE_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040)) -#define DANUBE_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060)) -#define DANUBE_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004)) -#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024)) -#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044)) -#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064)) -#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008)) -#define DANUBE_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028)) -#define DANUBE_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048)) -#define DANUBE_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068)) -#define DANUBE_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C)) -#define DANUBE_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C)) -#define DANUBE_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C)) -#define DANUBE_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C)) -#define DANUBE_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010)) -#define DANUBE_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030)) -#define DANUBE_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050)) -#define DANUBE_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070)) -#define DANUBE_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014)) -#define DANUBE_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034)) -#define DANUBE_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054)) -#define DANUBE_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074)) -#define DANUBE_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018)) -#define DANUBE_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038)) -#define DANUBE_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058)) -#define DANUBE_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078)) -#define DANUBE_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C)) -#define DANUBE_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C)) -#define DANUBE_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C)) -#define DANUBE_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C)) -#define DANUBE_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0)) -#define DANUBE_MBC_DCTRL_BA (1 << 0) -#define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define DANUBE_MBC_DCTRL_IDL (1 << 4) -#define DANUBE_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4)) -#define DANUBE_MBC_DSTA_IDLE (1 << 0) -#define DANUBE_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8)) -#define DANUBE_MBC_DTST1_ABORT (1 << 0) -#define DANUBE_MBC_DTST1_HWF32 (1 << 1) -#define DANUBE_MBC_DTST1_HWF4M (1 << 2) -#define DANUBE_MBC_DTST1_HWFOP (1 << 3) - - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ -#define DANUBE_SSC1 (KSEG1+0x1e100800) -/***********************************************************************/ -/***SSC Clock Control Register***/ -#define DANUBE_SSC_CLC (0x0000) -#define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_SSC_CLC_DISS (1 << 1) -#define DANUBE_SSC_CLC_DISR (1 << 0) -/***SSC Port Input Selection Register***/ -#define DANUBE_SSC_PISEL (0x0004) -/***SSC Identification Register***/ -#define DANUBE_SSC_ID (0x0008) -/***Control Register (Programming Mode)***/ -#define DANUBE_SSC_CON (0x0010) -#define DANUBE_SSC_CON_RUEN (1 << 12) -#define DANUBE_SSC_CON_TUEN (1 << 11) -#define DANUBE_SSC_CON_AEN (1 << 10) -#define DANUBE_SSC_CON_REN (1 << 9) -#define DANUBE_SSC_CON_TEN (1 << 8) -#define DANUBE_SSC_CON_LB (1 << 7) -#define DANUBE_SSC_CON_PO (1 << 6) -#define DANUBE_SSC_CON_PH (1 << 5) -#define DANUBE_SSC_CON_HB (1 << 4) -#define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16) -#define DANUBE_SSC_CON_RX_OFF (1 << 1) -#define DANUBE_SSC_CON_TX_OFF (1 << 0) -/***SCC Status Register***/ -#define DANUBE_SSC_STATE (0x0014) -#define DANUBE_SSC_STATE_EN (1 << 0) -#define DANUBE_SSC_STATE_MS (1 << 1) -#define DANUBE_SSC_STATE_BSY (1 << 13) -#define DANUBE_SSC_STATE_RUE (1 << 12) -#define DANUBE_SSC_STATE_TUE (1 << 11) -#define DANUBE_SSC_STATE_AE (1 << 10) -#define DANUBE_SSC_STATE_RE (1 << 9) -#define DANUBE_SSC_STATE_TE (1 << 8) -#define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16) -/***SSC Write Hardware Modified Control Register***/ -#define DANUBE_SSC_WHBSTATE ( 0x0018) -#define DANUBE_SSC_WHBSTATE_SETBE (1 << 15) -#define DANUBE_SSC_WHBSTATE_SETPE (1 << 14) -#define DANUBE_SSC_WHBSTATE_SETRE (1 << 13) -#define DANUBE_SSC_WHBSTATE_SETTE (1 << 12) -#define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11) -#define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10) -#define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9) -#define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8) -/***SSC Transmitter Buffer Register***/ -#define DANUBE_SSC_TB (0x0020) -#define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -/***SSC Receiver Buffer Register***/ -#define DANUBE_SSC_RB (0x0024) -#define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -/***SSC Receive FIFO Control Register***/ -#define DANUBE_SSC_RXFCON (0x0030) -#define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_RXFCON_RXTMEN (1 << 2) -#define DANUBE_SSC_RXFCON_RXFLU (1 << 1) -#define DANUBE_SSC_RXFCON_RXFEN (1 << 0) -/***SSC Transmit FIFO Control Register***/ -#define DANUBE_SSC_TXFCON ( 0x0034) -#define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_TXFCON_TXTMEN (1 << 2) -#define DANUBE_SSC_TXFCON_TXFLU (1 << 1) -#define DANUBE_SSC_TXFCON_TXFEN (1 << 0) -/***SSC FIFO Status Register***/ -#define DANUBE_SSC_FSTAT (0x0038) -#define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -/***SSC Baudrate Timer Reload Register***/ -#define DANUBE_SSC_BR (0x0040) -#define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -#define DANUBE_SSC_BRSTAT (0x0044) -#define DANUBE_SSC_SFCON (0x0060) -#define DANUBE_SSC_SFSTAT (0x0064) -#define DANUBE_SSC_GPOCON (0x0070) -#define DANUBE_SSC_GPOSTAT (0x0074) -#define DANUBE_SSC_WHBGPOSTAT (0x0078) -#define DANUBE_SSC_RXREQ (0x0080) -#define DANUBE_SSC_RXCNT (0x0084) -/*DMA Registers in Bus Clock Domain*/ -#define DANUBE_SSC_DMA_CON (0x00EC) -/*interrupt Node Registers in Bus Clock Domain*/ -#define DANUBE_SSC_IRNEN (0x00F4) -#define DANUBE_SSC_IRNCR (0x00F8) -#define DANUBE_SSC_IRNICR (0x00FC) -#define DANUBE_SSC_IRN_FIR 0x8 -#define DANUBE_SSC_IRN_EIR 0x4 -#define DANUBE_SSC_IRN_RIR 0x2 -#define DANUBE_SSC_IRN_TIR 0x1 - - -#define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC)) -#define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID)) -#define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON)) -#define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE)) -#define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE)) -#define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB)) -#define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB)) -#define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT)) -#define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL)) -#define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON)) -#define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON)) -#define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR)) -#define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT)) -#define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON)) -#define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT)) -#define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON)) -#define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT)) -#define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT)) -#define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ)) -#define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT)) -#define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON)) -#define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN)) -#define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR)) -#define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR)) - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ -#define DANUBE_GPIO (0xBE100B00) -/***Port 0 Data Output Register (0010H)***/ -#define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010)) -/***Port 1 Data Output Register (0040H)***/ -#define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040)) -/***Port 0 Data Input Register (0014H)***/ -#define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014)) -/***Port 1 Data Input Register (0044H)***/ -#define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044)) -/***Port 0 Direction Register (0018H)***/ -#define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018)) -/***Port 1 Direction Register (0048H)***/ -#define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048)) -/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -#define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C)) -/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -#define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C)) -/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -#define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020)) -/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -#define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050)) -/***Port 0 Open Drain Control Register (0024H)***/ -#define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024)) -/***Port 1 Open Drain Control Register (0054H)***/ -#define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054)) -/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -#define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028)) -/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -#define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058)) -/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -#define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C)) -/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -#define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C)) -/***Port 0 Pull Up Device Enable Register (0030 H)***/ -#define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030)) -/***Port 1 Pull Up Device Enable Register (0060 H)***/ -#define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060)) -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define DANUBE_CGU (0xBF103000) -/***********************************************************************/ - -/***CGU Clock PLL0 ***/ -#define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004)) -/***CGU Clock PLL1 ***/ -#define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008)) -/***CGU Clock SYS Mux Register***/ -#define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010)) -/***CGU Interface Clock Control Register***/ -#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) -/***CGU PCI Clock Control Register**/ -#define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034)) - - -/***********************************************************************/ -/* Module : PCI register address and bits */ -/***********************************************************************/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000) - -#define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004) -#define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010) -#define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014) -#define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018) -#define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C) -#define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020) -#define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024) -#define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028) -#define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C) -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034) -#define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038) -#define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C) -#define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040) -#define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044) -#define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048) -#define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C) -#define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050) -#define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054) -#define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058) -#define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C) -#define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060) -#define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064) -#define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068) -#define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C) -#define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070) -#define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074) -#define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078) -#define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C) -#define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080) -#define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084) -#define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088) -#define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C) -#define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090) -#define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094) -#define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098) -#define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C) -#define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0) -#define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4) -#define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8) -#define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC) - - -/***********************************************************************/ -/* Module : MCD register address and bits */ -/***********************************************************************/ -#define DANUBE_MCD (KSEG1+0x1F106000) - -/***Manufacturer Identification Register***/ -#define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024)) -#define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028)) -#define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -#define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) - -#define DANUBE_CHIPID_STANDARD 0x00EB -#define DANUBE_CHIPID_YANGTSE 0x00ED - -/***Redesign Tracing Identification Register***/ -#define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C)) -#define DANUBE_MCD_RTID_LC (1 << 15) -#define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define DANUBE_EBU (0xBE105300) -#define EBU_NAND_CON (volatile u32*)(DANUBE_EBU + 0xB0) -#define EBU_NAND_WAIT (volatile u32*)(DANUBE_EBU + 0xB4) -#define EBU_NAND_ECC0 (volatile u32*)(DANUBE_EBU + 0xB8) -#define EBU_NAND_ECC_AC (volatile u32*)(DANUBE_EBU + 0xBC) - -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000)) -#define DANUBE_EBU_CLC_DISS (1 << 1) -#define DANUBE_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010)) -#define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_EBU_CON_ARBSYNC (1 << 5) -#define DANUBE_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020)) -#define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024)) -#define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028)) -#define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Address Select Register 3***/ -#define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x002C)) -#define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL3_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060)) -#define DANUBE_EBU_BUSCON0_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON0_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON0_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064)) -#define DANUBE_EBU_BUSCON1_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON1_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON1_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068)) -#define DANUBE_EBU_BUSCON2_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON2_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON2_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define DANUBE_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100)) -#define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108)) -#define DANUBE_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800)) -#define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11) -#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00)) -#define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000)) -#define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008)) -#define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3) -#define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010)) -#define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018)) -#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038)) -#define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040)) -#define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define DANUBE_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000)) -#define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_GPTU_GPT_CLC_DISS (1 << 1) -#define DANUBE_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014)) -#define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7) -#define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6) -#define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C)) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010)) -#define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9) -#define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7) -#define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6) -#define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018)) -#define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9) -#define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7) -#define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6) -#define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048)) -#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050)) -#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030)) -#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034)) -#define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038)) -#define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C)) -#define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040)) -#define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044)) -#define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020)) -#define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15) -#define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7) -#define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6) -#define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054)) -#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C)) -#define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15) -#define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11) -#define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10) -#define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9) -#define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7) -#define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6) -#define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define DANUBE_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) -#define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) -#define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080)) -#define DANUBE_IOM_ISTAH_RME (1 << 7) -#define DANUBE_IOM_ISTAH_RPF (1 << 6) -#define DANUBE_IOM_ISTAH_RFO (1 << 5) -#define DANUBE_IOM_ISTAH_XPR (1 << 4) -#define DANUBE_IOM_ISTAH_XMR (1 << 3) -#define DANUBE_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080)) -#define DANUBE_IOM_MASKH_RME (1 << 7) -#define DANUBE_IOM_MASKH_RPF (1 << 6) -#define DANUBE_IOM_MASKH_RFO (1 << 5) -#define DANUBE_IOM_MASKH_XPR (1 << 4) -#define DANUBE_IOM_MASKH_XMR (1 << 3) -#define DANUBE_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084)) -#define DANUBE_IOM_STAR_XDOV (1 << 7) -#define DANUBE_IOM_STAR_XFW (1 << 6) -#define DANUBE_IOM_STAR_RACI (1 << 3) -#define DANUBE_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084)) -#define DANUBE_IOM_CMDR_RMC (1 << 7) -#define DANUBE_IOM_CMDR_RRES (1 << 6) -#define DANUBE_IOM_CMDR_XTF (1 << 3) -#define DANUBE_IOM_CMDR_XME (1 << 1) -#define DANUBE_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088)) -#define DANUBE_IOM_MODEH_MDS2 (1 << 7) -#define DANUBE_IOM_MODEH_MDS1 (1 << 6) -#define DANUBE_IOM_MODEH_MDS0 (1 << 5) -#define DANUBE_IOM_MODEH_RAC (1 << 3) -#define DANUBE_IOM_MODEH_DIM2 (1 << 2) -#define DANUBE_IOM_MODEH_DIM1 (1 << 1) -#define DANUBE_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C)) -#define DANUBE_IOM_EXMR_XFBS (1 << 7) -#define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define DANUBE_IOM_EXMR_SRA (1 << 4) -#define DANUBE_IOM_EXMR_XCRC (1 << 3) -#define DANUBE_IOM_EXMR_RCRC (1 << 2) -#define DANUBE_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094)) -#define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098)) -#define DANUBE_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098)) -#define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C)) -#define DANUBE_IOM_RBCH_OV (1 << 4) -#define DANUBE_IOM_RBCH_RBC11 (1 << 3) -#define DANUBE_IOM_RBCH_RBC10 (1 << 2) -#define DANUBE_IOM_RBCH_RBC9 (1 << 1) -#define DANUBE_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C)) -#define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define DANUBE_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0)) -#define DANUBE_IOM_RSTA_VFR (1 << 7) -#define DANUBE_IOM_RSTA_RDO (1 << 6) -#define DANUBE_IOM_RSTA_CRC (1 << 5) -#define DANUBE_IOM_RSTA_RAB (1 << 4) -#define DANUBE_IOM_RSTA_SA1 (1 << 3) -#define DANUBE_IOM_RSTA_SA0 (1 << 2) -#define DANUBE_IOM_RSTA_TA (1 << 0) -#define DANUBE_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0)) -#define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define DANUBE_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4)) -#define DANUBE_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) -#define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_IOM_CIR0_CIC0 (1 << 3) -#define DANUBE_IOM_CIR0_CIC1 (1 << 2) -#define DANUBE_IOM_CIR0_SG (1 << 1) -#define DANUBE_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) -#define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_IOM_CIX0_TBA2 (1 << 3) -#define DANUBE_IOM_CIX0_TBA1 (1 << 2) -#define DANUBE_IOM_CIX0_TBA0 (1 << 1) -#define DANUBE_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) -#define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) -#define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_CIX1_CICW (1 << 1) -#define DANUBE_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100)) -#define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104)) -#define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108)) -#define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C)) -#define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110)) -#define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114)) -#define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118)) -#define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C)) -#define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120)) -#define DANUBE_IOM_CO_TSDP10_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124)) -#define DANUBE_IOM_CO_TSDP11_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128)) -#define DANUBE_IOM_CO_TSDP20_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C)) -#define DANUBE_IOM_CO_TSDP21_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138)) -#define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5) -#define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4) -#define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3) -#define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2) -#define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1) -#define DANUBE_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C)) -#define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5) -#define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4) -#define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3) -#define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2) -#define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1) -#define DANUBE_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144)) -#define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148)) -#define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) -#define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6) -#define DANUBE_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) -#define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154)) -#define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7) -#define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C)) -#define DANUBE_IOM_IOM_CR_SPU (1 << 7) -#define DANUBE_IOM_IOM_CR_CI_CS (1 << 5) -#define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4) -#define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3) -#define DANUBE_IOM_IOM_CR_CLKM (1 << 2) -#define DANUBE_IOM_IOM_CR_Res (1 << 1) -#define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160)) -#define DANUBE_IOM_STI_STOV21 (1 << 7) -#define DANUBE_IOM_STI_STOV20 (1 << 6) -#define DANUBE_IOM_STI_STOV11 (1 << 5) -#define DANUBE_IOM_STI_STOV10 (1 << 4) -#define DANUBE_IOM_STI_STI21 (1 << 3) -#define DANUBE_IOM_STI_STI20 (1 << 2) -#define DANUBE_IOM_STI_STI11 (1 << 1) -#define DANUBE_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160)) -#define DANUBE_IOM_ASTI_ACK21 (1 << 3) -#define DANUBE_IOM_ASTI_ACK20 (1 << 2) -#define DANUBE_IOM_ASTI_ACK11 (1 << 1) -#define DANUBE_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164)) -#define DANUBE_IOM_MSTI_STOV21 (1 << 7) -#define DANUBE_IOM_MSTI_STOV20 (1 << 6) -#define DANUBE_IOM_MSTI_STOV11 (1 << 5) -#define DANUBE_IOM_MSTI_STOV10 (1 << 4) -#define DANUBE_IOM_MSTI_STI21 (1 << 3) -#define DANUBE_IOM_MSTI_STI20 (1 << 2) -#define DANUBE_IOM_MSTI_STI11 (1 << 1) -#define DANUBE_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168)) -#define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C)) -#define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC0 register address and bits */ -/***********************************************************************/ -#define DANUBE_ASC0 (KSEG1+0x1E100400) -/***********************************************************************/ -#define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020)) -#define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024)) -#define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048)) -#define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC1 register address and bits */ -/***********************************************************************/ - -#define DANUBE_ASC1 (KSEG1+0x1E100C00) - /***********************************************************************/ - -#define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1 + 0x0020)) -#define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1 + 0x0024)) -#define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1 + 0x0048)) -#define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define DANUBE_DMA (0xBE104100) -/***********************************************************************/ - -#define DANUBE_DMA_BASE DANUBE_DMA -#define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE -#define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08) -#define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10) -#define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14) -#define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18) -#define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C) -#define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20) -#define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24) -#define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28) -#define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C) - -#define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40) -#define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44) - -#define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4) -#define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8) -#define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc) -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define DANUBE_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000)) -#define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19) -#define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18) -#define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17) -#define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16) -#define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15) -#define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14) -#define DANUBE_Debug_MCD_BBS_BT5 (1 << 13) -#define DANUBE_Debug_MCD_BBS_BT4 (1 << 12) -#define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7) -#define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6) -#define DANUBE_Debug_MCD_BBS_BS5 (1 << 5) -#define DANUBE_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008)) -#define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4) -#define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3) -#define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0) - - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define DANUBE_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800)) -#define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define DANUBE_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000)) -#define DANUBE_BIU_BIU_ID_ARCH (1 << 16) -#define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100)) -#define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108)) -#define DANUBE_BIU_BIU_ERRADDR_ADDR - - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define DANUBE_ICU (0xBF880200) -#define DANUBE_ICU (0xBF880200) -#define DANUBE_ICU_EXI (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU+ 0x0000)) -#define DANUBE_ICU_IM0_ISR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Status Register***/ -#define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU+ 0x0020)) -#define DANUBE_ICU_IM1_ISR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Status Register***/ -#define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU+ 0x0040)) -#define DANUBE_ICU_IM2_ISR_IR(value) (1 << (value)) - -/***IM3 Interrupt Status Register***/ -#define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU+ 0x0060)) -#define DANUBE_ICU_IM3_ISR_IR(value) (1 << (value)) - -/***IM4 Interrupt Status Register***/ -#define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU+ 0x0080)) -#define DANUBE_ICU_IM4_ISR_IR(value) (1 << (value)) - - -/***IM0 Interrupt Enable Register***/ -#define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU+ 0x0008)) -#define DANUBE_ICU_IM0_IER_IR(value) (1 << (value)) - - -/***IM1 Interrupt Enable Register***/ -#define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU+ 0x0028)) -#define DANUBE_ICU_IM1_IER_IR(value) (1 << (value)) - - -/***IM2 Interrupt Enable Register***/ -#define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU+ 0x0048)) -#define DANUBE_ICU_IM2_IER_IR(value) (1 << (value)8 - -/***IM3 Interrupt Enable Register***/ -#define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU+ 0x0068)) -#define DANUBE_ICU_IM3_IER_IR(value) (1 << (value)) - -/***IM4 Interrupt Enable Register***/ -#define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU+ 0x0088)) -#define DANUBE_ICU_IM4_IER_IR(value) (1 << (value)) - - -/***IM0 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0010)) -#define DANUBE_ICU_IM0_IOSR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0030)) -#define DANUBE_ICU_IM1_IOSR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0050)) -#define DANUBE_ICU_IM2_IOSR_IR(value) (1 << (value)) - -/***IM3 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0070)) -#define DANUBE_ICU_IM3_IOSR_IR(value) (1 << (value)) - -/***IM4 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0090)) -#define DANUBE_ICU_IM4_IOSR_IR(value) (1 << (value)) - - -/***IM0 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0018)) -#define DANUBE_ICU_IM0_IRSR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0038)) -#define DANUBE_ICU_IM1_IRSR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0058)) -#define DANUBE_ICU_IM2_IRSR_IR(value) (1 << (value)) - -/***IM3 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0078)) -#define DANUBE_ICU_IM3_IRSR_IR(value) (1 << (value)) - -/***IM4 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0098)) -#define DANUBE_ICU_IM4_IRSR_IR(value) (1 << (value)) - -/***Interrupt Vector Value Register***/ -#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x0060)) - -/***Interrupt Vector Value Mask***/ -#define DANUBE_ICU_IM0_VEC_MASK 0x0000001f -#define DANUBE_ICU_IM1_VEC_MASK 0x000003e0 -#define DANUBE_ICU_IM2_VEC_MASK 0x00007c00 -#define DANUBE_ICU_IM3_VEC_MASK 0x000f8000 -#define DANUBE_ICU_IM4_VEC_MASK 0x01f00000 - -/***DMA Interrupt Mask Value***/ -#define DANUBE_DMA_H_MASK 0x00000fff - -/***External Interrupt Control Register***/ -#define DANUBE_ICU_EXTINTCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0000)) -#define DANUBE_ICU_IRNICR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0004)) -#define DANUBE_ICU_IRNCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0008)) -#define DANUBE_ICU_IRNEN ((volatile u32*)(DANUBE_ICU_EXI+ 0x000c)) -#define DANUBE_ICU_NMI_CR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f0)) -#define DANUBE_ICU_NMI_SR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f4)) - -/***********************************************************************/ -/* Module : MPS register address and bits */ -/***********************************************************************/ - -#define DANUBE_MPS (KSEG1+0x1F107000) -/***********************************************************************/ - -#define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344)) -#define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) - - -/* voice channel 0 ... 3 interrupt enable register */ -#define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000)) -#define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004)) -#define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008)) -#define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C)) -/* voice channel 0 ... 3 interrupt status read register */ -#define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010)) -#define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014)) -#define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018)) -#define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C)) -/* voice channel 0 ... 3 interrupt status set register */ -#define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020)) -#define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024)) -#define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028)) -#define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C)) -/* voice channel 0 ... 3 interrupt status clear register */ -#define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030)) -#define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034)) -#define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038)) -#define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C)) -/* common status 0 and 1 read register */ -#define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040)) -#define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044)) -/* common status 0 and 1 set register */ -#define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048)) -#define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C)) -/* common status 0 and 1 clear register */ -#define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050)) -#define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054)) -/* common status 0 and 1 enable register */ -#define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058)) -#define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C)) -/* notification enable register */ -#define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060)) -#define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064)) -/* CPU to CPU interrup request register */ -#define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070)) -#define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074)) -/* Global interrupt request and request enable register */ -#define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078)) -#define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C)) - - -#define DANUBE_MPS_CPU0_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00100)) - -#define DANUBE_MPS_CPU1_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00200)) - -/************************************************************************/ -/* Module : DEU register address and bits */ -/************************************************************************/ -#define DANUBE_DEU_BASE_ADDR (0xBE102000) -/* DEU Control Register */ -#define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000)) -#define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008)) - -/* DEU control register */ -#define DANUBE_DEU_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010)) -#define DANUBE_DEU_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014)) -#define DANUBE_DEU_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018)) -#define DANUBE_DEU_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C)) -#define DANUBE_DEU_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020)) -#define DANUBE_DEU_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024)) -#define DANUBE_DEU_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028)) -#define DANUBE_DEU_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C)) -#define DANUBE_DEU_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030)) -#define DANUBE_DEU_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040)) -#define DANUBE_DEU_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) - -/* AES DEU register */ -#define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) -#define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054)) -#define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058)) -#define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C)) -#define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060)) - -/* AES Key register */ -#define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064)) -#define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068)) -#define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C)) -#define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070)) -#define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074)) -#define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078)) -#define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C)) -#define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080)) - -/* AES vector register */ -#define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084)) -#define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088)) -#define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C)) -#define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090)) -#define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094)) -#define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098)) -#define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C)) -#define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0)) - -/* hash control registe */ -#define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0)) -#define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4)) -#define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 )) -#define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC )) -#define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 )) -#define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4)) -#define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8)) - -#define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC)) - - - - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE_BASE_ADDR (KSEG1 + 0x1E180000) -#define DANUBE_PPE_PP32_DEBUG_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0000) << 2))) -#define DANUBE_PPE_PPM_INT_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0030) << 2))) -#define DANUBE_PPE_PP32_INTERNAL_RES_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0040) << 2))) -#define DANUBE_PPE_PPE_CLOCK_CONTROL_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0100) << 2))) -#define DANUBE_PPE_CDM_CODE_MEMORY_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x1000) << 2))) -#define DANUBE_PPE_CDM_CODE_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x2000) << 2))) -#define DANUBE_PPE_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x4000) << 2))) -#define DANUBE_PPE_PP32_DATA_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x5000) << 2))) -#define DANUBE_PPE_PPM_INT_UNIT_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6000) << 2))) -#define DANUBE_PPE_PPM_TIMER0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6100) << 2))) -#define DANUBE_PPE_PPM_TASK_IND_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6200) << 2))) -#define DANUBE_PPE_PPS_BRK_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6300) << 2))) -#define DANUBE_PPE_PPM_TIMER1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6400) << 2))) -#define DANUBE_PPE_SB_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8000) << 2))) -#define DANUBE_PPE_SB_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8400) << 2))) -#define DANUBE_PPE_SB_RAM2_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8C00) << 2))) -#define DANUBE_PPE_SB_RAM3_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x9600) << 2))) - -#define DANUBE_PPE_PP32_SLEEP DANUBE_PPE_REG_ADDR(0x0010) /* PP32 Power Saving Register */ -#define DANUBE_PPE_CDM_CFG DANUBE_PPE_REG_ADDR(0x0100) /* Code/Data Memory (CDM) Register */ - -/* Mailbox Registers */ -#define DANUBE_PPE_MBOX_IGU0_ISRS DANUBE_PPE_REG_ADDR(0x0200) -#define DANUBE_PPE_MBOX_IGU0_ISRC DANUBE_PPE_REG_ADDR(0x0201) -#define DANUBE_PPE_MBOX_IGU0_ISR DANUBE_PPE_REG_ADDR(0x0202) -#define DANUBE_PPE_MBOX_IGU0_IER DANUBE_PPE_REG_ADDR(0x0203) -#define DANUBE_PPE_MBOX_IGU1_ISRS0 DANUBE_PPE_REG_ADDR(0x0204) -#define DANUBE_PPE_MBOX_IGU1_ISRC0 DANUBE_PPE_REG_ADDR(0x0205) -#define DANUBE_PPE_MBOX_IGU1_ISR0 DANUBE_PPE_REG_ADDR(0x0206) -#define DANUBE_PPE_MBOX_IGU1_IER0 DANUBE_PPE_REG_ADDR(0x0207) -#define DANUBE_PPE_MBOX_IGU1_ISRS1 DANUBE_PPE_REG_ADDR(0x0208) -#define DANUBE_PPE_MBOX_IGU1_ISRC1 DANUBE_PPE_REG_ADDR(0x0209) -#define DANUBE_PPE_MBOX_IGU1_ISR1 DANUBE_PPE_REG_ADDR(0x020A) -#define DANUBE_PPE_MBOX_IGU1_IER1 DANUBE_PPE_REG_ADDR(0x020B) -#define DANUBE_PPE_MBOX_IGU1_ISRS2 DANUBE_PPE_REG_ADDR(0x020C) -#define DANUBE_PPE_MBOX_IGU1_ISRC2 DANUBE_PPE_REG_ADDR(0x020D) -#define DANUBE_PPE_MBOX_IGU1_ISR2 DANUBE_PPE_REG_ADDR(0x020E) -#define DANUBE_PPE_MBOX_IGU1_IER2 DANUBE_PPE_REG_ADDR(0x020F) -#define DANUBE_PPE_MBOX_IGU2_ISRS DANUBE_PPE_REG_ADDR(0x0210) -#define DANUBE_PPE_MBOX_IGU2_ISRC DANUBE_PPE_REG_ADDR(0x0211) -#define DANUBE_PPE_MBOX_IGU2_ISR DANUBE_PPE_REG_ADDR(0x0212) -#define DANUBE_PPE_MBOX_IGU2_IER DANUBE_PPE_REG_ADDR(0x0213) -#define DANUBE_PPE_MBOX_IGU3_ISRS DANUBE_PPE_REG_ADDR(0x0214) -#define DANUBE_PPE_MBOX_IGU3_ISRC DANUBE_PPE_REG_ADDR(0x0215) -#define DANUBE_PPE_MBOX_IGU3_ISR DANUBE_PPE_REG_ADDR(0x0216) -#define DANUBE_PPE_MBOX_IGU3_IER DANUBE_PPE_REG_ADDR(0x0217) -#define DANUBE_PPE_MBOX_IGU4_ISRS DANUBE_PPE_REG_ADDR(0x0218) -#define DANUBE_PPE_MBOX_IGU4_ISRC DANUBE_PPE_REG_ADDR(0x0219) -#define DANUBE_PPE_MBOX_IGU4_ISR DANUBE_PPE_REG_ADDR(0x021A) -#define DANUBE_PPE_MBOX_IGU4_IER DANUBE_PPE_REG_ADDR(0x021B) -/* - * Shared Buffer (SB) Registers - */ -#define DANUBE_PPE_SB_MST_PRI0 DANUBE_PPE_REG_ADDR(0x0300) -#define DANUBE_PPE_SB_MST_PRI1 DANUBE_PPE_REG_ADDR(0x0301) -#define DANUBE_PPE_SB_MST_PRI2 DANUBE_PPE_REG_ADDR(0x0302) -#define DANUBE_PPE_SB_MST_PRI3 DANUBE_PPE_REG_ADDR(0x0303) -#define DANUBE_PPE_SB_MST_PRI4 DANUBE_PPE_REG_ADDR(0x0304) -#define DANUBE_PPE_SB_MST_SEL DANUBE_PPE_REG_ADDR(0x0305) -/* - * RTHA Registers - */ -#define DANUBE_PPE_RFBI_CFG DANUBE_PPE_REG_ADDR(0x0400) -#define DANUBE_PPE_RBA_CFG0 DANUBE_PPE_REG_ADDR(0x0404) -#define DANUBE_PPE_RBA_CFG1 DANUBE_PPE_REG_ADDR(0x0405) -#define DANUBE_PPE_RCA_CFG0 DANUBE_PPE_REG_ADDR(0x0408) -#define DANUBE_PPE_RCA_CFG1 DANUBE_PPE_REG_ADDR(0x0409) -#define DANUBE_PPE_RDES_CFG0 DANUBE_PPE_REG_ADDR(0x040C) -#define DANUBE_PPE_RDES_CFG1 DANUBE_PPE_REG_ADDR(0x040D) -#define DANUBE_PPE_SFSM_STATE0 DANUBE_PPE_REG_ADDR(0x0410) -#define DANUBE_PPE_SFSM_STATE1 DANUBE_PPE_REG_ADDR(0x0411) -#define DANUBE_PPE_SFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0412) -#define DANUBE_PPE_SFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0413) -#define DANUBE_PPE_SFSM_CBA0 DANUBE_PPE_REG_ADDR(0x0414) -#define DANUBE_PPE_SFSM_CBA1 DANUBE_PPE_REG_ADDR(0x0415) -#define DANUBE_PPE_SFSM_CFG0 DANUBE_PPE_REG_ADDR(0x0416) -#define DANUBE_PPE_SFSM_CFG1 DANUBE_PPE_REG_ADDR(0x0417) -#define DANUBE_PPE_SFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x041C) -#define DANUBE_PPE_SFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x041D) -/* - * TTHA Registers - */ -#define DANUBE_PPE_FFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0508) -#define DANUBE_PPE_FFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0509) -#define DANUBE_PPE_FFSM_CFG0 DANUBE_PPE_REG_ADDR(0x050A) -#define DANUBE_PPE_FFSM_CFG1 DANUBE_PPE_REG_ADDR(0x050B) -#define DANUBE_PPE_FFSM_IDLE_HEAD_BC0 DANUBE_PPE_REG_ADDR(0x050E) -#define DANUBE_PPE_FFSM_IDLE_HEAD_BC1 DANUBE_PPE_REG_ADDR(0x050F) -#define DANUBE_PPE_FFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x0514) -#define DANUBE_PPE_FFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x0515) -/* - * ETOP MDIO Registers - */ -#define DANUBE_PPE_ETOP_MDIO_CFG DANUBE_PPE_REG_ADDR(0x0600) -#define DANUBE_PPE_ETOP_MDIO_ACC DANUBE_PPE_REG_ADDR(0x0601) -#define DANUBE_PPE_ETOP_CFG DANUBE_PPE_REG_ADDR(0x0602) -#define DANUBE_PPE_ETOP_IG_VLAN_COS DANUBE_PPE_REG_ADDR(0x0603) -#define DANUBE_PPE_ETOP_IG_DSCP_COS3 DANUBE_PPE_REG_ADDR(0x0604) -#define DANUBE_PPE_ETOP_IG_DSCP_COS2 DANUBE_PPE_REG_ADDR(0x0605) -#define DANUBE_PPE_ETOP_IG_DSCP_COS1 DANUBE_PPE_REG_ADDR(0x0606) -#define DANUBE_PPE_ETOP_IG_DSCP_COS0 DANUBE_PPE_REG_ADDR(0x0607) -#define DANUBE_PPE_ETOP_IG_PLEN_CTRL0 DANUBE_PPE_REG_ADDR(0x0608) -#define DANUBE_PPE_ETOP_IG_PLEN_CTRL1 DANUBE_PPE_REG_ADDR(0x0609) -#define DANUBE_PPE_ETOP_ISR DANUBE_PPE_REG_ADDR(0x060A) -#define DANUBE_PPE_ETOP_IER DANUBE_PPE_REG_ADDR(0x060B) -#define DANUBE_PPE_ETOP_VPID DANUBE_PPE_REG_ADDR(0x060C) -#define DANUBE_PPE_ENET_MAC_CFG DANUBE_PPE_REG_ADDR(0x0610) -#define DANUBE_PPE_ENETS_DBA DANUBE_PPE_REG_ADDR(0x0612) -#define DANUBE_PPE_ENETS_CBA DANUBE_PPE_REG_ADDR(0x0613) -#define DANUBE_PPE_ENETS_CFG DANUBE_PPE_REG_ADDR(0x0614) -#define DANUBE_PPE_ENETS_PGCNT DANUBE_PPE_REG_ADDR(0x0615) -#define DANUBE_PPE_ENETS_PGCNT_DSRC_PP32 (0x00020000) -#define DANUBE_PPE_ENETS_PGCNT_DVAL_SHIFT (9) -#define DANUBE_PPE_ENETS_PGCNT_DCMD (0x00000100) -#define DANUBE_PPE_ENETS_PKTCNT DANUBE_PPE_REG_ADDR(0x0616) -#define DANUBE_PPE_ENETS_PKTCNT_DSRC_PP32 (0x00000200) -#define DANUBE_PPE_ENETS_PKTCNT_DCMD (0x00000100) -#define DANUBE_PPE_ENETS_PKTCNT_UPKT (0x000000FF) -#define DANUBE_PPE_ENETS_BUF_CTRL DANUBE_PPE_REG_ADDR(0x0617) -#define DANUBE_PPE_ENETS_COS_CFG DANUBE_PPE_REG_ADDR(0x0618) -#define DANUBE_PPE_ENETS_IGDROP DANUBE_PPE_REG_ADDR(0x0619) -#define DANUBE_PPE_ENETF_DBA DANUBE_PPE_REG_ADDR(0x0630) -#define DANUBE_PPE_ENETF_CBA DANUBE_PPE_REG_ADDR(0x0631) -#define DANUBE_PPE_ENETF_CFG DANUBE_PPE_REG_ADDR(0x0632) -#define DANUBE_PPE_ENETF_PGCNT DANUBE_PPE_REG_ADDR(0x0633) -#define DANUBE_PPE_ENETF_PGCNT_ISRC_PP32 (0x00020000) -#define DANUBE_PPE_ENETF_PGCNT_IVAL_SHIFT (9) -#define DANUBE_PPE_ENETF_PGCNT_ICMD (0x00000100) -#define DANUBE_PPE_ENETF_PKTCNT DANUBE_PPE_REG_ADDR(0x0634) -#define DANUBE_PPE_ENETF_PKTCNT_ISRC_PP32 (0x00000200) -#define DANUBE_PPE_ENETF_PKTCNT_ICMD (0x00000100) -#define DANUBE_PPE_ENETF_PKTCNT_VPKT (0x000000FF) -#define DANUBE_PPE_ENETF_HFCTRL DANUBE_PPE_REG_ADDR(0x0635) -#define DANUBE_PPE_ENETF_TXCTRL DANUBE_PPE_REG_ADDR(0x0636) -#define DANUBE_PPE_ENETF_VLCOS0 DANUBE_PPE_REG_ADDR(0x0638) -#define DANUBE_PPE_ENETF_VLCOS1 DANUBE_PPE_REG_ADDR(0x0639) -#define DANUBE_PPE_ENETF_VLCOS2 DANUBE_PPE_REG_ADDR(0x063A) -#define DANUBE_PPE_ENETF_VLCOS3 DANUBE_PPE_REG_ADDR(0x063B) -#define DANUBE_PPE_ENETF_EGERR DANUBE_PPE_REG_ADDR(0x063C) -#define DANUBE_PPE_ENETF_EGDROP DANUBE_PPE_REG_ADDR(0x063D) -/* - * DPLUS Registers - */ -#define DANUBE_PPE_DPLUS_TXDB DANUBE_PPE_REG_ADDR(0x0700) -#define DANUBE_PPE_DPLUS_TXCB DANUBE_PPE_REG_ADDR(0x0701) -#define DANUBE_PPE_DPLUS_TXCFG DANUBE_PPE_REG_ADDR(0x0702) -#define DANUBE_PPE_DPLUS_TXPGCNT DANUBE_PPE_REG_ADDR(0x0703) -#define DANUBE_PPE_DPLUS_RXDB DANUBE_PPE_REG_ADDR(0x0710) -#define DANUBE_PPE_DPLUS_RXCB DANUBE_PPE_REG_ADDR(0x0711) -#define DANUBE_PPE_DPLUS_RXCFG DANUBE_PPE_REG_ADDR(0x0712) -#define DANUBE_PPE_DPLUS_RXPGCNT DANUBE_PPE_REG_ADDR(0x0713) -/* - * BMC Registers - */ -#define DANUBE_PPE_BMC_CMD3 DANUBE_PPE_REG_ADDR(0x0800) -#define DANUBE_PPE_BMC_CMD2 DANUBE_PPE_REG_ADDR(0x0801) -#define DANUBE_PPE_BMC_CMD1 DANUBE_PPE_REG_ADDR(0x0802) -#define DANUBE_PPE_BMC_CMD0 DANUBE_PPE_REG_ADDR(0x0803) -#define DANUBE_PPE_BMC_CFG0 DANUBE_PPE_REG_ADDR(0x0804) -#define DANUBE_PPE_BMC_CFG1 DANUBE_PPE_REG_ADDR(0x0805) -#define DANUBE_PPE_BMC_POLY0 DANUBE_PPE_REG_ADDR(0x0806) -#define DANUBE_PPE_BMC_POLY1 DANUBE_PPE_REG_ADDR(0x0807) -#define DANUBE_PPE_BMC_CRC0 DANUBE_PPE_REG_ADDR(0x0808) -#define DANUBE_PPE_BMC_CRC1 DANUBE_PPE_REG_ADDR(0x0809) -/* - * SLL Registers - */ -#define DANUBE_PPE_SLL_CMD1 DANUBE_PPE_REG_ADDR(0x0900) -#define DANUBE_PPE_SLL_CMD0 DANUBE_PPE_REG_ADDR(0x0901) -#define DANUBE_PPE_SLL_KEY0 DANUBE_PPE_REG_ADDR(0x0910) -#define DANUBE_PPE_SLL_KEY1 DANUBE_PPE_REG_ADDR(0x0911) -#define DANUBE_PPE_SLL_KEY2 DANUBE_PPE_REG_ADDR(0x0912) -#define DANUBE_PPE_SLL_KEY3 DANUBE_PPE_REG_ADDR(0x0913) -#define DANUBE_PPE_SLL_KEY4 DANUBE_PPE_REG_ADDR(0x0914) -#define DANUBE_PPE_SLL_KEY5 DANUBE_PPE_REG_ADDR(0x0915) -#define DANUBE_PPE_SLL_RESULT DANUBE_PPE_REG_ADDR(0x0920) -/* - * EMA Registers - */ -#define DANUBE_PPE_EMA_CMD2 DANUBE_PPE_REG_ADDR(0x0A00) -#define DANUBE_PPE_EMA_CMD1 DANUBE_PPE_REG_ADDR(0x0A01) -#define DANUBE_PPE_EMA_CMD0 DANUBE_PPE_REG_ADDR(0x0A02) -#define DANUBE_PPE_EMA_ISR DANUBE_PPE_REG_ADDR(0x0A04) -#define DANUBE_PPE_EMA_IER DANUBE_PPE_REG_ADDR(0x0A05) -#define DANUBE_PPE_EMA_CFG DANUBE_PPE_REG_ADDR(0x0A06) -/* - * UTPS Registers - */ -#define DANUBE_PPE_UTP_TXCA0 DANUBE_PPE_REG_ADDR(0x0B00) -#define DANUBE_PPE_UTP_TXNA0 DANUBE_PPE_REG_ADDR(0x0B01) -#define DANUBE_PPE_UTP_TXCA1 DANUBE_PPE_REG_ADDR(0x0B02) -#define DANUBE_PPE_UTP_TXNA1 DANUBE_PPE_REG_ADDR(0x0B03) -#define DANUBE_PPE_UTP_RXCA0 DANUBE_PPE_REG_ADDR(0x0B10) -#define DANUBE_PPE_UTP_RXNA0 DANUBE_PPE_REG_ADDR(0x0B11) -#define DANUBE_PPE_UTP_RXCA1 DANUBE_PPE_REG_ADDR(0x0B12) -#define DANUBE_PPE_UTP_RXNA1 DANUBE_PPE_REG_ADDR(0x0B13) -#define DANUBE_PPE_UTP_CFG DANUBE_PPE_REG_ADDR(0x0B20) -#define DANUBE_PPE_UTP_ISR DANUBE_PPE_REG_ADDR(0x0B30) -#define DANUBE_PPE_UTP_IER DANUBE_PPE_REG_ADDR(0x0B31) -/* - * QSB Registers - */ -#define DANUBE_PPE_QSB_RELOG DANUBE_PPE_REG_ADDR(0x0C00) -#define DANUBE_PPE_QSB_EMIT0 DANUBE_PPE_REG_ADDR(0x0C01) -#define DANUBE_PPE_QSB_EMIT1 DANUBE_PPE_REG_ADDR(0x0C02) -#define DANUBE_PPE_QSB_ICDV DANUBE_PPE_REG_ADDR(0x0C07) -#define DANUBE_PPE_QSB_SBL DANUBE_PPE_REG_ADDR(0x0C09) -#define DANUBE_PPE_QSB_CFG DANUBE_PPE_REG_ADDR(0x0C0A) -#define DANUBE_PPE_QSB_RTM DANUBE_PPE_REG_ADDR(0x0C0B) -#define DANUBE_PPE_QSB_RTD DANUBE_PPE_REG_ADDR(0x0C0C) -#define DANUBE_PPE_QSB_RAMAC DANUBE_PPE_REG_ADDR(0x0C0D) -#define DANUBE_PPE_QSB_ISTAT DANUBE_PPE_REG_ADDR(0x0C0E) -#define DANUBE_PPE_QSB_IMR DANUBE_PPE_REG_ADDR(0x0C0F) -#define DANUBE_PPE_QSB_SRC DANUBE_PPE_REG_ADDR(0x0C10) -/* - * DSP User Registers - */ -#define DANUBE_PPE_DREG_A_VERSION DANUBE_PPE_REG_ADDR(0x0D00) -#define DANUBE_PPE_DREG_A_CFG DANUBE_PPE_REG_ADDR(0x0D01) -#define DANUBE_PPE_DREG_AT_CTRL DANUBE_PPE_REG_ADDR(0x0D02) -#define DANUBE_PPE_DREG_AR_CTRL DANUBE_PPE_REG_ADDR(0x0D08) -#define DANUBE_PPE_DREG_A_UTPCFG DANUBE_PPE_REG_ADDR(0x0D0E) -#define DANUBE_PPE_DREG_A_STATUS DANUBE_PPE_REG_ADDR(0x0D0F) -#define DANUBE_PPE_DREG_AT_CFG0 DANUBE_PPE_REG_ADDR(0x0D20) -#define DANUBE_PPE_DREG_AT_CFG1 DANUBE_PPE_REG_ADDR(0x0D21) -#define DANUBE_PPE_DREG_FB_SIZE0 DANUBE_PPE_REG_ADDR(0x0D22) -#define DANUBE_PPE_DREG_FB_SIZE1 DANUBE_PPE_REG_ADDR(0x0D23) -#define DANUBE_PPE_DREG_AT_CELL0 DANUBE_PPE_REG_ADDR(0x0D24) -#define DANUBE_PPE_DREG_AT_CELL1 DANUBE_PPE_REG_ADDR(0x0D25) -#define DANUBE_PPE_DREG_AT_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D26) -#define DANUBE_PPE_DREG_AT_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D27) -#define DANUBE_PPE_DREG_AT_IDLE0 DANUBE_PPE_REG_ADDR(0x0D28) -#define DANUBE_PPE_DREG_AT_IDLE1 DANUBE_PPE_REG_ADDR(0x0D29) -#define DANUBE_PPE_DREG_AR_CFG0 DANUBE_PPE_REG_ADDR(0x0D60) -#define DANUBE_PPE_DREG_AR_CFG1 DANUBE_PPE_REG_ADDR(0x0D61) -#define DANUBE_PPE_DREG_AR_FB_START0 DANUBE_PPE_REG_ADDR(0x0D62) -#define DANUBE_PPE_DREG_AR_FB_START1 DANUBE_PPE_REG_ADDR(0x0D63) -#define DANUBE_PPE_DREG_AR_FB_END0 DANUBE_PPE_REG_ADDR(0x0D64) -#define DANUBE_PPE_DREG_AR_FB_END1 DANUBE_PPE_REG_ADDR(0x0D65) -#define DANUBE_PPE_DREG_AR_ATM_STAT0 DANUBE_PPE_REG_ADDR(0x0D66) -#define DANUBE_PPE_DREG_AR_ATM_STAT1 DANUBE_PPE_REG_ADDR(0x0D67) -#define DANUBE_PPE_DREG_AR_CELL0 DANUBE_PPE_REG_ADDR(0x0D68) -#define DANUBE_PPE_DREG_AR_CELL1 DANUBE_PPE_REG_ADDR(0x0D69) -#define DANUBE_PPE_DREG_AR_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6A) -#define DANUBE_PPE_DREG_AR_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6B) -#define DANUBE_PPE_DREG_AR_AIIDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6C) -#define DANUBE_PPE_DREG_AR_AIIDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6D) -#define DANUBE_PPE_DREG_AR_BE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6E) -#define DANUBE_PPE_DREG_AR_BE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6F) -#define DANUBE_PPE_DREG_AR_HEC_CNT0 DANUBE_PPE_REG_ADDR(0x0D70) -#define DANUBE_PPE_DREG_AR_HEC_CNT1 DANUBE_PPE_REG_ADDR(0x0D71) -#define DANUBE_PPE_DREG_AR_CD_CNT0 DANUBE_PPE_REG_ADDR(0x0D72) -#define DANUBE_PPE_DREG_AR_CD_CNT1 DANUBE_PPE_REG_ADDR(0x0D73) -#define DANUBE_PPE_DREG_AR_IDLE0 DANUBE_PPE_REG_ADDR(0x0D74) -#define DANUBE_PPE_DREG_AR_IDLE1 DANUBE_PPE_REG_ADDR(0x0D75) -#define DANUBE_PPE_DREG_AR_DELIN0 DANUBE_PPE_REG_ADDR(0x0D76) -#define DANUBE_PPE_DREG_AR_DELIN1 DANUBE_PPE_REG_ADDR(0x0D77) -#define DANUBE_PPE_DREG_RESV0 DANUBE_PPE_REG_ADDR(0x0D78) -#define DANUBE_PPE_DREG_RESV1 DANUBE_PPE_REG_ADDR(0x0D79) -#define DANUBE_PPE_DREG_RX_MIB_CMD0 DANUBE_PPE_REG_ADDR(0x0D80) -#define DANUBE_PPE_DREG_RX_MIB_CMD1 DANUBE_PPE_REG_ADDR(0x0D81) -#define DANUBE_PPE_DREG_AR_OVDROP_CNT0 DANUBE_PPE_REG_ADDR(0x0D98) -#define DANUBE_PPE_DREG_AR_OVDROP_CNT1 DANUBE_PPE_REG_ADDR(0x0D99) - - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE32_BASE 0xBE180000 -#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) -#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) -#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) -#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) - -/* - * ETOP MDIO Registers - */ -#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) - -#define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -#define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -#define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -#define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -#define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -#define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -#define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) - -#define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -#define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -#define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -#define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -#define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -#define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) - - -/* - * ETOP MDIO Registers - */ -#define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) - - -/* ENET Register */ -#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) - -/*********LED register definition****************/ - -#define DANUBE_LED 0xBE100BB0 -#define DANUBE_LED_CON0 ((volatile u32*)(DANUBE_LED + 0x0000)) -#define DANUBE_LED_CON1 ((volatile u32*)(DANUBE_LED + 0x0004)) -#define DANUBE_LED_CPU0 ((volatile u32*)(DANUBE_LED + 0x0008)) -#define DANUBE_LED_CPU1 ((volatile u32*)(DANUBE_LED + 0x000C)) -#define DANUBE_LED_AR ((volatile u32*)(DANUBE_LED + 0x0010)) - - - - -/***********************************************************************/ -#define DANUBE_REG32(addr) *((volatile u32 *)(addr)) -/***********************************************************************/ -#endif //DANUBE_H diff --git a/package/uboot-lantiq/files/include/configs/arcadyan-common.h b/package/uboot-lantiq/files/include/configs/arcadyan-common.h deleted file mode 100644 index 75f5c38636..0000000000 --- a/package/uboot-lantiq/files/include/configs/arcadyan-common.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the Danube reference board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */ -#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */ -#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */ - -#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */ - -#define CONFIG_USE_DDR_RAM - -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_INIT_RAM_LOCK_MIPS - -#ifdef CONFIG_SYS_RAMBOOT - //#warning CONFIG_SYS_RAMBOOT - #define CONFIG_SKIP_LOWLEVEL_INIT -#else /* CONFIG_SYS_RAMBOOT */ - #define CONFIG_SYS_EBU_BOOT - #define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */ -#endif /* CONFIG_SYS_RAMBOOT */ - -#if 1 -#ifndef CPU_CLOCK_RATE -#define CPU_CLOCK_RATE (ifx_get_cpuclk()) -#endif -#endif - -#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -/* - * Include common defines/options for all Infineon boards - */ -#include "ifx-common.h" - - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ram_addr=0x80500000\0" \ - "kernel_addr=0xb0020000\0" \ - "flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} \0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \ - "console=ttyS1,115200 ethaddr=${ethaddr} " \ - "${mtdparts}\0" \ - "flash_flash=run flashargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \ - "net_flash=run load_kernel flashargs addip addmisc;" \ - "bootm ${ram_addr}\0" \ - "net_nfs=run load_kernel nfsargs addip addmisc;" \ - "bootm ${ram_addr}\0" \ - "load_kernel=tftp ${ram_addr} " \ - "${tftppath}openwrt-ifxmips-uImage\0" \ - "update_uboot=tftp 0x80500000 ${tftppath}u-boot-" CONFIG_ARCADYAN ".bin;era 0xb0000000 +${filesize};" \ - "cp.b 0x80500000 0xb0000000 ${filesize}\0" \ - "update_openwrt=tftp ${ram_addr} " \ - "${tftppath}" CONFIG_ARCADYAN "-squashfs.image;" \ - "era ${kernel_addr} +${filesize};" \ - "cp.b ${ram_addr} ${kernel_addr} ${filesize}\0" - -/* - * Cache Configuration (cpu/chip specific, Danube) - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA - -#define CONFIG_NET_MULTI - -#define CONFIG_IFX_ETOP -//#define CLK_OUT2_25MHZ - -#define CONFIG_MII -#undef CONFIG_CMD_MII - -#define CONFIG_IFX_ASC - -#ifdef CONFIG_USE_ASC0 -#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400 -#else -#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00 -#endif - -#ifdef CONFIG_SYS_RAMBOOT -/* Configuration of EBU: */ -/* starting address from 0xb0000000 */ -/* make the flash available from RAM boot */ -# define CONFIG_EBU_ADDSEL0 0x10000031 -# define CONFIG_EBU_BUSCON0 0x0001D7FF -# define CONFIG_EBU_ADDSEL1 0x14000001 -# define CONFIG_EBU_BUSCON1 0x4041D7FD -#endif - -#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */ - -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.101 -#define CONFIG_GATEWAYIP 192.168.1.254 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_ROOTPATH "/export" - -#ifdef CONFIG_BOOTSTRAP -#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE -#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOOTSTRAP_LZMA -//#define CONFIG_BOOTSTRAP_SERIAL -#endif - - - -#endif /* __CONFIG_H */ diff --git a/package/uboot-lantiq/files/include/configs/arv3527P.h b/package/uboot-lantiq/files/include/configs/arv3527P.h deleted file mode 100644 index f282fc8169..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv3527P.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __CONFIG_H_3527 -#define __CONFIG_H_3527 - -#define CONFIG_ARV3527 1 -#define CONFIG_ARCADYAN "ARV3527P" - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 -#define CONFIG_USE_DDR_PSC_32 1 -#define CONFIG_SYS_PROMPT "ARV3527 => " - -/*#define CONFIG_BUTTON_PORT1 -#define CONFIG_BUTTON_PIN 13 -#define CONFIG_BUTTON_LEVEL 0 -*/ -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv4518PW.h b/package/uboot-lantiq/files/include/configs/arv4518PW.h deleted file mode 100644 index 30bbf6e46b..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv4518PW.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __CONFIG_H_4518 -#define __CONFIG_H_4518 - -#define CONFIG_ARV4518 1 -#define CONFIG_ARCADYAN "ARV4518PW" - -#define CONFIG_SYS_MAX_RAM 64*1024*1024 -#define CONFIG_USE_DDR_PSC_64 1 -#define CONFIG_SYS_PROMPT "ARV4518 => " - -//#define CONFIG_RMII 1 -#define CONFIG_RTL8306_SWITCH 1 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv4519PW.h b/package/uboot-lantiq/files/include/configs/arv4519PW.h deleted file mode 100644 index 1fbc361dc1..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv4519PW.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __CONFIG_H_4519 -#define __CONFIG_H_4519 - -#define CONFIG_ARV4519 1 -#define CONFIG_ARCADYAN "ARV4519PW" - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 -#define CONFIG_USE_DDR_PSC_32 1 -#define CONFIG_SYS_PROMPT "ARV4519 => " - -#define CONFIG_AR8216_SWITCH 1 -#define CONFIG_EBU_GPIO 0 -#define CONFIG_SWITCH_PORT0 -#define CONFIG_SWITCH_PIN 13 -#define CONFIG_BUTTON_PORT1 -#define CONFIG_BUTTON_PIN 12 -#define CONFIG_BUTTON_LEVEL 0 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv4520PW.h b/package/uboot-lantiq/files/include/configs/arv4520PW.h deleted file mode 100644 index d4b130b9d2..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv4520PW.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __CONFIG_H_4520 -#define __CONFIG_H_4520 - -#define CONFIG_ARV4520 1 -#define CONFIG_ARCADYAN "ARV4520PW" - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 -#define CONFIG_USE_DDR_PSC_32 1 -#define CONFIG_SYS_PROMPT "ARV4520 => " -#define CONFIG_RMII 1 -#define CONFIG_ADM6996_SWITCH 1 -#define CONFIG_EBU_GPIO 0x400 - -#define CONFIG_BUTTON_PORT0 -#define CONFIG_BUTTON_PIN 11 -#define CONFIG_BUTTON_LEVEL 0 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv4525PW.h b/package/uboot-lantiq/files/include/configs/arv4525PW.h deleted file mode 100644 index 63e7d32b4d..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv4525PW.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __CONFIG_H_4525 -#define __CONFIG_H_4525 - -#define CONFIG_ARV4525 1 -#define CONFIG_ARCADYAN "ARV4525PW" - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 -#define CONFIG_USE_DDR_PSC_32 1 -#define CONFIG_SYS_PROMPT "ARV4525 => " - -#define CONFIG_BUTTON_PORT1 -#define CONFIG_BUTTON_PIN 13 -#define CONFIG_BUTTON_LEVEL 0 - - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv452CPW.h b/package/uboot-lantiq/files/include/configs/arv452CPW.h deleted file mode 100644 index 579105f97e..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv452CPW.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __CONFIG_H_452C -#define __CONFIG_H_452C - -#define CONFIG_ARV452C 1 -#define CONFIG_ARCADYAN "ARV452CPW" - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 -#define CONFIG_USE_DDR_PSC_32 1 -#define CONFIG_SYS_PROMPT "ARV452c => " -#define CONFIG_RMII 1 -#define CONFIG_RTL8306_SWITCH 1 -#define CONFIG_EBU_GPIO 0xf00 - -#define CONFIG_BUTTON_PORT0 -#define CONFIG_BUTTON_PIN 11 -#define CONFIG_BUTTON_LEVEL 0 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv7518PW.h b/package/uboot-lantiq/files/include/configs/arv7518PW.h deleted file mode 100644 index 5d65dbbf9a..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv7518PW.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __CONFIG_H_7518 -#define __CONFIG_H_7518 - -#define CONFIG_ARV7518 1 -#define CONFIG_ARCADYAN "ARV7518PW" - -#define CONFIG_SYS_MAX_RAM 64*1024*1024 -#define CONFIG_USE_DDR_PSC_64 1 -#define CONFIG_SYS_PROMPT "ARV7518 => " - -//#define CONFIG_RMII 1 -#define CONFIG_AR8216_SWITCH 1 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv7525PW.h b/package/uboot-lantiq/files/include/configs/arv7525PW.h deleted file mode 100644 index ffa59947b8..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv7525PW.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __CONFIG_H_7525PW -#define __CONFIG_H_7525PW - -#define CONFIG_ARV7525 1 -#define CONFIG_ARCADYAN "ARV7525PW" - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 -#define CONFIG_USE_DDR_PSC_32 1 -#define CONFIG_SYS_PROMPT "ARV7525 => " - -#define CONFIG_BUTTON_PORT1 -#define CONFIG_BUTTON_PIN 13 -#define CONFIG_BUTTON_LEVEL 0 - - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv752DPW.h b/package/uboot-lantiq/files/include/configs/arv752DPW.h deleted file mode 100644 index 594ce61e6d..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv752DPW.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __CONFIG_H_752DPW -#define __CONFIG_H_752DPW - -#define CONFIG_ARV752DPW 1 -#define CONFIG_ARCADYAN "ARV752DPW" - -#define CONFIG_SYS_MAX_RAM 64*1024*1024 -#define CONFIG_USE_DDR_PSC_64 1 -#define CONFIG_SYS_PROMPT "ARV752DPW => " - -#define CONFIG_RMII -#define CONFIG_RTL8306G_SWITCH 1 -//#define CONFIG_EBU_GPIO 0x2 -//#define CONFIG_BUTTON_PORT0 -//#define CONFIG_BUTTON_PIN 12 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/arv752DPW22.h b/package/uboot-lantiq/files/include/configs/arv752DPW22.h deleted file mode 100644 index 294628dbe2..0000000000 --- a/package/uboot-lantiq/files/include/configs/arv752DPW22.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __CONFIG_H_752DPW22 -#define __CONFIG_H_752DPW22 - -#define CONFIG_ARV752DPW22 1 -#define CONFIG_ARCADYAN "ARV752DPW22" - -#define CONFIG_SYS_MAX_RAM 64*1024*1024 -#define CONFIG_USE_DDR_PSC_64 1 -#define CONFIG_SYS_PROMPT "ARV752DPW22 => " - -#define CONFIG_AR8216_SWITCH 1 -#define CONFIG_EBU_GPIO 0x2 -#define CONFIG_SWITCH_PORT1 -#define CONFIG_SWITCH_PIN 3 -#define CONFIG_BUTTON_PORT0 -#define CONFIG_BUTTON_PIN 13 -#define CONFIG_BUTTON_LEVEL 0 - -#include "arcadyan-common.h" - -#endif diff --git a/package/uboot-lantiq/files/include/configs/easy50712.h b/package/uboot-lantiq/files/include/configs/easy50712.h deleted file mode 100644 index 8eeb6c06a1..0000000000 --- a/package/uboot-lantiq/files/include/configs/easy50712.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the Danube reference board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ - -#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */ -#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */ -#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */ -#define CONFIG_EASY50712 1 /* on the Danube Reference Board */ - -#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */ - -#define CONFIG_SYS_MAX_RAM 32*1024*1024 - -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_INIT_RAM_LOCK_MIPS -#ifdef CONFIG_SYS_RAMBOOT - //#warning CONFIG_SYS_RAMBOOT - #define CONFIG_SKIP_LOWLEVEL_INIT -#else /* CONFIG_SYS_RAMBOOT */ - - #define CONFIG_SYS_EBU_BOOT - - #ifdef CONFIG_USE_DDR_RAM - /* FIXME: should not need these workarounds */ - #define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */ - #endif - - #define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#if 1 -#ifndef CPU_CLOCK_RATE -#define CPU_CLOCK_RATE (ifx_get_cpuclk()) -#endif -#endif - -#define CONFIG_SYS_PROMPT "DANUBE => " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -/* - * Include common defines/options for all Infineon boards - */ -#include "ifx-common.h" - -/* - * Cache Configuration (cpu/chip specific, Danube) - */ -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA - -#define CONFIG_NET_MULTI -#if 0 -#define CONFIG_M4530_ETH -#define CONFIG_M4530_FPGA -#endif - -#define CONFIG_IFX_ETOP -#define CLK_OUT2_25MHZ -#define CONFIG_EXTRA_SWITCH - -#define CONFIG_RMII /* use interface in RMII mode */ - -#define CONFIG_MII -#define CONFIG_CMD_MII - -#define CONFIG_IFX_ASC - -#ifdef CONFIG_USE_ASC0 -#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400 -#else -#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00 -#endif - -#ifdef CONFIG_SYS_RAMBOOT -/* Configuration of EBU: */ -/* starting address from 0xb0000000 */ -/* make the flash available from RAM boot */ -# define CONFIG_EBU_ADDSEL0 0x10000031 -# define CONFIG_EBU_BUSCON0 0x0001D7FF -#endif - -#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */ - -#endif /* __CONFIG_H */ diff --git a/package/uboot-lantiq/files/include/configs/easy50812.h b/package/uboot-lantiq/files/include/configs/easy50812.h deleted file mode 100644 index c7e96c1bc0..0000000000 --- a/package/uboot-lantiq/files/include/configs/easy50812.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the Danube reference board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ - -#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */ -#define CONFIG_MIPS34KC 1 /* MIPS 34Kc CPU core */ -#define CONFIG_AR9 1 /* an AR9 device */ -#define CONFIG_EASY50812 1 /* on the AR9 reference board */ -#define CONFIG_SYS_MAX_RAM 32*1024*1024 /* 32 MB */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* using CFI flash driver */ - -#define CONFIG_SYS_INIT_RAM_LOCK_MIPS - -/* use PPL1 and fixed values for CPU / DDR and bus speed */ -#define CONFIG_USE_PLL1 -#define CONFIG_CPU_333M_RAM_166M -#define CONFIG_CLASS_II_DDR_PAD - -#ifdef CONFIG_SYS_RAMBOOT - #define CONFIG_SKIP_LOWLEVEL_INIT /* no cache */ -#else - #define CONFIG_SYS_EBU_BOOT - #define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */ -#endif - -#ifndef CPU_CLOCK_RATE -#define CPU_CLOCK_RATE (ifx_get_cpuclk()) -#endif - -#define CONFIG_SYS_PROMPT "AR9 => " /* Monitor Command Prompt */ -#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ - -/* - * Include common defines/options for all Lantiq boards - */ -#include "ifx-common.h" - -/* - * Cache Configuration (cpu/chip specific, ar9) - */ -#define CONFIG_SYS_DCACHE_SIZE (16384) -#define CONFIG_SYS_ICACHE_SIZE (16384) -#define CONFIG_SYS_CACHELINE_SIZE (32) -#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA - -#define CONFIG_NET_MULTI -#if 0 -#define CONFIG_M4530_ETH -#define CONFIG_M4530_FPGA -#endif - -#define CONFIG_IFX_ETOP /* lantiq ethernet cpe interface */ -#define CLK_OUT2_25MHZ -#define CONFIG_EXTRA_SWITCH /* search for external switches like tantos */ -#define CONFIG_RMII /* use interface in RMII mode */ -#define CONFIG_MII -#define CONFIG_CMD_MII /* enable MII command */ - -#define CONFIG_IFX_ASC /* use lantiq ASC driver */ -#ifdef CONFIG_USE_ASC0 -#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400 -#else -#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00 -#endif - -#ifdef CONFIG_SYS_RAMBOOT -/* Configuration of EBU: */ -/* starting address from 0xb0000000 */ -/* make the flash available from RAM boot */ -# define CONFIG_EBU_ADDSEL0 0x10000031 -# define CONFIG_EBU_BUSCON0 0x0001D7FF -#endif - -#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */ - -#endif /* __CONFIG_H */ diff --git a/package/uboot-lantiq/files/include/configs/ifx-common.h b/package/uboot-lantiq/files/include/configs/ifx-common.h deleted file mode 100644 index 4189031b90..0000000000 --- a/package/uboot-lantiq/files/include/configs/ifx-common.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Common configuration options for all AMCC boards - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IFX_COMMON_H -#define __IFX_COMMON_H - -#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#undef CONFIG_PREBOOT - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ram_addr=0x80500000\0" \ - "kernel_addr=0xb0020000\0" \ - "mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \ - "flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} \0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \ - "console=ttyS1,115200 ethaddr=${ethaddr} " \ - "${mtdparts}\0" \ - "flash_flash=run flashargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \ - "net_flash=run load_kernel flashargs addip addmisc;" \ - "bootm ${ram_addr}\0" \ - "net_nfs=run load_kernel nfsargs addip addmisc;" \ - "bootm ${ram_addr}\0" \ - "load_kernel=tftp ${ram_addr} " \ - "${tftppath}openwrt-ifxmips-uImage\0" \ - "update_uboot=tftp 0x80500000 ${tftppath}u-boot.bin;era 0xb0000000 +${filesize};" \ - "cp.b 0x80500000 0xb0000000 ${filesize}\0" \ - "update_openwrt=tftp ${ram_addr} " \ - "${tftppath}openwrt-ifxmips-squashfs.image;" \ - "era ${kernel_addr} +${filesize};" \ - "cp.b ${ram_addr} ${kernel_addr} ${filesize}\0" - -#define CONFIG_BOOTCOMMAND "run flash_flash" - -/* - * TFTP is using fragmented packets -*/ -#define CONFIG_IP_DEFRAG - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_CMD_RUN /* run command in env variable */ -#define CONFIG_CMD_SAVEENV /* saveenv */ -#define CONFIG_CMD_IMI -#undef CONFIG_CMD_PING -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#undef CONFIG_SYS_HUSH_PARSER - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LZMA - -#undef CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifndef CONFIG_SYS_PROMPT -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -#define CONFIG_SYS_MALLOC_LEN 1024*1024 -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2) -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#undef CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE /* include version env variable */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ - -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (140) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xB0000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xB0800000 /* Flash Bank #2 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0010000 -#define CONFIG_ENV_SIZE 0x10000 - -#ifdef CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_SWAP_ADDR -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define FLASH_FIXUP_ADDR_8(addr) ((void*)((ulong)(addr)^2)) -#define FLASH_FIXUP_ADDR_16(addr) ((void*)((ulong)(addr)^2)) - -#endif - -#define CONFIG_NR_DRAM_BANKS 1 - -#ifdef CONFIG_SYS_EBU_BOOT -#ifndef INFINEON_EBU_BOOTCFG -#error Please define INFINEON_EBU_BOOTCFG -#endif -#endif - -#ifdef CONFIG_BOOTSTRAP -#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE -#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOOTSTRAP_LZMA -//#define CONFIG_BOOTSTRAP_SERIAL -#endif - -#endif /* __IFX_COMMON_H */ diff --git a/package/uboot-lantiq/gct b/package/uboot-lantiq/gct deleted file mode 100755 index 4054c15f5f..0000000000 --- a/package/uboot-lantiq/gct +++ /dev/null @@ -1,165 +0,0 @@ -#!/usr/bin/perl - -#use strict; -#use Cwd; -#use Env; - -my $aline; -my $lineid; -my $length; -my $address; -my @bytes; -my $addstr; -my $chsum=0; -my $count=0; -my $firstime=1; -my $i; -my $currentaddr; -my $tmp; -my $holder=""; -my $loadaddr; - -if(@ARGV < 2){ - die("\n Syntax: ./program_SDRAM input1(memory setup) input2(*\.srec) output\n"); -} - -open(INFILE1, "<$ARGV[0]") || die("\ninput1 open fail\n"); -open(INFILE2, "<$ARGV[1]") || die("\ninput2 open fail\n"); -open(OUTFILE, ">$ARGV[2]") || die("\nOutput file open fail\n"); - -$i=0; -while ($line = <INFILE1>){ - if($line=~/\w/){ - if($line!~/[;#\*]/){ - if($i eq 0){ - printf OUTFILE ("33333333"); - } - chomp($line); - $line=~s/\t//; - @array=split(/ +/,$line); - $j=0; - while(@array[$j]!~/\w/){ - $j=$j+1; - } - $addr=@array[$j]; - $regval=@array[$j+1]; - $addr=~s/0x//; - $regval=~s/0x//; - printf OUTFILE ("%08x%08x",hex($addr),hex($regval)); - $i=$i+1; - if($i eq 8){ - $i=0; - printf OUTFILE ("\n"); - } - } - } -} - -while($i lt 8 && $i gt 0){ - printf OUTFILE "00"x8; - $i=$i+1; -} - -if($i eq 8){ - printf OUTFILE ("\n"); -} - -while($aline=<INFILE2>){ - $aline=uc($aline); - chomp($aline); - next if(($aline=~/^S0/) || ($aline=~/^S7/)); - ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline; - $length = hex($length); - $address = hex($address); - $length -=5; - $i=0; - - while($length>0){ - if($firstime==1){ - $addstr = sprintf("%x", $address); - $addstr = "0"x(8-length($addstr)).$addstr; - print OUTFILE $addstr; - addchsum($addstr); - $firstime=0; - $currentaddr=$address; - $loadaddr = $addstr; - } - else{ - if($count==64){ - $addstr = sprintf("%x", $currentaddr); - $addstr = "0"x(8-length($addstr)).$addstr; - print OUTFILE $addstr; - addchsum($addstr); - $count=0; - } - #printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr; - } - if($currentaddr < $address) { - print OUTFILE "00"; - addchsum("00"); - $count++; - $currentaddr++; - } - else { - while($count<64){ - $bytes[$i]=~tr/ABCDEF/abcdef/; - print OUTFILE "$bytes[$i]"; - addchsum($bytes[$i]); - $i++; - $count++; - $currentaddr++; - $length--; - last if($length==0); - } - } - if($count==64){ - print OUTFILE "\n"; - #print OUTFILE "\r"; - } - } -} -if($count != 64){ - $tmp = "00"; - for($i=0;$i<(64-$count);$i++){ - print OUTFILE "00"; - addchsum($tmp); - } - print OUTFILE "\n"; - #print OUTFILE "\r"; -} - - -print OUTFILE "11"x4; -use integer; -$chsum=$chsum & 0xffffffff; -$chsum = sprintf("%X", $chsum); -$chsum = "0"x(8-length($chsum)).$chsum; -$chsum =~tr/ABCDEF/abcdef/; -print OUTFILE $chsum; -print OUTFILE "00"x60; -print OUTFILE "\n"; -#print OUTFILE "\r"; - -print OUTFILE "99"x4; -print OUTFILE $loadaddr; -print OUTFILE "00"x60; -print OUTFILE "\n"; -#print OUTFILE "\r"; - - -close OUTFILE; -#END of Program - - - -sub addchsum{ - my $cc=$_[0]; - $holder=$holder.$cc; - if(length($holder)==8){ - $holder = hex($holder); - $chsum+=$holder; - $holder=""; - } -} -#END - diff --git a/package/uboot-lantiq/patches/000-build-infos.patch b/package/uboot-lantiq/patches/000-build-infos.patch deleted file mode 100644 index bd185d9b5a..0000000000 --- a/package/uboot-lantiq/patches/000-build-infos.patch +++ /dev/null @@ -1,60 +0,0 @@ -Add output like in linux kernel for current compiled file -Used normaly in combination with make option -s - -Like in following example: - -$ make -s V=1 -[CC] tools/img2srec.c -[CC] tools/bmp_logo.c -[CC] examples/hello_world.c - ---- a/config.mk -+++ b/config.mk -@@ -234,17 +234,47 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATF - - ######################################################################### - -+ifndef KBUILD_VERBOSE -+ KBUILD_VERBOSE:=0 -+endif -+ifeq ("$(origin V)", "command line") -+ KBUILD_VERBOSE:=$(V) -+endif -+ifeq (,$(findstring s,$(MAKEFLAGS))) -+ KBUILD_VERBOSE:=0 -+endif -+ -+ifneq ($(KBUILD_VERBOSE),0) -+ define MESSAGE -+ @printf " %s %s/%s\n" $(1) $(2) $(3) -+ endef -+else -+ define MESSAGE -+ endef -+endif -+ - # Allow boards to use custom optimize flags on a per dir/file basis - BCURDIR := $(notdir $(CURDIR)) -+ - $(obj)%.s: %.S -+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<) -+ #echo $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< - $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< - $(obj)%.o: %.S -+ $(call MESSAGE, [AS], $(subst $(SRCTREE)/,,$(CURDIR)),$<) -+ #echo $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c - $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c - $(obj)%.o: %.c -+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<) -+ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c - $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c - $(obj)%.i: %.c -+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<) -+ #echo $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c - $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c - $(obj)%.s: %.c -+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<) -+ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S - $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S - - ######################################################################### diff --git a/package/uboot-lantiq/patches/010-fix-mips-flags.patch b/package/uboot-lantiq/patches/010-fix-mips-flags.patch deleted file mode 100644 index 6dd7d8f569..0000000000 --- a/package/uboot-lantiq/patches/010-fix-mips-flags.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/cpu/mips/config.mk -+++ b/cpu/mips/config.mk -@@ -23,17 +23,19 @@ - v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) - MIPSFLAGS:=$(shell \ - if [ "$v" -lt "14" ]; then \ -- echo "-mcpu=4kc"; \ -+ echo "-mcpu=mips32"; \ - else \ -- echo "-march=4kc -mtune=4kc"; \ -+ echo "-mips32 -march=mips32 -mtune=mips32"; \ - fi) - -+ifndef ENDIANNESS - ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) - ENDIANNESS = -EL - else - ENDIANNESS = -EB - endif -+endif - --MIPSFLAGS += $(ENDIANNESS) -+MIPSFLAGS += $(ENDIANNESS) -fno-schedule-insns -fno-schedule-insns2 - - PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/package/uboot-lantiq/patches/020-mips-enhancements.patch b/package/uboot-lantiq/patches/020-mips-enhancements.patch deleted file mode 100644 index d056467704..0000000000 --- a/package/uboot-lantiq/patches/020-mips-enhancements.patch +++ /dev/null @@ -1,124 +0,0 @@ ---- a/cpu/mips/start.S -+++ b/cpu/mips/start.S -@@ -69,6 +69,9 @@ _start: - #elif defined(CONFIG_PURPLE) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -+#elif defined(CONFIG_SYS_EBU_BOOT) -+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -+ .word 0x00000000 /* phase of the flash */ - #else - RVECENT(romReserved,2) - #endif -@@ -202,7 +205,25 @@ _start: - * 128 * 8 == 1024 == 0x400 - * so this is address R_VEC+0x400 == 0xbfc00400 - */ --#ifdef CONFIG_PURPLE -+#ifndef CONFIG_PURPLE -+ XVECENT(romExcHandle,0x400); /* bfc00400: Int, CauseIV=1 */ -+ RVECENT(romReserved,129); -+ RVECENT(romReserved,130); -+ RVECENT(romReserved,131); -+ RVECENT(romReserved,132); -+ RVECENT(romReserved,133); -+ RVECENT(romReserved,134); -+ RVECENT(romReserved,135); -+ RVECENT(romReserved,136); -+ RVECENT(romReserved,137); -+ RVECENT(romReserved,138); -+ RVECENT(romReserved,139); -+ RVECENT(romReserved,140); -+ RVECENT(romReserved,141); -+ RVECENT(romReserved,142); -+ RVECENT(romReserved,143); -+ XVECENT(romExcHandle,0x480); /* bfc00480: EJTAG debug exception */ -+#else /* CONFIG_PURPLE */ - /* 0xbfc00400 */ - .word 0xdc870000 - .word 0xfca70000 -@@ -228,6 +249,12 @@ _start: - #endif /* CONFIG_PURPLE */ - .align 4 - reset: -+#ifdef CONFIG_SYS_MIPS_MULTI_CPU -+ mfc0 k0, CP0_EBASE -+ and k0, EBASEF_CPUNUM -+ bne k0, zero, ifx_mips_handler_cpux -+ nop -+#endif - - /* Clear watch registers. - */ -@@ -239,6 +266,16 @@ reset: - - setup_c0_status_reset - -+#if defined(CONFIG_MIPS24KEC) || defined(CONFIG_MIPS34KC) -+ /* CONFIG7 register */ -+ /* Erratum "RPS May Cause Incorrect Instruction Execution" -+ * for 24KEC and 34KC */ -+ mfc0 k0, CP0_CONFIG, 7 -+ li k1, MIPS_CONF7_RPS -+ or k0, k1 -+ mtc0 k0, CP0_CONFIG, 7 -+#endif -+ - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE -@@ -270,9 +307,12 @@ reset: - jalr t9 - nop - -+#ifndef CONFIG_SYS_MIPS_CACHE_OPER_MODE -+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NONCOHERENT -+#endif - /* ... and enable them. - */ -- li t0, CONF_CM_CACHABLE_NONCOHERENT -+ li t0, CONFIG_SYS_MIPS_CACHE_OPER_MODE - mtc0 t0, CP0_CONFIG - #endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ - -@@ -419,3 +459,15 @@ romReserved: - - romExcHandle: - b romExcHandle -+ -+ /* Additional handlers. -+ */ -+#ifdef CONFIG_SYS_MIPS_MULTI_CPU -+/* -+ * Stop Slave CPUs -+ */ -+ifx_mips_handler_cpux: -+ wait; -+ b ifx_mips_handler_cpux; -+ nop; -+#endif ---- a/include/asm-mips/mipsregs.h -+++ b/include/asm-mips/mipsregs.h -@@ -57,6 +57,7 @@ - #define CP0_CAUSE $13 - #define CP0_EPC $14 - #define CP0_PRID $15 -+#define CP0_EBASE $15,1 - #define CP0_CONFIG $16 - #define CP0_LLADDR $17 - #define CP0_WATCHLO $18 -@@ -395,6 +396,14 @@ - #define CAUSEF_BD (_ULCAST_(1) << 31) - - /* -+ * Bits in the coprocessor 0 EBase register -+ */ -+#define EBASEB_CPUNUM 0 -+#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM) -+#define EBASEB_EXPBASE 12 -+#define EBASEF_EXPBASE (0x3ffff << EBASEB_EXPBASE) -+ -+/* - * Bits in the coprocessor 0 config register. - */ - /* Generic bits. */ diff --git a/package/uboot-lantiq/patches/030-cfi-addr-fixup.patch b/package/uboot-lantiq/patches/030-cfi-addr-fixup.patch deleted file mode 100644 index 8f95da1f75..0000000000 --- a/package/uboot-lantiq/patches/030-cfi-addr-fixup.patch +++ /dev/null @@ -1,225 +0,0 @@ ---- a/drivers/mtd/cfi_flash.c -+++ b/drivers/mtd/cfi_flash.c -@@ -85,6 +85,22 @@ flash_info_t flash_info[CFI_MAX_FLASH_BA - #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT - #endif - -+/* -+ * Check if address fixup macros are defined, define defaults otherwise -+ */ -+#ifndef FLASH_FIXUP_ADDR_8 -+#define FLASH_FIXUP_ADDR_8(addr) (addr) -+#endif -+#ifndef FLASH_FIXUP_ADDR_16 -+#define FLASH_FIXUP_ADDR_16(addr) (addr) -+#endif -+#ifndef FLASH_FIXUP_ADDR_32 -+#define FLASH_FIXUP_ADDR_32(addr) (addr) -+#endif -+#ifndef FLASH_FIXUP_ADDR_64 -+#define FLASH_FIXUP_ADDR_64(addr) (addr) -+#endif -+ - static void __flash_write8(u8 value, void *addr) - { - __raw_writeb(value, addr); -@@ -264,9 +280,9 @@ static inline uchar flash_read_uchar (fl - - cp = flash_map (info, 0, offset); - #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) -- retval = flash_read8(cp); -+ retval = flash_read8(FLASH_FIXUP_ADDR_8(cp)); - #else -- retval = flash_read8(cp + info->portwidth - 1); -+ retval = flash_read8(FLASH_FIXUP_ADDR_8(cp) + info->portwidth - 1); - #endif - flash_unmap (info, 0, offset, cp); - return retval; -@@ -280,7 +296,7 @@ static inline ushort flash_read_word (fl - ushort *addr, retval; - - addr = flash_map (info, 0, offset); -- retval = flash_read16 (addr); -+ retval = flash_read16 (FLASH_FIXUP_ADDR_16(addr)); - flash_unmap (info, 0, offset, addr); - return retval; - } -@@ -305,19 +321,28 @@ static ulong flash_read_long (flash_info - debug ("long addr is at %p info->portwidth = %d\n", addr, - info->portwidth); - for (x = 0; x < 4 * info->portwidth; x++) { -- debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); -+ debug ("addr[%x] = 0x%x\n", x, -+ flash_read8(FLASH_FIXUP_ADDR_32(addr) + x)); - } - #endif - #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) -- retval = ((flash_read8(addr) << 16) | -- (flash_read8(addr + info->portwidth) << 24) | -- (flash_read8(addr + 2 * info->portwidth)) | -- (flash_read8(addr + 3 * info->portwidth) << 8)); -+ retval = ((flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr) << 16) | -+ (flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + info->portwidth)) << 24) | -+ (flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + 2 * info->portwidth))) | -+ (flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + 3 * info->portwidth)) << 8)); - #else -- retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | -- (flash_read8(addr + info->portwidth - 1) << 16) | -- (flash_read8(addr + 4 * info->portwidth - 1) << 8) | -- (flash_read8(addr + 3 * info->portwidth - 1))); -+ retval = ((flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + 2 * info->portwidth - 1)) << 24) | -+ (flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + info->portwidth - 1)) << 16) | -+ (flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + 4 * info->portwidth - 1)) << 8) | -+ (flash_read8(FLASH_FIXUP_ADDR_8 -+ (addr + 3 * info->portwidth - 1)))); - #endif - flash_unmap(info, sect, offset, addr); - -@@ -338,21 +363,22 @@ void flash_write_cmd (flash_info_t * inf - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: -- debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, -- cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); -- flash_write8(cword.c, addr); -+ debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", -+ FLASH_FIXUP_ADDR_8(addr), cmd, cword.c, -+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH); -+ flash_write8(cword.c, FLASH_FIXUP_ADDR_8(addr)); - break; - case FLASH_CFI_16BIT: -- debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, -- cmd, cword.w, -+ debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", -+ FLASH_FIXUP_ADDR_16(addr), cmd, cword.w, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); -- flash_write16(cword.w, addr); -+ flash_write16(cword.w, FLASH_FIXUP_ADDR_16(addr)); - break; - case FLASH_CFI_32BIT: -- debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, -- cmd, cword.l, -+ debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", -+ FLASH_FIXUP_ADDR_32(addr), cmd, cword.l, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); -- flash_write32(cword.l, addr); -+ flash_write32(cword.l, FLASH_FIXUP_ADDR_32(addr)); - break; - case FLASH_CFI_64BIT: - #ifdef DEBUG -@@ -362,11 +388,11 @@ void flash_write_cmd (flash_info_t * inf - print_longlong (str, cword.ll); - - debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", -- addr, cmd, str, -+ FLASH_FIXUP_ADDR_64(addr), cmd, str, - info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - } - #endif -- flash_write64(cword.ll, addr); -+ flash_write64(cword.ll, FLASH_FIXUP_ADDR_64(addr)); - break; - } - -@@ -397,16 +423,19 @@ static int flash_isequal (flash_info_t * - debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); - switch (info->portwidth) { - case FLASH_CFI_8BIT: -- debug ("is= %x %x\n", flash_read8(addr), cword.c); -- retval = (flash_read8(addr) == cword.c); -+ debug ("is= %x %x\n", -+ flash_read8(FLASH_FIXUP_ADDR_8(addr)), cword.c); -+ retval = (flash_read8(FLASH_FIXUP_ADDR_8(addr)) == cword.c); - break; - case FLASH_CFI_16BIT: -- debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); -- retval = (flash_read16(addr) == cword.w); -+ debug ("is= %4.4x %4.4x\n", -+ flash_read16(FLASH_FIXUP_ADDR_16(addr)), cword.w); -+ retval = (flash_read16(FLASH_FIXUP_ADDR_16(addr)) == cword.w); - break; - case FLASH_CFI_32BIT: -- debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); -- retval = (flash_read32(addr) == cword.l); -+ debug ("is= %8.8x %8.8lx\n", -+ flash_read32(FLASH_FIXUP_ADDR_32(addr)), cword.l); -+ retval = (flash_read32(FLASH_FIXUP_ADDR_32(addr)) == cword.l); - break; - case FLASH_CFI_64BIT: - #ifdef DEBUG -@@ -414,12 +443,13 @@ static int flash_isequal (flash_info_t * - char str1[20]; - char str2[20]; - -- print_longlong (str1, flash_read64(addr)); -+ print_longlong (str1, flash_read64(FLASH_FIXUP_ADDR_64 -+ (addr))); - print_longlong (str2, cword.ll); - debug ("is= %s %s\n", str1, str2); - } - #endif -- retval = (flash_read64(addr) == cword.ll); -+ retval = (flash_read64(FLASH_FIXUP_ADDR_64(addr)) == cword.ll); - break; - default: - retval = 0; -@@ -443,16 +473,20 @@ static int flash_isset (flash_info_t * i - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: -- retval = ((flash_read8(addr) & cword.c) == cword.c); -+ retval = ((flash_read8(FLASH_FIXUP_ADDR_8(addr)) -+ & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: -- retval = ((flash_read16(addr) & cword.w) == cword.w); -+ retval = ((flash_read16(FLASH_FIXUP_ADDR_16(addr)) -+ & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: -- retval = ((flash_read32(addr) & cword.l) == cword.l); -+ retval = ((flash_read32(FLASH_FIXUP_ADDR_32(addr)) -+ & cword.l) == cword.l); - break; - case FLASH_CFI_64BIT: -- retval = ((flash_read64(addr) & cword.ll) == cword.ll); -+ retval = ((flash_read64(FLASH_FIXUP_ADDR_64(addr)) -+ & cword.ll) == cword.ll); - break; - default: - retval = 0; -@@ -476,17 +510,22 @@ static int flash_toggle (flash_info_t * - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: -- retval = flash_read8(addr) != flash_read8(addr); -+ retval = flash_read8(FLASH_FIXUP_ADDR_8(addr)) != -+ flash_read8(FLASH_FIXUP_ADDR_8(addr)); - break; - case FLASH_CFI_16BIT: -- retval = flash_read16(addr) != flash_read16(addr); -+ retval = flash_read16(FLASH_FIXUP_ADDR_16(addr)) != -+ flash_read16(FLASH_FIXUP_ADDR_16(addr)); - break; - case FLASH_CFI_32BIT: -- retval = flash_read32(addr) != flash_read32(addr); -+ retval = flash_read32(FLASH_FIXUP_ADDR_32(addr)) != -+ flash_read32(FLASH_FIXUP_ADDR_32(addr)); - break; - case FLASH_CFI_64BIT: -- retval = ( (flash_read32( addr ) != flash_read32( addr )) || -- (flash_read32(addr+4) != flash_read32(addr+4)) ); -+ retval = ( (flash_read32(FLASH_FIXUP_ADDR_64( addr )) != -+ flash_read32(FLASH_FIXUP_ADDR_64( addr ))) || -+ (flash_read32(FLASH_FIXUP_ADDR_64(addr+4)) != -+ flash_read32(FLASH_FIXUP_ADDR_64(addr+4))) ); - break; - default: - retval = 0; diff --git a/package/uboot-lantiq/patches/040-compile.patch b/package/uboot-lantiq/patches/040-compile.patch deleted file mode 100644 index c00230069d..0000000000 --- a/package/uboot-lantiq/patches/040-compile.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/common/env_common.c -+++ b/common/env_common.c -@@ -26,6 +26,7 @@ - - #include <common.h> - #include <command.h> -+#include <configs/ifx-common.h> - #include <environment.h> - #include <linux/stddef.h> - #include <malloc.h> ---- a/common/env_embedded.c -+++ b/common/env_embedded.c -@@ -27,6 +27,7 @@ - #define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */ - #include <config.h> - #undef __ASSEMBLY__ -+#include <configs/ifx-common.h> - #include <environment.h> - - /* diff --git a/package/uboot-lantiq/patches/050-portability.patch b/package/uboot-lantiq/patches/050-portability.patch deleted file mode 100644 index ae38ad68ea..0000000000 --- a/package/uboot-lantiq/patches/050-portability.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/tools/kwbimage.c -+++ b/tools/kwbimage.c -@@ -206,6 +206,28 @@ INVL_DATA: - exit (EXIT_FAILURE); - } - -+#ifndef __GLIBC__ -+static ssize_t -+getline(char **line, size_t *len, FILE *fd) -+{ -+ char *tmp; -+ int tmplen; -+ -+ tmp = fgetln(fd, &tmplen); -+ if (!tmp) -+ return -1; -+ -+ if (!*line || tmplen > *len) { -+ *len = tmplen + 1; -+ *line = realloc(*line, *len); -+ } -+ -+ strncpy(*line, tmp, tmplen); -+ line[tmplen] = 0; -+ return tmplen; -+} -+#endif -+ - /* - * this function sets the kwbimage header by- - * 1. Abstracting input command line arguments data diff --git a/package/uboot-lantiq/patches/100-ifx_targets.patch b/package/uboot-lantiq/patches/100-ifx_targets.patch deleted file mode 100644 index dcd931cb8d..0000000000 --- a/package/uboot-lantiq/patches/100-ifx_targets.patch +++ /dev/null @@ -1,135 +0,0 @@ ---- a/MAKEALL -+++ b/MAKEALL -@@ -730,6 +730,12 @@ - ## MIPS Systems (default = big endian) - ######################################################################### - -+LIST_ifxcpe=" \ -+ easy50712 \ -+ easy50712_DDR166M \ -+ easy50712_DDR166M_ramboot \ -+" -+ - LIST_mips4kc=" \ - incaip \ - qemu_mips \ -@@ -761,6 +767,7 @@ - " - - LIST_mips=" \ -+ ${LIST_ifxcpe} \ - ${LIST_mips4kc} \ - ${LIST_mips5kc} \ - ${LIST_au1xx0} \ ---- a/Makefile -+++ b/Makefile -@@ -447,7 +447,7 @@ - set -e ; \ - : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \ -- sed -n -f tools/scripts/define2mk.sed > $@.tmp && \ -+ sed -n -f tools/scripts/define2mk.sed |sort > $@.tmp && \ - mv $@.tmp $@ - - ######################################################################### -@@ -3370,7 +3370,7 @@ - { echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h ; \ - $(XECHO) "... with 150MHz system clock" ; \ - } -- @$(MKCONFIG) -a $(call xtract_incaip,$@) mips mips incaip -+ @$(MKCONFIG) -a $(call xtract_incaip,$@) mips mips incaip infineon - - tb0229_config: unconfig - @$(MKCONFIG) $(@:_config=) mips mips tb0229 -@@ -3411,6 +3411,53 @@ - @$(MKCONFIG) -a vct mips mips vct micronas - - ######################################################################### -+## MIPS32 ifxcpe -+######################################################################### -+ -+easy50712%config : unconfig -+ @mkdir -p $(obj)include -+ @mkdir -p $(obj)board/infineon/easy50712 -+ @[ -z "$(findstring ramboot,$@)" ] || \ -+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/infineon/easy50712/config.tmp ; \ -+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \ -+ $(XECHO) "... with ramboot configuration" ; \ -+ } -+ @if [ "$(findstring _DDR,$@)" -a -z "$(findstring ramboot,$@)" ] ; then \ -+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \ -+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \ -+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \ -+ case "$${DDR}" in \ -+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \ -+ $(XECHO) "... with DDR RAM config $${DDR}" ; \ -+ echo "#define CONFIG_USE_DDR_RAM_CFG_$${DDR}" >>$(obj)include/config.h ;; \ -+ *) $(XECHO) "... DDR RAM config \\\"$${DDR}\\\" unknown, use default"; \ -+ esac; \ -+ fi -+ @$(MKCONFIG) -a $(word 1,$(subst _, ,$@)) mips mips easy50712 infineon danube -+ -+easy50812%config : unconfig -+ @mkdir -p $(obj)include -+ @mkdir -p $(obj)board/infineon/easy50812 -+ @[ -z "$(findstring ramboot,$@)" ] || \ -+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/infineon/easy50812/config.tmp ; \ -+ echo "CONFIG_BOOTSTRAP = 0" >>$(obj)board/infineon/easy50812/config.tmp ; \ -+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \ -+ $(XECHO) "... with ramboot configuration" ; \ -+ } -+ @if [ "$(findstring _DDR,$@)" -a -z "$(findstring ramboot,$@)" ] ; then \ -+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \ -+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \ -+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \ -+ case "$${DDR}" in \ -+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \ -+ $(XECHO) "... with DDR RAM config $${DDR}" ; \ -+ echo "#define CONFIG_USE_DDR_RAM_CFG_$${DDR}" >>$(obj)include/config.h ;; \ -+ *) $(XECHO) "... DDR RAM config \\\"$${DDR}\\\" unknown, use default"; \ -+ esac; \ -+ fi -+ @$(MKCONFIG) -a $(word 1,$(subst _, ,$@)) mips mips easy50812 infineon ar9 -+ -+######################################################################### - ## MIPS32 AU1X00 - ######################################################################### - ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -43,6 +43,7 @@ - COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o - COBJS-$(CONFIG_FTMAC100) += ftmac100.o - COBJS-$(CONFIG_GRETH) += greth.o -+COBJS-$(CONFIG_IFX_ETOP) += ifx_etop.o - COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o - COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o - COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o ---- a/drivers/serial/Makefile -+++ b/drivers/serial/Makefile -@@ -28,6 +28,7 @@ - COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o - COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o - COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o -+COBJS-$(CONFIG_IFX_ASC) += ifx_asc.o - COBJS-$(CONFIG_MCFUART) += mcfuart.o - COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o - COBJS-$(CONFIG_SYS_NS16550) += ns16550.o ---- a/include/netdev.h -+++ b/include/netdev.h -@@ -57,6 +57,7 @@ - int ftmac100_initialize(bd_t *bits); - int greth_initialize(bd_t *bis); - void gt6426x_eth_initialize(bd_t *bis); -+int ifx_etop_initialize(bd_t *bis); - int inca_switch_initialize(bd_t *bis); - int kirkwood_egiga_initialize(bd_t *bis); - int lan91c96_initialize(u8 dev_num, int base_addr); -@@ -85,6 +86,7 @@ - int uli526x_initialize(bd_t *bis); - int sh_eth_initialize(bd_t *bis); - int dm9000_initialize(bd_t *bis); -+int lq_eth_initialize(bd_t * bis); - - /* Boards with PCI network controllers can call this from their board_eth_init() - * function to initialize whatever's on board. diff --git a/package/uboot-lantiq/patches/200-httpd.patch b/package/uboot-lantiq/patches/200-httpd.patch deleted file mode 100644 index b0ab3b6afd..0000000000 --- a/package/uboot-lantiq/patches/200-httpd.patch +++ /dev/null @@ -1,6164 +0,0 @@ ---- a/common/cmd_net.c -+++ b/common/cmd_net.c -@@ -43,6 +43,18 @@ U_BOOT_CMD( - "[loadAddress] [[hostIPaddr:]bootfilename]" - ); - -+#if defined(CONFIG_CMD_HTTPD) -+int do_httpd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -+{ -+ return NetLoopHttpd(); -+} -+ -+U_BOOT_CMD( -+ httpd, 1, 1, do_httpd, -+ "httpd\t- start webserver", "" -+); -+#endif -+ - int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) - { - return netboot_common (TFTP, cmdtp, argc, argv); ---- /dev/null -+++ b/include/httpd.h -@@ -0,0 +1,17 @@ -+#ifndef _UIP_HTTPD_H__ -+#define _UIP_HTTPD_H__ -+ -+void HttpdStart (void); -+void HttpdHandler (void); -+ -+/* board specific implementation */ -+extern int do_http_upgrade(const unsigned char *data, const ulong size); -+ -+#define HTTP_PROGRESS_START 0 -+#define HTTP_PROGRESS_TIMEOUT 1 -+#define HTTP_PROGRESS_UPLOAD_READY 2 -+#define HTTP_PROGRESS_UGRADE_READY 3 -+#define HTTP_PROGRESS_UGRADE_FAILED 4 -+extern int do_http_progress(const int state); -+ -+#endif ---- a/include/net.h -+++ b/include/net.h -@@ -383,7 +383,8 @@ extern int NetTimeOffset; /* offset ti - - /* Initialize the network adapter */ - extern int NetLoop(proto_t); -- -+extern int NetLoopHttpd(void); -+extern void NetSendHttpd(void); - /* Shutdown adapters and cleanup */ - extern void NetStop(void); - ---- a/net/Makefile -+++ b/net/Makefile -@@ -26,6 +26,8 @@ include $(TOPDIR)/config.mk - # CFLAGS += -DDEBUG - - LIB = $(obj)libnet.a -+UIPDIR = uip-0.9 -+$(shell mkdir -p $(obj)$(UIPDIR)) - - COBJS-$(CONFIG_CMD_NET) += bootp.o - COBJS-$(CONFIG_CMD_DNS) += dns.o -@@ -36,6 +40,8 @@ COBJS-$(CONFIG_CMD_NET) += rarp.o - COBJS-$(CONFIG_CMD_SNTP) += sntp.o - COBJS-$(CONFIG_CMD_NET) += tftp.o - -+COBJS-$(CONFIG_CMD_HTTPD) += httpd.o $(UIPDIR)/fs.o $(UIPDIR)/httpd.o $(UIPDIR)/uip_arp.o $(UIPDIR)/uip_arch.o $(UIPDIR)/uip.o -+ - COBJS := $(COBJS-y) - SRCS := $(COBJS:.o=.c) - OBJS := $(addprefix $(obj),$(COBJS)) ---- /dev/null -+++ b/net/httpd.c -@@ -0,0 +1,52 @@ -+/* -+ * Copyright 1994, 1995, 2000 Neil Russell. -+ * (See License) -+ * Copyright 2000, 2001 DENX Software Engineering, Wolfgang Denk, wd@denx.de -+ */ -+ -+#include <common.h> -+#include <command.h> -+#include <net.h> -+#include "uip-0.9/uipopt.h" -+#include "uip-0.9/uip.h" -+#include "uip-0.9/uip_arp.h" -+ -+ -+#if defined(CONFIG_CMD_HTTPD) -+ -+#define TIMEOUT 5 -+ -+static int arptimer = 0; -+ -+void -+HttpdHandler (void) -+{ -+ int i; -+ for(i = 0; i < UIP_CONNS; i++) { -+ uip_periodic(i); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ NetSendHttpd(); -+ } -+ } -+ if(++arptimer == 20) { -+ uip_arp_timer(); -+ arptimer = 0; -+ } -+} -+ -+static void -+HttpdTimeout (void) -+{ -+ puts ("T "); -+ NetSetTimeout (TIMEOUT * 1000, HttpdTimeout); -+} -+ -+void -+HttpdStart (void) -+{ -+ uip_init(); -+ httpd_init(); -+} -+ -+#endif ---- a/net/net.c -+++ b/net/net.c -@@ -95,6 +95,19 @@ - #if defined(CONFIG_CMD_DNS) - #include "dns.h" - #endif -+#if defined(CONFIG_CMD_HTTPD) -+#include "httpd.h" -+#include "uip-0.9/uipopt.h" -+#include "uip-0.9/uip.h" -+#include "uip-0.9/uip_arp.h" -+static int https_running = 0; -+int httpd_upload_complete = 0; -+unsigned char *httpd_upload_data = 0; -+extern int upload_running; -+void NetReceiveHttpd(volatile uchar * inpkt, int len); -+void NetSendHttpd(void); -+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -+#endif - - DECLARE_GLOBAL_DATA_PTR; - -@@ -1308,6 +1321,13 @@ NetReceive(volatile uchar * inpkt, int l - - debug("packet received\n"); - -+#if defined(CONFIG_CMD_HTTPD) -+ if(https_running) { -+ NetReceiveHttpd(inpkt, len); -+ return; -+ } -+#endif -+ - NetRxPacket = inpkt; - NetRxPacketLen = len; - et = (Ethernet_t *)inpkt; -@@ -1922,3 +1942,162 @@ ushort getenv_VLAN(char *var) - { - return (string_to_VLAN(getenv(var))); - } -+ -+#if defined(CONFIG_CMD_HTTPD) -+ -+void -+NetSendHttpd(void) -+{ -+ volatile uchar *tmpbuf = NetTxPacket; -+ int i; -+ -+ for(i = 0; i < 40 + UIP_LLH_LEN; i++) { -+ tmpbuf[i] = uip_buf[i]; -+ } -+ -+ for(; i < uip_len; i++) { -+ tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; -+ } -+ eth_send(NetTxPacket, uip_len); -+} -+ -+#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) -+ -+void -+NetReceiveHttpd(volatile uchar * inpkt, int len) -+{ -+ memcpy(uip_buf, inpkt, len); -+ uip_len = len; -+ if(BUF->type == htons(UIP_ETHTYPE_IP)) { -+ uip_arp_ipin(); -+ uip_input(); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ NetSendHttpd(); -+ } -+ } else if(BUF->type == htons(UIP_ETHTYPE_ARP)) { -+ uip_arp_arpin(); -+ if(uip_len > 0) { -+ NetSendHttpd(); -+ } -+ } -+} -+ -+int -+NetLoopHttpd(void) -+{ -+ unsigned long long tout = 0; -+ bd_t *bd = gd->bd; -+ unsigned short int ip[2]; -+ -+#ifdef CONFIG_NET_MULTI -+ NetRestarted = 0; -+ NetDevExists = 0; -+#endif -+ -+ /* XXX problem with bss workaround */ -+ NetArpWaitPacketMAC = NULL; -+ NetArpWaitTxPacket = NULL; -+ NetArpWaitPacketIP = 0; -+ NetArpWaitReplyIP = 0; -+ NetArpWaitTxPacket = NULL; -+ NetTxPacket = NULL; -+ NetTryCount = 1; -+ -+ if (!NetTxPacket) { -+ int i; -+ /* -+ * Setup packet buffers, aligned correctly. -+ */ -+ NetTxPacket = &PktBuf[0] + (PKTALIGN - 1); -+ NetTxPacket -= (ulong)NetTxPacket % PKTALIGN; -+ for (i = 0; i < PKTBUFSRX; i++) { -+ NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN; -+ } -+ } -+ -+ if (!NetArpWaitTxPacket) { -+ NetArpWaitTxPacket = &NetArpWaitPacketBuf[0] + (PKTALIGN - 1); -+ NetArpWaitTxPacket -= (ulong)NetArpWaitTxPacket % PKTALIGN; -+ NetArpWaitTxPacketSize = 0; -+ } -+ -+restart: -+ -+ eth_halt(); -+#ifdef CONFIG_NET_MULTI -+ eth_set_current(); -+#endif -+ if (eth_init(bd) < 0) { -+ eth_halt(); -+ return(-1); -+ } -+ -+#ifdef CONFIG_NET_MULTI -+ memcpy (NetOurEther, eth_get_dev()->enetaddr, 6); -+#else -+ eth_getenv_enetaddr("ethaddr", NetOurEther); -+#endif -+ -+ NetCopyIP(&NetOurIP, &bd->bi_ip_addr); -+ NetOurGatewayIP = getenv_IPaddr ("gatewayip"); -+ NetOurSubnetMask= getenv_IPaddr ("netmask"); -+ NetOurVLAN = getenv_VLAN("vlan"); -+ NetOurNativeVLAN = getenv_VLAN("nvlan"); -+ -+ printf("starting httpd server from server %ld.%ld.%ld.%ld\n", -+ (bd->bi_ip_addr & 0xff000000) >> 24, -+ (bd->bi_ip_addr & 0x00ff0000) >> 16, -+ (bd->bi_ip_addr & 0x0000ff00) >> 8, -+ (bd->bi_ip_addr & 0x000000ff)); -+ -+ HttpdStart(); -+ -+ ip[0] = ((bd->bi_ip_addr & 0xffff0000) >> 16); -+ ip[1] = (bd->bi_ip_addr & 0x0000ffff); -+ uip_sethostaddr(ip); -+ -+ do_http_progress(HTTP_PROGRESS_START); -+ -+ https_running = 1; -+ for (;;) { -+ unsigned long long t1; -+ WATCHDOG_RESET(); -+ if(eth_rx() > 0) { -+ HttpdHandler(); -+ } else { -+ t1 = get_ticks(); -+ if(t1 - tout > 1000) { -+ do_http_progress(HTTP_PROGRESS_TIMEOUT); -+ tout = t1; -+ } -+ } -+ if(!httpd_upload_complete) -+ continue; -+ printf("Bytes transferred = %ld (%lx hex)\n", -+ NetBootFileXferSize, -+ NetBootFileXferSize); -+ eth_halt(); -+ do_http_progress(HTTP_PROGRESS_UPLOAD_READY); -+ if(do_http_upgrade(&httpd_upload_data[0], NetBootFileXferSize) == 0) { -+ do_http_progress(HTTP_PROGRESS_UGRADE_READY); -+ udelay(1000 * 10); -+ do_reset (0,0,0,0); -+ return 0; -+ } -+ break; -+ } -+ https_running = 0; -+ NetBootFileXferSize = 0; -+ httpd_upload_complete = 0; -+ upload_running = 0; -+// free(httpd_upload_data); -+ -+ do_http_progress(HTTP_PROGRESS_UGRADE_FAILED); -+ -+ goto restart; -+ -+ return -1; -+} -+ -+#endif ---- /dev/null -+++ b/net/uip-0.9/Makefile -@@ -0,0 +1,54 @@ -+# Copyright (c) 2001, Adam Dunkels. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# 1. Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# 2. Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in the -+# documentation and/or other materials provided with the distribution. -+# 3. All advertising materials mentioning features or use of this software -+# must display the following acknowledgement: -+# This product includes software developed by Adam Dunkels. -+# 4. The name of the author may not be used to endorse or promote -+# products derived from this software without specific prior -+# written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# This file is part of the uIP TCP/IP stack. -+# -+# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $ -+# -+ -+CC=gcc -+CFLAGS=-Wall -fpack-struct -DDUMP=0 -+ -+all: uip -+ -+uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o -+ $(CC) $(CFLAGS) $(LDFLAGS) $^ -o $@ -+ -+%.o: %.c -+ $(CC) $(CFLAGS) -c $^ -o $@ -+ -+clean: -+ rm -f *.o *~ *core uip -+ -+ -+ -+ -+ -+ ---- /dev/null -+++ b/net/uip-0.9/fs.c -@@ -0,0 +1,154 @@ -+/** -+ * \addtogroup httpd -+ * @{ -+ */ -+ -+/** -+ * \file -+ * HTTP server read-only file system code. -+ * \author Adam Dunkels <adam@dunkels.com> -+ * -+ * A simple read-only filesystem. -+ */ -+ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ -+ */ -+ -+#include "uip.h" -+#include "httpd.h" -+#include "fs.h" -+#include "fsdata.h" -+ -+#include "fsdata.c" -+ -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+static u16_t count[FS_NUMFILES]; -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+ -+/*-----------------------------------------------------------------------------------*/ -+static u8_t -+fs_strcmp(const char *str1, const char *str2) -+{ -+ u8_t i; -+ i = 0; -+ loop: -+ -+ if(str2[i] == 0 || -+ str1[i] == '\r' || -+ str1[i] == '\n') { -+ return 0; -+ } -+ -+ if(str1[i] != str2[i]) { -+ return 1; -+ } -+ -+ -+ ++i; -+ goto loop; -+} -+/*-----------------------------------------------------------------------------------*/ -+int -+fs_open(const char *name, struct fs_file *file) -+{ -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+ u16_t i = 0; -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+ struct fsdata_file_noconst *f; -+ -+ for(f = (struct fsdata_file_noconst *)FS_ROOT; -+ f != NULL; -+ f = (struct fsdata_file_noconst *)f->next) { -+ -+ if(fs_strcmp(name, f->name) == 0) { -+ file->data = f->data; -+ file->len = f->len; -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+ ++count[i]; -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+ return 1; -+ } -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+ ++i; -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+ -+ } -+ return 0; -+} -+/*-----------------------------------------------------------------------------------*/ -+void -+fs_init(void) -+{ -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+ u16_t i; -+ for(i = 0; i < FS_NUMFILES; i++) { -+ count[i] = 0; -+ } -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+} -+/*-----------------------------------------------------------------------------------*/ -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+u16_t fs_count -+(char *name) -+{ -+ struct fsdata_file_noconst *f; -+ u16_t i; -+ -+ i = 0; -+ for(f = (struct fsdata_file_noconst *)FS_ROOT; -+ f != NULL; -+ f = (struct fsdata_file_noconst *)f->next) { -+ -+ if(fs_strcmp(name, f->name) == 0) { -+ return count[i]; -+ } -+ ++i; -+ } -+ return 0; -+} -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+/*-----------------------------------------------------------------------------------*/ ---- /dev/null -+++ b/net/uip-0.9/fs.h -@@ -0,0 +1,80 @@ -+/** -+ * \addtogroup httpd -+ * @{ -+ */ -+ -+/** -+ * \file -+ * HTTP server read-only file system header file. -+ * \author Adam Dunkels <adam@dunkels.com> -+ */ -+ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ -+ */ -+#ifndef __FS_H__ -+#define __FS_H__ -+ -+#include "uip.h" -+ -+/** -+ * An open file in the read-only file system. -+ */ -+struct fs_file { -+ char *data; /**< The actual file data. */ -+ int len; /**< The length of the file data. */ -+}; -+ -+/** -+ * Open a file in the read-only file system. -+ * -+ * \param name The name of the file. -+ * -+ * \param file The file pointer, which must be allocated by caller and -+ * will be filled in by the function. -+ */ -+int fs_open(const char *name, struct fs_file *file); -+ -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+u16_t fs_count(char *name); -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+ -+/** -+ * Initialize the read-only file system. -+ */ -+void fs_init(void); -+ -+#endif /* __FS_H__ */ ---- /dev/null -+++ b/net/uip-0.9/fsdata.c -@@ -0,0 +1,199 @@ -+static const char data_flashing_html[] = { -+ /* /flashing.html */ -+ 0x2f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x69, 0x6e, 0x67, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -+ 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, -+ 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, -+ 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, -+ 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, -+ 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, -+ 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, -+ 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, -+ 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, -+ 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, -+ 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0x3c, 0x62, -+ 0x6f, 0x64, 0x79, 0x20, 0x73, 0x74, 0x79, 0x6c, 0x65, 0x3d, -+ 0x22, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e, 0x3a, 0x20, 0x30, -+ 0x70, 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x3b, 0x20, 0x68, -+ 0x65, 0x69, 0x67, 0x68, 0x74, 0x3a, 0x31, 0x30, 0x30, 0x25, -+ 0x3b, 0x20, 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, -+ 0x66, 0x66, 0x66, 0x3b, 0x20, 0x62, 0x61, 0x63, 0x6b, 0x67, -+ 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, 0x63, 0x6f, 0x6c, 0x6f, -+ 0x72, 0x3a, 0x20, 0x23, 0x66, 0x62, 0x62, 0x30, 0x33, 0x34, -+ 0x3b, 0x22, 0x3e, 0x3c, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, -+ 0x3e, 0x3c, 0x68, 0x31, 0x3e, 0x55, 0x70, 0x67, 0x72, 0x61, -+ 0x64, 0x69, 0x6e, 0x67, 0x20, 0x73, 0x79, 0x73, 0x74, 0x65, -+ 0x6d, 0x20, 0x2e, 0x2e, 0x2e, 0x2e, 0x3c, 0x2f, 0x68, 0x31, -+ 0x3e, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, -+ 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0x3c, 0x2f, 0x68, -+ 0x74, 0x6d, 0x6c, 0x3e, 0xa, }; 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-+ -+static const char data_404_html[] = { -+ /* /404.html */ -+ 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -+ 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, -+ 0x30, 0x34, 0x20, 0x46, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, -+ 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, -+ 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, -+ 0x2f, 0x30, 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, -+ 0x3a, 0x2f, 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, -+ 0x2e, 0x63, 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, -+ 0x75, 0x69, 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, -+ 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, -+ 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, -+ 0xd, 0xa, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, -+ 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, -+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, -+ 0x22, 0x3e, 0x3c, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, -+ 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, 0x20, -+ 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, 0x66, -+ 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 0x3c, -+ 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0x3c, 0x2f, -+ 0x62, 0x6f, 0x64, 0x79, 0x3e, 0x3c, 0x2f, 0x68, 0x74, 0x6d, -+ 0x6c, 0x3e, }; -+ -+static const char data_index_html[] = { -+ /* /index.html */ -+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -+ 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, -+ 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, -+ 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, -+ 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, -+ 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, -+ 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, -+ 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, -+ 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, -+ 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, -+ 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x9, -+ 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x9, 0x9, 0x3c, -+ 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 0xa, 0x9, 0x9, 0x9, -+ 0x4c, 0x61, 0x46, 0x6f, 0x6e, 0x65, 0x72, 0x61, 0x20, 0x46, -+ 0x61, 0x69, 0x6c, 0x73, 0x61, 0x66, 0x65, 0x20, 0x55, 0x49, -+ 0xa, 0x9, 0x9, 0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, -+ 0x3e, 0xa, 0x9, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x3e, -+ 0xa, 0x9, 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x73, 0x74, -+ 0x79, 0x6c, 0x65, 0x3d, 0x22, 0x6d, 0x61, 0x72, 0x67, 0x69, -+ 0x6e, 0x3a, 0x20, 0x30, 0x70, 0x74, 0x20, 0x61, 0x75, 0x74, -+ 0x6f, 0x3b, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3a, -+ 0x31, 0x30, 0x30, 0x25, 0x3b, 0x20, 0x63, 0x6f, 0x6c, 0x6f, -+ 0x72, 0x3a, 0x20, 0x23, 0x30, 0x30, 0x30, 0x3b, 0x20, 0x62, -+ 0x61, 0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, -+ 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, 0x66, 0x62, -+ 0x62, 0x30, 0x33, 0x34, 0x3b, 0x22, 0x3e, 0xa, 0x9, 0x9, -+ 0x3c, 0x68, 0x31, 0x3e, 0x4c, 0x61, 0x46, 0x6f, 0x6e, 0x65, -+ 0x72, 0x61, 0x20, 0x46, 0x61, 0x69, 0x6c, 0x73, 0x61, 0x66, -+ 0x65, 0x20, 0x55, 0x49, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 0xa, -+ 0x9, 0x9, 0x3c, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x6d, 0x65, -+ 0x74, 0x68, 0x6f, 0x64, 0x3d, 0x22, 0x70, 0x6f, 0x73, 0x74, -+ 0x22, 0x20, 0x65, 0x6e, 0x63, 0x74, 0x79, 0x70, 0x65, 0x3d, -+ 0x22, 0x6d, 0x75, 0x6c, 0x74, 0x69, 0x70, 0x61, 0x72, 0x74, -+ 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x2d, 0x64, 0x61, 0x74, 0x61, -+ 0x22, 0x3e, 0xa, 0x9, 0x9, 0x9, 0x3c, 0x69, 0x6e, 0x70, -+ 0x75, 0x74, 0x20, 0x74, 0x79, 0x70, 0x65, 0x3d, 0x66, 0x69, -+ 0x6c, 0x65, 0x20, 0x6e, 0x61, 0x6d, 0x65, 0x3d, 0x66, 0x69, -+ 0x72, 0x6d, 0x77, 0x61, 0x72, 0x65, 0x3e, 0xa, 0x9, 0x9, -+ 0x9, 0x3c, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x20, 0x74, 0x79, -+ 0x70, 0x65, 0x3d, 0x73, 0x75, 0x62, 0x6d, 0x69, 0x74, 0x3e, -+ 0xa, 0x9, 0x9, 0x3c, 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x3e, -+ 0xa, 0x9, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, -+ 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, }; -+ -+static const char data_flash_html[] = { -+ /* /flash.html */ -+ 0x2f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -+ 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, -+ 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, -+ 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, -+ 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, -+ 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, -+ 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, -+ 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, -+ 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, -+ 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, -+ 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x9, -+ 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x9, 0x9, 0x3c, -+ 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 0xa, 0x9, 0x9, 0x9, -+ 0x4c, 0x61, 0x46, 0x6f, 0x6e, 0x65, 0x72, 0x61, 0x20, 0x46, -+ 0x61, 0x69, 0x6c, 0x73, 0x61, 0x66, 0x65, 0x20, 0x55, 0x49, -+ 0xa, 0x9, 0x9, 0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, -+ 0x3e, 0xa, 0x9, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x3e, -+ 0xa, 0x9, 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x73, 0x74, -+ 0x79, 0x6c, 0x65, 0x3d, 0x22, 0x6d, 0x61, 0x72, 0x67, 0x69, -+ 0x6e, 0x3a, 0x20, 0x30, 0x70, 0x74, 0x20, 0x61, 0x75, 0x74, -+ 0x6f, 0x3b, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3a, -+ 0x31, 0x30, 0x30, 0x25, 0x3b, 0x20, 0x63, 0x6f, 0x6c, 0x6f, -+ 0x72, 0x3a, 0x20, 0x23, 0x30, 0x30, 0x30, 0x3b, 0x20, 0x62, -+ 0x61, 0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, -+ 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, 0x66, 0x62, -+ 0x62, 0x30, 0x33, 0x34, 0x3b, 0x22, 0x3e, 0xa, 0x9, 0x9, -+ 0x3c, 0x68, 0x31, 0x3e, 0x46, 0x6c, 0x61, 0x73, 0x68, 0x69, -+ 0x6e, 0x67, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 0xa, 0x9, 0x9, -+ 0x54, 0x68, 0x65, 0x20, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, -+ 0x20, 0x69, 0x73, 0x20, 0x6e, 0x6f, 0x77, 0x20, 0x74, 0x72, -+ 0x79, 0x69, 0x6e, 0x67, 0x20, 0x74, 0x6f, 0x20, 0x66, 0x6c, -+ 0x61, 0x73, 0x68, 0x2e, 0x20, 0x49, 0x66, 0x20, 0x74, 0x68, -+ 0x65, 0x72, 0x65, 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x70, -+ 0x72, 0x6f, 0x62, 0x6c, 0x65, 0x6d, 0x2c, 0x20, 0x74, 0x68, -+ 0x65, 0x20, 0x6c, 0x65, 0x64, 0x73, 0x20, 0x77, 0x69, 0x6c, -+ 0x6c, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x6f, -+ 0x20, 0x62, 0x6c, 0x69, 0x6e, 0x6b, 0x2e, 0xa, 0xa, 0x9, -+ 0x9, 0x41, 0x66, 0x74, 0x65, 0x72, 0x20, 0x61, 0x20, 0x73, -+ 0x75, 0x63, 0x63, 0x65, 0x73, 0x73, 0x66, 0x75, 0x6c, 0x6c, -+ 0x20, 0x75, 0x70, 0x64, 0x61, 0x74, 0x65, 0x20, 0x74, 0x68, -+ 0x65, 0x20, 0x62, 0x6f, 0x78, 0x20, 0x77, 0x69, 0x6c, 0x6c, -+ 0x20, 0x72, 0x65, 0x62, 0x6f, 0x6f, 0x74, 0xa, 0x9, 0x3c, -+ 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, -+ 0x74, 0x6d, 0x6c, 0x3e, 0xa, }; -+ -+const struct fsdata_file file_flashing_html[] = {{NULL, data_flashing_html, data_flashing_html + 15, sizeof(data_flashing_html) - 15}}; -+ -+const struct fsdata_file file_fail_html[] = {{file_flashing_html, data_fail_html, data_fail_html + 11, sizeof(data_fail_html) - 11}}; -+ -+const struct fsdata_file file_404_html[] = {{file_fail_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; -+ -+const struct fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; -+ -+const struct fsdata_file file_flash_html[] = {{file_index_html, data_flash_html, data_flash_html + 12, sizeof(data_flash_html) - 12}}; -+ -+#define FS_ROOT file_flash_html -+ -+#define FS_NUMFILES 5 -\ No newline at end of file ---- /dev/null -+++ b/net/uip-0.9/fsdata.h -@@ -0,0 +1,64 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ -+ */ -+#ifndef __FSDATA_H__ -+#define __FSDATA_H__ -+ -+#include "uipopt.h" -+ -+struct fsdata_file { -+ const struct fsdata_file *next; -+ const char *name; -+ const char *data; -+ const int len; -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+ u16_t count; -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+}; -+ -+struct fsdata_file_noconst { -+ struct fsdata_file *next; -+ char *name; -+ char *data; -+ int len; -+#ifdef FS_STATISTICS -+#if FS_STATISTICS == 1 -+ u16_t count; -+#endif /* FS_STATISTICS */ -+#endif /* FS_STATISTICS */ -+}; -+ -+#endif /* __FSDATA_H__ */ ---- /dev/null -+++ b/net/uip-0.9/httpd.c -@@ -0,0 +1,278 @@ -+#include "uip.h" -+#include "httpd.h" -+#include "fs.h" -+#include "fsdata.h" -+#include <asm/addrspace.h> -+ -+#define HTTP_NONE 0 -+#define HTTP_FILE 1 -+#define HTTP_FIRMWARE 2 -+ -+#define PRINT(x) printf("%s", x) -+#define PRINTLN(x) printf("%s\n", x) -+ -+extern unsigned long do_http_tmp_address(void); -+ -+struct httpd_state *hs; -+ -+extern const struct fsdata_file file_index_html; -+extern const struct fsdata_file file_404_html; -+extern const struct fsdata_file file_flash_html; -+extern int httpd_upload_complete; -+extern unsigned char *httpd_upload_data; -+unsigned char *upload_data; -+extern ulong NetBootFileXferSize; -+int upload_running = 0; -+ -+#define ISO_G 0x47 -+#define ISO_E 0x45 -+#define ISO_T 0x54 -+#define ISO_P 0x50 -+#define ISO_O 0x4f -+#define ISO_S 0x53 -+#define ISO_T 0x54 -+#define ISO_slash 0x2f -+#define ISO_c 0x63 -+#define ISO_g 0x67 -+#define ISO_i 0x69 -+#define ISO_space 0x20 -+#define ISO_nl 0x0a -+#define ISO_cr 0x0d -+#define ISO_a 0x61 -+#define ISO_t 0x74 -+#define ISO_hash 0x23 -+#define ISO_period 0x2e -+ -+static char eol[3] = { 0x0d, 0x0a, 0x00 }; -+static char eol2[5] = { 0x0d, 0x0a, 0x0d, 0x0a, 0x00 }; -+static char boundary[128]; -+static int boundary_len = 0; -+ -+/* we use this so that we can do without the ctype library */ -+#define is_digit(c) ((c) >= '0' && (c) <= '9') -+static int atoi(const char *s) -+{ -+ int i=0; -+ -+ while (is_digit(*s)) -+ i = i*10 + *(s++) - '0'; -+ return i; -+} -+ -+void -+httpd_init(void) -+{ -+ fs_init(); -+ uip_listen(HTONS(80)); -+} -+ -+void -+httpd_appcall(void) -+{ -+ struct fs_file fsfile; -+ u8_t i; -+ switch(uip_conn->lport) { -+ case HTONS(80): -+ hs = (struct httpd_state *)(uip_conn->appstate); -+ if(uip_connected()) -+ { -+ hs->state = HTTP_NONE; -+ hs->count = 0; -+ return; -+ } else if(uip_poll()) -+ { -+ if(hs->count++ >= 1000) { -+ uip_abort(); -+ } -+ return; -+ } else if(uip_newdata() && hs->state == HTTP_NONE) -+ { -+ if(uip_appdata[0] == ISO_G && -+ uip_appdata[1] == ISO_E && -+ uip_appdata[2] == ISO_T && -+ uip_appdata[3] == ISO_space) -+ { -+ hs->state = HTTP_FILE; -+ } -+ if(uip_appdata[0] == ISO_P && -+ uip_appdata[1] == ISO_O && -+ uip_appdata[2] == ISO_S && -+ uip_appdata[3] == ISO_T && -+ uip_appdata[4] == ISO_space) -+ { -+ hs->state = HTTP_FIRMWARE; -+ } -+ if(hs->state == HTTP_NONE) -+ { -+ uip_abort(); -+ return; -+ } -+ if(hs->state == HTTP_FILE) -+ { -+ for(i = 4; i < 40; ++i) -+ { -+ if(uip_appdata[i] == ISO_space || -+ uip_appdata[i] == ISO_cr || -+ uip_appdata[i] == ISO_nl) -+ { -+ uip_appdata[i] = 0; -+ break; -+ } -+ } -+ -+ PRINT("request for file "); -+ PRINTLN(&uip_appdata[4]); -+ if(uip_appdata[4] == ISO_slash && -+ uip_appdata[5] == 0) -+ { -+ fs_open(file_index_html.name, &fsfile); -+ } else { -+ if(!fs_open((const char *)&uip_appdata[4], &fsfile)) -+ { -+ PRINTLN("couldn't open file"); -+ fs_open(file_index_html.name, &fsfile); -+ } -+ } -+ hs->script = 0; -+ hs->state = HTTP_FILE; -+ hs->dataptr = fsfile.data; -+ hs->count = fsfile.len; -+ } -+ if(hs->state == HTTP_FIRMWARE) -+ { -+ unsigned char *start = (unsigned char*)uip_appdata; -+ char *clen = strstr(start, "Content-Length:"); -+ int len = 0; -+ unsigned char *next, *end; -+ unsigned char *boundary_start; -+ int i; -+ uip_appdata[uip_len] = '\0'; -+ if(clen) -+ { -+ clen += sizeof("Content-Length:"); -+ next = strstr(clen, eol); -+ if(next) -+ { -+ len = atoi(clen); -+ next++; -+ printf("expecting %d bytes\n", len); -+ upload_data = httpd_upload_data = (unsigned char *)do_http_tmp_address(); -+ printf("received data will be stored at 0x%08X\n", upload_data); -+ if(!upload_data) -+ { -+ printf("failed to allocate memory\n"); -+ uip_close(); -+ return; -+ } -+ } else { -+ uip_close(); -+ return; -+ } -+ } -+ if(len < 4 * 1024) -+ { -+ uip_close(); -+ return; -+ } -+ boundary_start = strstr(next, "---"); -+ if(!boundary_start) -+ { -+ uip_close(); -+ return; -+ } -+ end = strstr(boundary_start, eol); -+ if(!eol) -+ { -+ uip_close(); -+ return; -+ } -+ boundary_len = end - boundary_start; -+ memcpy(boundary, boundary_start, boundary_len); -+ boundary[boundary_len] = 0; -+ next = strstr(boundary_start, "name=\"firmware\";"); -+ if(!next) -+ { -+ uip_close(); -+ return; -+ } -+ next = strstr(next, eol2); -+ if(!next) -+ { -+ printf("could not find start of data\n"); -+ uip_close(); -+ return; -+ } -+ next += 4; -+ hs->script = 0; -+ hs->state = HTTP_FIRMWARE; -+ hs->upload = uip_len - (next - start); -+ hs->upload_total = len - (int)(next - boundary_start); -+ hs->upload_total -= (strlen(boundary) + 6); -+ //printf("storing %d bytes at %p\n", (int)hs->upload, upload_data); -+ for(i = 0; i < hs->upload; i++) -+ upload_data[i] = next[i]; -+ upload_data += (int)hs->upload; -+ printf("%d / %d\n", (int)hs->upload, hs->upload_total); -+ uip_slen = 0; -+ return; -+ } -+ } -+ -+ if(hs->state == HTTP_FIRMWARE) -+ { -+ if(uip_newdata()) -+ { -+ int i; -+ hs->count = 0; -+ uip_appdata[uip_len] = '\0'; -+ hs->upload += uip_len; -+ //printf("storing %d bytes at %p\n", uip_len, upload_data); -+ printf("%d / %d\n", (int)hs->upload, hs->upload_total); -+ for(i = 0; i < uip_len; i++) -+ upload_data[i] = uip_appdata[i]; -+ upload_data += uip_len; -+ uip_slen = 0; -+ if(hs->upload >= hs->upload_total) -+ { -+ upload_running = 1; -+ NetBootFileXferSize = hs->upload_total; -+ fs_open(file_flash_html.name, &fsfile); -+ hs->script = 0; -+ hs->state = HTTP_FILE; -+ hs->dataptr = fsfile.data; -+ hs->count = fsfile.len; -+ } -+ } -+ } -+ if(hs->state == HTTP_FILE) -+ { -+ if(uip_acked()) -+ { -+ if(hs->count >= uip_conn->len) -+ { -+ hs->count -= uip_conn->len; -+ hs->dataptr += uip_conn->len; -+ } else { -+ hs->count = 0; -+ } -+ if(hs->count == 0) -+ { -+ if(upload_running) -+ { -+ int i; -+ httpd_upload_complete = 1; -+ // for(i = 0; i < hs->upload_total; i++) -+ // printf("%c", httpd_upload_data[i]); -+ } -+ uip_close(); -+ } -+ } -+ uip_send(hs->dataptr, hs->count); -+ } -+ break; -+ -+ default: -+ uip_abort(); -+ break; -+ } -+} ---- /dev/null -+++ b/net/uip-0.9/httpd.h -@@ -0,0 +1,83 @@ -+/** -+ * \addtogroup httpd -+ * @{ -+ */ -+ -+/** -+ * \file -+ * HTTP server header file. -+ * \author Adam Dunkels <adam@dunkels.com> -+ */ -+ -+/* -+ * Copyright (c) 2001, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ -+ * -+ */ -+ -+#ifndef __HTTPD_H__ -+#define __HTTPD_H__ -+ -+void httpd_init(void); -+void httpd_appcall(void); -+ -+/* UIP_APPCALL: the name of the application function. This function -+ must return void and take no arguments (i.e., C type "void -+ appfunc(void)"). */ -+#ifndef UIP_APPCALL -+#define UIP_APPCALL httpd_appcall -+#endif -+ -+struct httpd_state { -+ u8_t state; -+ u16_t count; -+ char *dataptr; -+ char *script; -+ unsigned int upload; -+ unsigned int upload_total; -+}; -+ -+ -+/* UIP_APPSTATE_SIZE: The size of the application-specific state -+ stored in the uip_conn structure. */ -+#ifndef UIP_APPSTATE_SIZE -+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) -+#endif -+ -+#define FS_STATISTICS 1 -+ -+extern struct httpd_state *hs; -+ -+ -+/* we copy the data to RAM+10MB */ -+#define TMP_DATA 0x8A100000 -+ -+#endif /* __HTTPD_H__ */ ---- /dev/null -+++ b/net/uip-0.9/main.c -@@ -0,0 +1,88 @@ -+/* -+ * Copyright (c) 2001-2003, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: main.c,v 1.10.2.1 2003/10/04 22:54:17 adam Exp $ -+ * -+ */ -+ -+ -+#include "uip.h" -+#include "uip_arp.h" -+#include "tapdev.h" -+#include "httpd.h" -+ -+#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) -+ -+#ifndef NULL -+#define NULL (void *)0 -+#endif /* NULL */ -+ -+/*-----------------------------------------------------------------------------------*/ -+int -+main(void) -+{ -+ u8_t i, arptimer; -+ tapdev_init(); -+ uip_init(); -+ httpd_init(); -+ arptimer = 0; -+ while(1) { -+ uip_len = tapdev_read(); -+ if(uip_len == 0) { -+ for(i = 0; i < UIP_CONNS; i++) { -+ uip_periodic(i); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ tapdev_send(); -+ } -+ } -+ -+ if(++arptimer == 20) { -+ uip_arp_timer(); -+ arptimer = 0; -+ } -+ } else { -+ if(BUF->type == htons(UIP_ETHTYPE_IP)) { -+ uip_arp_ipin(); -+ uip_input(); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ tapdev_send(); -+ } -+ } else if(BUF->type == htons(UIP_ETHTYPE_ARP)) { -+ uip_arp_arpin(); -+ if(uip_len > 0) { -+ tapdev_send(); -+ } -+ } -+ } -+ } -+ return 0; -+} ---- /dev/null -+++ b/net/uip-0.9/tapdev.c -@@ -0,0 +1,192 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ -+ */ -+ -+ -+#include <fcntl.h> -+#include <stdlib.h> -+#include <stdio.h> -+#include <unistd.h> -+#include <string.h> -+#include <sys/ioctl.h> -+#include <sys/socket.h> -+#include <sys/types.h> -+#include <sys/time.h> -+#include <sys/uio.h> -+#include <sys/socket.h> -+ -+#ifdef linux -+#include <sys/ioctl.h> -+#include <linux/if.h> -+#include <linux/if_tun.h> -+#define DEVTAP "/dev/net/tun" -+#else /* linux */ -+#define DEVTAP "/dev/tap0" -+#endif /* linux */ -+ -+#include "uip.h" -+ -+static int fd; -+ -+static unsigned long lasttime; -+static struct timezone tz; -+ -+/*-----------------------------------------------------------------------------------*/ -+void -+tapdev_init(void) -+{ -+ char buf[1024]; -+ -+ fd = open(DEVTAP, O_RDWR); -+ if(fd == -1) { -+ perror("tapdev: tapdev_init: open"); -+ exit(1); -+ } -+ -+#ifdef linux -+ { -+ struct ifreq ifr; -+ memset(&ifr, 0, sizeof(ifr)); -+ ifr.ifr_flags = IFF_TAP|IFF_NO_PI; -+ if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { -+ perror(buf); -+ exit(1); -+ } -+ } -+#endif /* Linux */ -+ -+ snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", -+ UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); -+ system(buf); -+ -+ lasttime = 0; -+} -+ -+void dump_mem(int type, int len) -+{ -+#if DUMP == 1 -+ int i; -+ for(i = 0; i < len; i++) -+ printf("%c", uip_buf[i]); -+ if(type) -+ { -+ printf("\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01"); -+ printf("\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01"); -+ } else { -+ printf("\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02"); -+ printf("\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02"); -+ } -+ fflush(stdout); -+#endif -+} -+ -+/*-----------------------------------------------------------------------------------*/ -+unsigned int -+tapdev_read(void) -+{ -+ fd_set fdset; -+ struct timeval tv, now; -+ int ret; -+ -+ if(lasttime >= 500000) { -+ lasttime = 0; -+ return 0; -+ } -+ -+ tv.tv_sec = 0; -+ tv.tv_usec = 500000 - lasttime; -+ -+ -+ FD_ZERO(&fdset); -+ FD_SET(fd, &fdset); -+ -+ gettimeofday(&now, &tz); -+ ret = select(fd + 1, &fdset, NULL, NULL, &tv); -+ if(ret == 0) { -+ lasttime = 0; -+ return 0; -+ } -+ ret = read(fd, uip_buf, UIP_BUFSIZE); -+ if(ret == -1) { -+ perror("tap_dev: tapdev_read: read"); -+ } -+ gettimeofday(&tv, &tz); -+ lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); -+ dump_mem(0, ret); -+ return ret; -+} -+/*-----------------------------------------------------------------------------------*/ -+void -+tapdev_send(void) -+{ -+ int ret; -+ struct iovec iov[2]; -+ -+#ifdef linux -+ { -+ char tmpbuf[UIP_BUFSIZE]; -+ int i; -+ -+ for(i = 0; i < 40 + UIP_LLH_LEN; i++) { -+ tmpbuf[i] = uip_buf[i]; -+ } -+ -+ for(; i < uip_len; i++) { -+ tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; -+ } -+ -+ ret = write(fd, tmpbuf, uip_len); -+ } -+#else -+ -+ if(uip_len < 40 + UIP_LLH_LEN) { -+ ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); -+ } else { -+ iov[0].iov_base = uip_buf; -+ iov[0].iov_len = 40 + UIP_LLH_LEN; -+ iov[1].iov_base = (char *)uip_appdata; -+ iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); -+ -+ ret = writev(fd, iov, 2); -+ } -+#endif -+ dump_mem(1, ret); -+ -+ if(ret == -1) { -+ perror("tap_dev: tapdev_send: writev"); -+ exit(1); -+ } -+} -+/*-----------------------------------------------------------------------------------*/ ---- /dev/null -+++ b/net/uip-0.9/tapdev.h -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (c) 2001, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ -+ * -+ */ -+ -+#ifndef __TAPDEV_H__ -+#define __TAPDEV_H__ -+ -+void tapdev_init(void); -+unsigned int tapdev_read(void); -+void tapdev_send(void); -+ -+#endif /* __TAPDEV_H__ */ ---- /dev/null -+++ b/net/uip-0.9/uip.c -@@ -0,0 +1,1503 @@ -+/** -+ * \addtogroup uip -+ * @{ -+ */ -+ -+/** -+ * \file -+ * The uIP TCP/IP stack code. -+ * \author Adam Dunkels <adam@dunkels.com> -+ */ -+ -+/* -+ * Copyright (c) 2001-2003, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ -+ * -+ */ -+ -+/* -+This is a small implementation of the IP and TCP protocols (as well as -+some basic ICMP stuff). The implementation couples the IP, TCP and the -+application layers very tightly. To keep the size of the compiled code -+down, this code also features heavy usage of the goto statement. -+ -+The principle is that we have a small buffer, called the uip_buf, in -+which the device driver puts an incoming packet. The TCP/IP stack -+parses the headers in the packet, and calls upon the application. If -+the remote host has sent data to the application, this data is present -+in the uip_buf and the application read the data from there. It is up -+to the application to put this data into a byte stream if needed. The -+application will not be fed with data that is out of sequence. -+ -+If the application whishes to send data to the peer, it should put its -+data into the uip_buf, 40 bytes from the start of the buffer. The -+TCP/IP stack will calculate the checksums, and fill in the necessary -+header fields and finally send the packet back to the peer. -+*/ -+ -+#include "uip.h" -+#include "uipopt.h" -+#include "uip_arch.h" -+ -+/*-----------------------------------------------------------------------------------*/ -+/* Variable definitions. */ -+ -+ -+/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ -+#if UIP_FIXEDADDR > 0 -+const unsigned short int uip_hostaddr[2] = -+ {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), -+ HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; -+const unsigned short int uip_arp_draddr[2] = -+ {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), -+ HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; -+const unsigned short int uip_arp_netmask[2] = -+ {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), -+ HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; -+#else -+unsigned short int uip_hostaddr[2]; -+unsigned short int uip_arp_draddr[2], uip_arp_netmask[2]; -+#endif /* UIP_FIXEDADDR */ -+ -+u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains -+ incoming packets. */ -+volatile u8_t *uip_appdata; /* The uip_appdata pointer points to -+ application data. */ -+volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the -+ application data which is to be sent. */ -+#if UIP_URGDATA > 0 -+volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to -+ urgent data (out-of-band data), if -+ present. */ -+volatile u8_t uip_urglen, uip_surglen; -+#endif /* UIP_URGDATA > 0 */ -+ -+volatile unsigned short int uip_len, uip_slen; -+ /* The uip_len is either 8 or 16 bits, -+ depending on the maximum packet -+ size. */ -+ -+volatile u8_t uip_flags; /* The uip_flags variable is used for -+ communication between the TCP/IP stack -+ and the application program. */ -+struct uip_conn *uip_conn; /* uip_conn always points to the current -+ connection. */ -+ -+struct uip_conn uip_conns[UIP_CONNS]; -+ /* The uip_conns array holds all TCP -+ connections. */ -+unsigned short int uip_listenports[UIP_LISTENPORTS]; -+ /* The uip_listenports list all currently -+ listning ports. */ -+#if UIP_UDP -+struct uip_udp_conn *uip_udp_conn; -+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -+#endif /* UIP_UDP */ -+ -+ -+static unsigned short int ipid; /* Ths ipid variable is an increasing -+ number that is used for the IP ID -+ field. */ -+ -+static u8_t iss[4]; /* The iss variable is used for the TCP -+ initial sequence number. */ -+ -+#if UIP_ACTIVE_OPEN -+static unsigned short int lastport; /* Keeps track of the last port used for -+ a new connection. */ -+#endif /* UIP_ACTIVE_OPEN */ -+ -+/* Temporary variables. */ -+volatile u8_t uip_acc32[4]; -+static u8_t c, opt; -+static unsigned short int tmp16; -+ -+/* Structures and definitions. */ -+#define TCP_FIN 0x01 -+#define TCP_SYN 0x02 -+#define TCP_RST 0x04 -+#define TCP_PSH 0x08 -+#define TCP_ACK 0x10 -+#define TCP_URG 0x20 -+#define TCP_CTL 0x3f -+ -+#define ICMP_ECHO_REPLY 0 -+#define ICMP_ECHO 8 -+ -+/* Macros. */ -+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -+#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) -+#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) -+#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) -+ -+#if UIP_STATISTICS == 1 -+struct uip_stats uip_stat; -+#define UIP_STAT(s) s -+#else -+#define UIP_STAT(s) -+#endif /* UIP_STATISTICS == 1 */ -+ -+#if UIP_LOGGING == 1 -+extern void puts(const char *s); -+#define UIP_LOG(m) puts(m) -+#else -+#define UIP_LOG(m) -+#endif /* UIP_LOGGING == 1 */ -+ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_init(void) -+{ -+ for(c = 0; c < UIP_LISTENPORTS; ++c) { -+ uip_listenports[c] = 0; -+ } -+ for(c = 0; c < UIP_CONNS; ++c) { -+ uip_conns[c].tcpstateflags = CLOSED; -+ } -+#if UIP_ACTIVE_OPEN -+ lastport = 1024; -+#endif /* UIP_ACTIVE_OPEN */ -+ -+#if UIP_UDP -+ for(c = 0; c < UIP_UDP_CONNS; ++c) { -+ uip_udp_conns[c].lport = 0; -+ } -+#endif /* UIP_UDP */ -+ -+ -+ /* IPv4 initialization. */ -+#if UIP_FIXEDADDR == 0 -+ uip_hostaddr[0] = uip_hostaddr[1] = 0; -+#endif /* UIP_FIXEDADDR */ -+ -+} -+/*-----------------------------------------------------------------------------------*/ -+#if UIP_ACTIVE_OPEN -+struct uip_conn * -+uip_connect(unsigned short int *ripaddr, unsigned short int rport) -+{ -+ register struct uip_conn *conn, *cconn; -+ -+ /* Find an unused local port. */ -+ again: -+ ++lastport; -+ -+ if(lastport >= 32000) { -+ lastport = 4096; -+ } -+ -+ /* Check if this port is already in use, and if so try to find -+ another one. */ -+ for(c = 0; c < UIP_CONNS; ++c) { -+ conn = &uip_conns[c]; -+ if(conn->tcpstateflags != CLOSED && -+ conn->lport == htons(lastport)) { -+ goto again; -+ } -+ } -+ -+ -+ conn = 0; -+ for(c = 0; c < UIP_CONNS; ++c) { -+ cconn = &uip_conns[c]; -+ if(cconn->tcpstateflags == CLOSED) { -+ conn = cconn; -+ break; -+ } -+ if(cconn->tcpstateflags == TIME_WAIT) { -+ if(conn == 0 || -+ cconn->timer > uip_conn->timer) { -+ conn = cconn; -+ } -+ } -+ } -+ -+ if(conn == 0) { -+ return 0; -+ } -+ -+ conn->tcpstateflags = SYN_SENT; -+ -+ conn->snd_nxt[0] = iss[0]; -+ conn->snd_nxt[1] = iss[1]; -+ conn->snd_nxt[2] = iss[2]; -+ conn->snd_nxt[3] = iss[3]; -+ -+ conn->initialmss = conn->mss = UIP_TCP_MSS; -+ -+ conn->len = 1; /* TCP length of the SYN is one. */ -+ conn->nrtx = 0; -+ conn->timer = 1; /* Send the SYN next time around. */ -+ conn->rto = UIP_RTO; -+ conn->sa = 0; -+ conn->sv = 16; -+ conn->lport = htons(lastport); -+ conn->rport = rport; -+ conn->ripaddr[0] = ripaddr[0]; -+ conn->ripaddr[1] = ripaddr[1]; -+ -+ return conn; -+} -+#endif /* UIP_ACTIVE_OPEN */ -+/*-----------------------------------------------------------------------------------*/ -+#if UIP_UDP -+struct uip_udp_conn * -+uip_udp_new(unsigned short int *ripaddr, unsigned short int rport) -+{ -+ register struct uip_udp_conn *conn; -+ -+ /* Find an unused local port. */ -+ again: -+ ++lastport; -+ -+ if(lastport >= 32000) { -+ lastport = 4096; -+ } -+ -+ for(c = 0; c < UIP_UDP_CONNS; ++c) { -+ if(uip_udp_conns[c].lport == lastport) { -+ goto again; -+ } -+ } -+ -+ -+ conn = 0; -+ for(c = 0; c < UIP_UDP_CONNS; ++c) { -+ if(uip_udp_conns[c].lport == 0) { -+ conn = &uip_udp_conns[c]; -+ break; -+ } -+ } -+ -+ if(conn == 0) { -+ return 0; -+ } -+ -+ conn->lport = HTONS(lastport); -+ conn->rport = HTONS(rport); -+ conn->ripaddr[0] = ripaddr[0]; -+ conn->ripaddr[1] = ripaddr[1]; -+ -+ return conn; -+} -+#endif /* UIP_UDP */ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_unlisten(unsigned short int port) -+{ -+ for(c = 0; c < UIP_LISTENPORTS; ++c) { -+ if(uip_listenports[c] == port) { -+ uip_listenports[c] = 0; -+ return; -+ } -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_listen(unsigned short int port) -+{ -+ for(c = 0; c < UIP_LISTENPORTS; ++c) { -+ if(uip_listenports[c] == 0) { -+ uip_listenports[c] = port; -+ return; -+ } -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -+/* XXX: IP fragment reassembly: not well-tested. */ -+ -+#if UIP_REASSEMBLY -+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) -+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; -+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; -+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, -+ 0x0f, 0x07, 0x03, 0x01}; -+static unsigned short int uip_reasslen; -+static u8_t uip_reassflags; -+#define UIP_REASS_FLAG_LASTFRAG 0x01 -+static u8_t uip_reasstmr; -+ -+#define IP_HLEN 20 -+#define IP_MF 0x20 -+ -+static u8_t -+uip_reass(void) -+{ -+ unsigned short int offset, len; -+ unsigned short int i; -+ -+ /* If ip_reasstmr is zero, no packet is present in the buffer, so we -+ write the IP header of the fragment into the reassembly -+ buffer. The timer is updated with the maximum age. */ -+ if(uip_reasstmr == 0) { -+ memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); -+ uip_reasstmr = UIP_REASS_MAXAGE; -+ uip_reassflags = 0; -+ /* Clear the bitmap. */ -+ memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); -+ } -+ -+ /* Check if the incoming fragment matches the one currently present -+ in the reasembly buffer. If so, we proceed with copying the -+ fragment into the buffer. */ -+ if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && -+ BUF->srcipaddr[1] == FBUF->srcipaddr[1] && -+ BUF->destipaddr[0] == FBUF->destipaddr[0] && -+ BUF->destipaddr[1] == FBUF->destipaddr[1] && -+ BUF->ipid[0] == FBUF->ipid[0] && -+ BUF->ipid[1] == FBUF->ipid[1]) { -+ -+ len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; -+ offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; -+ -+ /* If the offset or the offset + fragment length overflows the -+ reassembly buffer, we discard the entire packet. */ -+ if(offset > UIP_REASS_BUFSIZE || -+ offset + len > UIP_REASS_BUFSIZE) { -+ uip_reasstmr = 0; -+ goto nullreturn; -+ } -+ -+ /* Copy the fragment into the reassembly buffer, at the right -+ offset. */ -+ memcpy(&uip_reassbuf[IP_HLEN + offset], -+ (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), -+ len); -+ -+ /* Update the bitmap. */ -+ if(offset / (8 * 8) == (offset + len) / (8 * 8)) { -+ /* If the two endpoints are in the same byte, we only update -+ that byte. */ -+ -+ uip_reassbitmap[offset / (8 * 8)] |= -+ bitmap_bits[(offset / 8 ) & 7] & -+ ~bitmap_bits[((offset + len) / 8 ) & 7]; -+ } else { -+ /* If the two endpoints are in different bytes, we update the -+ bytes in the endpoints and fill the stuff inbetween with -+ 0xff. */ -+ uip_reassbitmap[offset / (8 * 8)] |= -+ bitmap_bits[(offset / 8 ) & 7]; -+ for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { -+ uip_reassbitmap[i] = 0xff; -+ } -+ uip_reassbitmap[(offset + len) / (8 * 8)] |= -+ ~bitmap_bits[((offset + len) / 8 ) & 7]; -+ } -+ -+ /* If this fragment has the More Fragments flag set to zero, we -+ know that this is the last fragment, so we can calculate the -+ size of the entire packet. We also set the -+ IP_REASS_FLAG_LASTFRAG flag to indicate that we have received -+ the final fragment. */ -+ -+ if((BUF->ipoffset[0] & IP_MF) == 0) { -+ uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; -+ uip_reasslen = offset + len; -+ } -+ -+ /* Finally, we check if we have a full packet in the buffer. We do -+ this by checking if we have the last fragment and if all bits -+ in the bitmap are set. */ -+ if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { -+ /* Check all bytes up to and including all but the last byte in -+ the bitmap. */ -+ for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { -+ if(uip_reassbitmap[i] != 0xff) { -+ goto nullreturn; -+ } -+ } -+ /* Check the last byte in the bitmap. It should contain just the -+ right amount of bits. */ -+ if(uip_reassbitmap[uip_reasslen / (8 * 8)] != -+ (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { -+ goto nullreturn; -+ } -+ -+ /* If we have come this far, we have a full packet in the -+ buffer, so we allocate a pbuf and copy the packet into it. We -+ also reset the timer. */ -+ uip_reasstmr = 0; -+ memcpy(BUF, FBUF, uip_reasslen); -+ -+ /* Pretend to be a "normal" (i.e., not fragmented) IP packet -+ from now on. */ -+ BUF->ipoffset[0] = BUF->ipoffset[1] = 0; -+ BUF->len[0] = uip_reasslen >> 8; -+ BUF->len[1] = uip_reasslen & 0xff; -+ BUF->ipchksum = 0; -+ BUF->ipchksum = ~(uip_ipchksum()); -+ -+ return uip_reasslen; -+ } -+ } -+ -+ nullreturn: -+ return 0; -+} -+#endif /* UIP_REASSEMBL */ -+/*-----------------------------------------------------------------------------------*/ -+static void -+uip_add_rcv_nxt(unsigned short int n) -+{ -+ uip_add32(uip_conn->rcv_nxt, n); -+ uip_conn->rcv_nxt[0] = uip_acc32[0]; -+ uip_conn->rcv_nxt[1] = uip_acc32[1]; -+ uip_conn->rcv_nxt[2] = uip_acc32[2]; -+ uip_conn->rcv_nxt[3] = uip_acc32[3]; -+} -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_process(u8_t flag) -+{ -+ register struct uip_conn *uip_connr = uip_conn; -+ -+ uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; -+ -+ -+ /* Check if we were invoked because of the perodic timer fireing. */ -+ if(flag == UIP_TIMER) { -+#if UIP_REASSEMBLY -+ if(uip_reasstmr != 0) { -+ --uip_reasstmr; -+ } -+#endif /* UIP_REASSEMBLY */ -+ /* Increase the initial sequence number. */ -+ if(++iss[3] == 0) { -+ if(++iss[2] == 0) { -+ if(++iss[1] == 0) { -+ ++iss[0]; -+ } -+ } -+ } -+ uip_len = 0; -+ if(uip_connr->tcpstateflags == TIME_WAIT || -+ uip_connr->tcpstateflags == FIN_WAIT_2) { -+ ++(uip_connr->timer); -+ if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { -+ uip_connr->tcpstateflags = CLOSED; -+ } -+ } else if(uip_connr->tcpstateflags != CLOSED) { -+ /* If the connection has outstanding data, we increase the -+ connection's timer and see if it has reached the RTO value -+ in which case we retransmit. */ -+ if(uip_outstanding(uip_connr)) { -+ if(uip_connr->timer-- == 0) { -+ if(uip_connr->nrtx == UIP_MAXRTX || -+ ((uip_connr->tcpstateflags == SYN_SENT || -+ uip_connr->tcpstateflags == SYN_RCVD) && -+ uip_connr->nrtx == UIP_MAXSYNRTX)) { -+ uip_connr->tcpstateflags = CLOSED; -+ -+ /* We call UIP_APPCALL() with uip_flags set to -+ UIP_TIMEDOUT to inform the application that the -+ connection has timed out. */ -+ uip_flags = UIP_TIMEDOUT; -+ UIP_APPCALL(); -+ -+ /* We also send a reset packet to the remote host. */ -+ BUF->flags = TCP_RST | TCP_ACK; -+ goto tcp_send_nodata; -+ } -+ -+ /* Exponential backoff. */ -+ uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? -+ 4: -+ uip_connr->nrtx); -+ ++(uip_connr->nrtx); -+ -+ /* Ok, so we need to retransmit. We do this differently -+ depending on which state we are in. In ESTABLISHED, we -+ call upon the application so that it may prepare the -+ data for the retransmit. In SYN_RCVD, we resend the -+ SYNACK that we sent earlier and in LAST_ACK we have to -+ retransmit our FINACK. */ -+ UIP_STAT(++uip_stat.tcp.rexmit); -+ switch(uip_connr->tcpstateflags & TS_MASK) { -+ case SYN_RCVD: -+ /* In the SYN_RCVD state, we should retransmit our -+ SYNACK. */ -+ goto tcp_send_synack; -+ -+#if UIP_ACTIVE_OPEN -+ case SYN_SENT: -+ /* In the SYN_SENT state, we retransmit out SYN. */ -+ BUF->flags = 0; -+ goto tcp_send_syn; -+#endif /* UIP_ACTIVE_OPEN */ -+ -+ case ESTABLISHED: -+ /* In the ESTABLISHED state, we call upon the application -+ to do the actual retransmit after which we jump into -+ the code for sending out the packet (the apprexmit -+ label). */ -+ uip_len = 0; -+ uip_slen = 0; -+ uip_flags = UIP_REXMIT; -+ UIP_APPCALL(); -+ goto apprexmit; -+ -+ case FIN_WAIT_1: -+ case CLOSING: -+ case LAST_ACK: -+ /* In all these states we should retransmit a FINACK. */ -+ goto tcp_send_finack; -+ -+ } -+ } -+ } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { -+ /* If there was no need for a retransmission, we poll the -+ application for new data. */ -+ uip_len = 0; -+ uip_slen = 0; -+ uip_flags = UIP_POLL; -+ UIP_APPCALL(); -+ goto appsend; -+ } -+ } -+ goto drop; -+ } -+#if UIP_UDP -+ if(flag == UIP_UDP_TIMER) { -+ if(uip_udp_conn->lport != 0) { -+ uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; -+ uip_len = uip_slen = 0; -+ uip_flags = UIP_POLL; -+ UIP_UDP_APPCALL(); -+ goto udp_send; -+ } else { -+ goto drop; -+ } -+ } -+#endif -+ -+ /* This is where the input processing starts. */ -+ UIP_STAT(++uip_stat.ip.recv); -+ -+ -+ /* Start of IPv4 input header processing code. */ -+ -+ /* Check validity of the IP header. */ -+ if(BUF->vhl != 0x45) { /* IP version and header length. */ -+ UIP_STAT(++uip_stat.ip.drop); -+ UIP_STAT(++uip_stat.ip.vhlerr); -+ UIP_LOG("ip: invalid version or header length."); -+ goto drop; -+ } -+ -+ /* Check the size of the packet. If the size reported to us in -+ uip_len doesn't match the size reported in the IP header, there -+ has been a transmission error and we drop the packet. */ -+ -+ if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ -+ uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); -+ } -+ if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ -+ uip_len = (uip_len & 0xff00) | BUF->len[1]; -+ } -+ -+ /* Check the fragment flag. */ -+ if((BUF->ipoffset[0] & 0x3f) != 0 || -+ BUF->ipoffset[1] != 0) { -+#if UIP_REASSEMBLY -+ uip_len = uip_reass(); -+ if(uip_len == 0) { -+ goto drop; -+ } -+#else -+ UIP_STAT(++uip_stat.ip.drop); -+ UIP_STAT(++uip_stat.ip.fragerr); -+ UIP_LOG("ip: fragment dropped."); -+ goto drop; -+#endif /* UIP_REASSEMBLY */ -+ } -+ -+ /* If we are configured to use ping IP address configuration and -+ hasn't been assigned an IP address yet, we accept all ICMP -+ packets. */ -+#if UIP_PINGADDRCONF -+ if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { -+ if(BUF->proto == UIP_PROTO_ICMP) { -+ UIP_LOG("ip: possible ping config packet received."); -+ goto icmp_input; -+ } else { -+ UIP_LOG("ip: packet dropped since no address assigned."); -+ goto drop; -+ } -+ } -+#endif /* UIP_PINGADDRCONF */ -+ -+ /* Check if the packet is destined for our IP address. */ -+ if(BUF->destipaddr[0] != uip_hostaddr[0]) { -+ UIP_STAT(++uip_stat.ip.drop); -+ UIP_LOG("ip: packet not for us."); -+ goto drop; -+ } -+ if(BUF->destipaddr[1] != uip_hostaddr[1]) { -+ UIP_STAT(++uip_stat.ip.drop); -+ UIP_LOG("ip: packet not for us."); -+ goto drop; -+ } -+ -+ if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header -+ checksum. */ -+ UIP_STAT(++uip_stat.ip.drop); -+ UIP_STAT(++uip_stat.ip.chkerr); -+ UIP_LOG("ip: bad checksum."); -+ goto drop; -+ } -+ -+ if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump -+ to the tcp_input label. */ -+ goto tcp_input; -+ -+#if UIP_UDP -+ if(BUF->proto == UIP_PROTO_UDP) -+ goto udp_input; -+#endif /* UIP_UDP */ -+ -+ if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from -+ here. */ -+ UIP_STAT(++uip_stat.ip.drop); -+ UIP_STAT(++uip_stat.ip.protoerr); -+ UIP_LOG("ip: neither tcp nor icmp."); -+ goto drop; -+ } -+ -+ //icmp_input: -+ UIP_STAT(++uip_stat.icmp.recv); -+ -+ /* ICMP echo (i.e., ping) processing. This is simple, we only change -+ the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP -+ checksum before we return the packet. */ -+ if(ICMPBUF->type != ICMP_ECHO) { -+ UIP_STAT(++uip_stat.icmp.drop); -+ UIP_STAT(++uip_stat.icmp.typeerr); -+ UIP_LOG("icmp: not icmp echo."); -+ goto drop; -+ } -+ -+ /* If we are configured to use ping IP address assignment, we use -+ the destination IP address of this ping packet and assign it to -+ ourself. */ -+#if UIP_PINGADDRCONF -+ if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { -+ uip_hostaddr[0] = BUF->destipaddr[0]; -+ uip_hostaddr[1] = BUF->destipaddr[1]; -+ } -+#endif /* UIP_PINGADDRCONF */ -+ -+ ICMPBUF->type = ICMP_ECHO_REPLY; -+ -+ if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { -+ ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; -+ } else { -+ ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); -+ } -+ -+ /* Swap IP addresses. */ -+ tmp16 = BUF->destipaddr[0]; -+ BUF->destipaddr[0] = BUF->srcipaddr[0]; -+ BUF->srcipaddr[0] = tmp16; -+ tmp16 = BUF->destipaddr[1]; -+ BUF->destipaddr[1] = BUF->srcipaddr[1]; -+ BUF->srcipaddr[1] = tmp16; -+ -+ UIP_STAT(++uip_stat.icmp.sent); -+ goto send; -+ -+ /* End of IPv4 input header processing code. */ -+ -+ -+#if UIP_UDP -+ /* UDP input processing. */ -+ udp_input: -+ /* UDP processing is really just a hack. We don't do anything to the -+ UDP/IP headers, but let the UDP application do all the hard -+ work. If the application sets uip_slen, it has a packet to -+ send. */ -+#if UIP_UDP_CHECKSUMS -+ if(uip_udpchksum() != 0xffff) { -+ UIP_STAT(++uip_stat.udp.drop); -+ UIP_STAT(++uip_stat.udp.chkerr); -+ UIP_LOG("udp: bad checksum."); -+ goto drop; -+ } -+#endif /* UIP_UDP_CHECKSUMS */ -+ -+ /* Demultiplex this UDP packet between the UDP "connections". */ -+ for(uip_udp_conn = &uip_udp_conns[0]; -+ uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; -+ ++uip_udp_conn) { -+ if(uip_udp_conn->lport != 0 && -+ UDPBUF->destport == uip_udp_conn->lport && -+ (uip_udp_conn->rport == 0 || -+ UDPBUF->srcport == uip_udp_conn->rport) && -+ BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && -+ BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { -+ goto udp_found; -+ } -+ } -+ goto drop; -+ -+ udp_found: -+ uip_len = uip_len - 28; -+ uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; -+ uip_flags = UIP_NEWDATA; -+ uip_slen = 0; -+ UIP_UDP_APPCALL(); -+ udp_send: -+ if(uip_slen == 0) { -+ goto drop; -+ } -+ uip_len = uip_slen + 28; -+ -+ BUF->len[0] = (uip_len >> 8); -+ BUF->len[1] = (uip_len & 0xff); -+ -+ BUF->proto = UIP_PROTO_UDP; -+ -+ UDPBUF->udplen = HTONS(uip_slen + 8); -+ UDPBUF->udpchksum = 0; -+#if UIP_UDP_CHECKSUMS -+ /* Calculate UDP checksum. */ -+ UDPBUF->udpchksum = ~(uip_udpchksum()); -+ if(UDPBUF->udpchksum == 0) { -+ UDPBUF->udpchksum = 0xffff; -+ } -+#endif /* UIP_UDP_CHECKSUMS */ -+ -+ BUF->srcport = uip_udp_conn->lport; -+ BUF->destport = uip_udp_conn->rport; -+ -+ BUF->srcipaddr[0] = uip_hostaddr[0]; -+ BUF->srcipaddr[1] = uip_hostaddr[1]; -+ BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; -+ BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; -+ -+ uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; -+ goto ip_send_nolen; -+#endif /* UIP_UDP */ -+ -+ /* TCP input processing. */ -+ tcp_input: -+ UIP_STAT(++uip_stat.tcp.recv); -+ -+ /* Start of TCP input header processing code. */ -+ -+ if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP -+ checksum. */ -+ UIP_STAT(++uip_stat.tcp.drop); -+ UIP_STAT(++uip_stat.tcp.chkerr); -+ UIP_LOG("tcp: bad checksum."); -+ goto drop; -+ } -+ -+ /* Demultiplex this segment. */ -+ /* First check any active connections. */ -+ for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { -+ if(uip_connr->tcpstateflags != CLOSED && -+ BUF->destport == uip_connr->lport && -+ BUF->srcport == uip_connr->rport && -+ BUF->srcipaddr[0] == uip_connr->ripaddr[0] && -+ BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { -+ goto found; -+ } -+ } -+ -+ /* If we didn't find and active connection that expected the packet, -+ either this packet is an old duplicate, or this is a SYN packet -+ destined for a connection in LISTEN. If the SYN flag isn't set, -+ it is an old packet and we send a RST. */ -+ if((BUF->flags & TCP_CTL) != TCP_SYN) -+ goto reset; -+ -+ tmp16 = BUF->destport; -+ /* Next, check listening connections. */ -+ for(c = 0; c < UIP_LISTENPORTS; ++c) { -+ if(tmp16 == uip_listenports[c]) -+ goto found_listen; -+ } -+ -+ /* No matching connection found, so we send a RST packet. */ -+ UIP_STAT(++uip_stat.tcp.synrst); -+ reset: -+ -+ /* We do not send resets in response to resets. */ -+ if(BUF->flags & TCP_RST) -+ goto drop; -+ -+ UIP_STAT(++uip_stat.tcp.rst); -+ -+ BUF->flags = TCP_RST | TCP_ACK; -+ uip_len = 40; -+ BUF->tcpoffset = 5 << 4; -+ -+ /* Flip the seqno and ackno fields in the TCP header. */ -+ c = BUF->seqno[3]; -+ BUF->seqno[3] = BUF->ackno[3]; -+ BUF->ackno[3] = c; -+ -+ c = BUF->seqno[2]; -+ BUF->seqno[2] = BUF->ackno[2]; -+ BUF->ackno[2] = c; -+ -+ c = BUF->seqno[1]; -+ BUF->seqno[1] = BUF->ackno[1]; -+ BUF->ackno[1] = c; -+ -+ c = BUF->seqno[0]; -+ BUF->seqno[0] = BUF->ackno[0]; -+ BUF->ackno[0] = c; -+ -+ /* We also have to increase the sequence number we are -+ acknowledging. If the least significant byte overflowed, we need -+ to propagate the carry to the other bytes as well. */ -+ if(++BUF->ackno[3] == 0) { -+ if(++BUF->ackno[2] == 0) { -+ if(++BUF->ackno[1] == 0) { -+ ++BUF->ackno[0]; -+ } -+ } -+ } -+ -+ /* Swap port numbers. */ -+ tmp16 = BUF->srcport; -+ BUF->srcport = BUF->destport; -+ BUF->destport = tmp16; -+ -+ /* Swap IP addresses. */ -+ tmp16 = BUF->destipaddr[0]; -+ BUF->destipaddr[0] = BUF->srcipaddr[0]; -+ BUF->srcipaddr[0] = tmp16; -+ tmp16 = BUF->destipaddr[1]; -+ BUF->destipaddr[1] = BUF->srcipaddr[1]; -+ BUF->srcipaddr[1] = tmp16; -+ -+ -+ /* And send out the RST packet! */ -+ goto tcp_send_noconn; -+ -+ /* This label will be jumped to if we matched the incoming packet -+ with a connection in LISTEN. In that case, we should create a new -+ connection and send a SYNACK in return. */ -+ found_listen: -+ /* First we check if there are any connections avaliable. Unused -+ connections are kept in the same table as used connections, but -+ unused ones have the tcpstate set to CLOSED. Also, connections in -+ TIME_WAIT are kept track of and we'll use the oldest one if no -+ CLOSED connections are found. Thanks to Eddie C. Dost for a very -+ nice algorithm for the TIME_WAIT search. */ -+ uip_connr = 0; -+ for(c = 0; c < UIP_CONNS; ++c) { -+ if(uip_conns[c].tcpstateflags == CLOSED) { -+ uip_connr = &uip_conns[c]; -+ break; -+ } -+ if(uip_conns[c].tcpstateflags == TIME_WAIT) { -+ if(uip_connr == 0 || -+ uip_conns[c].timer > uip_connr->timer) { -+ uip_connr = &uip_conns[c]; -+ } -+ } -+ } -+ -+ if(uip_connr == 0) { -+ /* All connections are used already, we drop packet and hope that -+ the remote end will retransmit the packet at a time when we -+ have more spare connections. */ -+ UIP_STAT(++uip_stat.tcp.syndrop); -+ UIP_LOG("tcp: found no unused connections."); -+ goto drop; -+ } -+ uip_conn = uip_connr; -+ -+ /* Fill in the necessary fields for the new connection. */ -+ uip_connr->rto = uip_connr->timer = UIP_RTO; -+ uip_connr->sa = 0; -+ uip_connr->sv = 4; -+ uip_connr->nrtx = 0; -+ uip_connr->lport = BUF->destport; -+ uip_connr->rport = BUF->srcport; -+ uip_connr->ripaddr[0] = BUF->srcipaddr[0]; -+ uip_connr->ripaddr[1] = BUF->srcipaddr[1]; -+ uip_connr->tcpstateflags = SYN_RCVD; -+ -+ uip_connr->snd_nxt[0] = iss[0]; -+ uip_connr->snd_nxt[1] = iss[1]; -+ uip_connr->snd_nxt[2] = iss[2]; -+ uip_connr->snd_nxt[3] = iss[3]; -+ uip_connr->len = 1; -+ -+ /* rcv_nxt should be the seqno from the incoming packet + 1. */ -+ uip_connr->rcv_nxt[3] = BUF->seqno[3]; -+ uip_connr->rcv_nxt[2] = BUF->seqno[2]; -+ uip_connr->rcv_nxt[1] = BUF->seqno[1]; -+ uip_connr->rcv_nxt[0] = BUF->seqno[0]; -+ uip_add_rcv_nxt(1); -+ -+ /* Parse the TCP MSS option, if present. */ -+ if((BUF->tcpoffset & 0xf0) > 0x50) { -+ for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { -+ opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; -+ if(opt == 0x00) { -+ /* End of options. */ -+ break; -+ } else if(opt == 0x01) { -+ ++c; -+ /* NOP option. */ -+ } else if(opt == 0x02 && -+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { -+ /* An MSS option with the right option length. */ -+ tmp16 = ((unsigned short int)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | -+ (unsigned short int)uip_buf[40 + UIP_LLH_LEN + 3 + c]; -+ uip_connr->initialmss = uip_connr->mss = -+ tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; -+ -+ /* And we are done processing options. */ -+ break; -+ } else { -+ /* All other options have a length field, so that we easily -+ can skip past them. */ -+ if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { -+ /* If the length field is zero, the options are malformed -+ and we don't process them further. */ -+ break; -+ } -+ c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; -+ } -+ } -+ } -+ -+ /* Our response will be a SYNACK. */ -+#if UIP_ACTIVE_OPEN -+ tcp_send_synack: -+ BUF->flags = TCP_ACK; -+ -+ tcp_send_syn: -+ BUF->flags |= TCP_SYN; -+#else /* UIP_ACTIVE_OPEN */ -+ tcp_send_synack: -+ BUF->flags = TCP_SYN | TCP_ACK; -+#endif /* UIP_ACTIVE_OPEN */ -+ -+ /* We send out the TCP Maximum Segment Size option with our -+ SYNACK. */ -+ BUF->optdata[0] = 2; -+ BUF->optdata[1] = 4; -+ BUF->optdata[2] = (UIP_TCP_MSS) / 256; -+ BUF->optdata[3] = (UIP_TCP_MSS) & 255; -+ uip_len = 44; -+ BUF->tcpoffset = 6 << 4; -+ goto tcp_send; -+ -+ /* This label will be jumped to if we found an active connection. */ -+ found: -+ uip_conn = uip_connr; -+ uip_flags = 0; -+ -+ /* We do a very naive form of TCP reset processing; we just accept -+ any RST and kill our connection. We should in fact check if the -+ sequence number of this reset is wihtin our advertised window -+ before we accept the reset. */ -+ if(BUF->flags & TCP_RST) { -+ uip_connr->tcpstateflags = CLOSED; -+ UIP_LOG("tcp: got reset, aborting connection."); -+ uip_flags = UIP_ABORT; -+ UIP_APPCALL(); -+ goto drop; -+ } -+ /* Calculated the length of the data, if the application has sent -+ any data to us. */ -+ c = (BUF->tcpoffset >> 4) << 2; -+ /* uip_len will contain the length of the actual TCP data. This is -+ calculated by subtracing the length of the TCP header (in -+ c) and the length of the IP header (20 bytes). */ -+ uip_len = uip_len - c - 20; -+ -+ /* First, check if the sequence number of the incoming packet is -+ what we're expecting next. If not, we send out an ACK with the -+ correct numbers in. */ -+ if(uip_len > 0 && -+ (BUF->seqno[0] != uip_connr->rcv_nxt[0] || -+ BUF->seqno[1] != uip_connr->rcv_nxt[1] || -+ BUF->seqno[2] != uip_connr->rcv_nxt[2] || -+ BUF->seqno[3] != uip_connr->rcv_nxt[3])) { -+ goto tcp_send_ack; -+ } -+ -+ /* Next, check if the incoming segment acknowledges any outstanding -+ data. If so, we update the sequence number, reset the length of -+ the outstanding data, calculate RTT estimations, and reset the -+ retransmission timer. */ -+ if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { -+ uip_add32(uip_connr->snd_nxt, uip_connr->len); -+ if(BUF->ackno[0] == uip_acc32[0] && -+ BUF->ackno[1] == uip_acc32[1] && -+ BUF->ackno[2] == uip_acc32[2] && -+ BUF->ackno[3] == uip_acc32[3]) { -+ /* Update sequence number. */ -+ uip_connr->snd_nxt[0] = uip_acc32[0]; -+ uip_connr->snd_nxt[1] = uip_acc32[1]; -+ uip_connr->snd_nxt[2] = uip_acc32[2]; -+ uip_connr->snd_nxt[3] = uip_acc32[3]; -+ -+ -+ /* Do RTT estimation, unless we have done retransmissions. */ -+ if(uip_connr->nrtx == 0) { -+ signed char m; -+ m = uip_connr->rto - uip_connr->timer; -+ /* This is taken directly from VJs original code in his paper */ -+ m = m - (uip_connr->sa >> 3); -+ uip_connr->sa += m; -+ if(m < 0) { -+ m = -m; -+ } -+ m = m - (uip_connr->sv >> 2); -+ uip_connr->sv += m; -+ uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; -+ -+ } -+ /* Set the acknowledged flag. */ -+ uip_flags = UIP_ACKDATA; -+ /* Reset the retransmission timer. */ -+ uip_connr->timer = uip_connr->rto; -+ } -+ -+ } -+ -+ /* Do different things depending on in what state the connection is. */ -+ switch(uip_connr->tcpstateflags & TS_MASK) { -+ /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not -+ implemented, since we force the application to close when the -+ peer sends a FIN (hence the application goes directly from -+ ESTABLISHED to LAST_ACK). */ -+ case SYN_RCVD: -+ /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and -+ we are waiting for an ACK that acknowledges the data we sent -+ out the last time. Therefore, we want to have the UIP_ACKDATA -+ flag set. If so, we enter the ESTABLISHED state. */ -+ if(uip_flags & UIP_ACKDATA) { -+ uip_connr->tcpstateflags = ESTABLISHED; -+ uip_flags = UIP_CONNECTED; -+ uip_connr->len = 0; -+ if(uip_len > 0) { -+ uip_flags |= UIP_NEWDATA; -+ uip_add_rcv_nxt(uip_len); -+ } -+ uip_slen = 0; -+ UIP_APPCALL(); -+ goto appsend; -+ } -+ goto drop; -+#if UIP_ACTIVE_OPEN -+ case SYN_SENT: -+ /* In SYN_SENT, we wait for a SYNACK that is sent in response to -+ our SYN. The rcv_nxt is set to sequence number in the SYNACK -+ plus one, and we send an ACK. We move into the ESTABLISHED -+ state. */ -+ if((uip_flags & UIP_ACKDATA) && -+ BUF->flags == (TCP_SYN | TCP_ACK)) { -+ -+ /* Parse the TCP MSS option, if present. */ -+ if((BUF->tcpoffset & 0xf0) > 0x50) { -+ for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { -+ opt = uip_buf[40 + UIP_LLH_LEN + c]; -+ if(opt == 0x00) { -+ /* End of options. */ -+ break; -+ } else if(opt == 0x01) { -+ ++c; -+ /* NOP option. */ -+ } else if(opt == 0x02 && -+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { -+ /* An MSS option with the right option length. */ -+ tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | -+ uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; -+ uip_connr->initialmss = -+ uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; -+ -+ /* And we are done processing options. */ -+ break; -+ } else { -+ /* All other options have a length field, so that we easily -+ can skip past them. */ -+ if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { -+ /* If the length field is zero, the options are malformed -+ and we don't process them further. */ -+ break; -+ } -+ c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; -+ } -+ } -+ } -+ uip_connr->tcpstateflags = ESTABLISHED; -+ uip_connr->rcv_nxt[0] = BUF->seqno[0]; -+ uip_connr->rcv_nxt[1] = BUF->seqno[1]; -+ uip_connr->rcv_nxt[2] = BUF->seqno[2]; -+ uip_connr->rcv_nxt[3] = BUF->seqno[3]; -+ uip_add_rcv_nxt(1); -+ uip_flags = UIP_CONNECTED | UIP_NEWDATA; -+ uip_connr->len = 0; -+ uip_len = 0; -+ uip_slen = 0; -+ UIP_APPCALL(); -+ goto appsend; -+ } -+ goto reset; -+#endif /* UIP_ACTIVE_OPEN */ -+ -+ case ESTABLISHED: -+ /* In the ESTABLISHED state, we call upon the application to feed -+ data into the uip_buf. If the UIP_ACKDATA flag is set, the -+ application should put new data into the buffer, otherwise we are -+ retransmitting an old segment, and the application should put that -+ data into the buffer. -+ -+ If the incoming packet is a FIN, we should close the connection on -+ this side as well, and we send out a FIN and enter the LAST_ACK -+ state. We require that there is no outstanding data; otherwise the -+ sequence numbers will be screwed up. */ -+ -+ if(BUF->flags & TCP_FIN) { -+ if(uip_outstanding(uip_connr)) { -+ goto drop; -+ } -+ uip_add_rcv_nxt(1 + uip_len); -+ uip_flags = UIP_CLOSE; -+ if(uip_len > 0) { -+ uip_flags |= UIP_NEWDATA; -+ } -+ UIP_APPCALL(); -+ uip_connr->len = 1; -+ uip_connr->tcpstateflags = LAST_ACK; -+ uip_connr->nrtx = 0; -+ tcp_send_finack: -+ BUF->flags = TCP_FIN | TCP_ACK; -+ goto tcp_send_nodata; -+ } -+ -+ /* Check the URG flag. If this is set, the segment carries urgent -+ data that we must pass to the application. */ -+ if(BUF->flags & TCP_URG) { -+#if UIP_URGDATA > 0 -+ uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; -+ if(uip_urglen > uip_len) { -+ /* There is more urgent data in the next segment to come. */ -+ uip_urglen = uip_len; -+ } -+ uip_add_rcv_nxt(uip_urglen); -+ uip_len -= uip_urglen; -+ uip_urgdata = uip_appdata; -+ uip_appdata += uip_urglen; -+ } else { -+ uip_urglen = 0; -+#endif /* UIP_URGDATA > 0 */ -+ uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; -+ uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; -+ } -+ -+ -+ /* If uip_len > 0 we have TCP data in the packet, and we flag this -+ by setting the UIP_NEWDATA flag and update the sequence number -+ we acknowledge. If the application has stopped the dataflow -+ using uip_stop(), we must not accept any data packets from the -+ remote host. */ -+ if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { -+ uip_flags |= UIP_NEWDATA; -+ uip_add_rcv_nxt(uip_len); -+ } -+ -+ /* Check if the available buffer space advertised by the other end -+ is smaller than the initial MSS for this connection. If so, we -+ set the current MSS to the window size to ensure that the -+ application does not send more data than the other end can -+ handle. -+ -+ If the remote host advertises a zero window, we set the MSS to -+ the initial MSS so that the application will send an entire MSS -+ of data. This data will not be acknowledged by the receiver, -+ and the application will retransmit it. This is called the -+ "persistent timer" and uses the retransmission mechanim. -+ */ -+ tmp16 = ((unsigned short int)BUF->wnd[0] << 8) + (unsigned short int)BUF->wnd[1]; -+ if(tmp16 > uip_connr->initialmss || -+ tmp16 == 0) { -+ tmp16 = uip_connr->initialmss; -+ } -+ uip_connr->mss = tmp16; -+ -+ /* If this packet constitutes an ACK for outstanding data (flagged -+ by the UIP_ACKDATA flag, we should call the application since it -+ might want to send more data. If the incoming packet had data -+ from the peer (as flagged by the UIP_NEWDATA flag), the -+ application must also be notified. -+ -+ When the application is called, the global variable uip_len -+ contains the length of the incoming data. The application can -+ access the incoming data through the global pointer -+ uip_appdata, which usually points 40 bytes into the uip_buf -+ array. -+ -+ If the application wishes to send any data, this data should be -+ put into the uip_appdata and the length of the data should be -+ put into uip_len. If the application don't have any data to -+ send, uip_len must be set to 0. */ -+ if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { -+ uip_slen = 0; -+ UIP_APPCALL(); -+ -+ appsend: -+ -+ if(uip_flags & UIP_ABORT) { -+ uip_slen = 0; -+ uip_connr->tcpstateflags = CLOSED; -+ BUF->flags = TCP_RST | TCP_ACK; -+ goto tcp_send_nodata; -+ } -+ -+ if(uip_flags & UIP_CLOSE) { -+ uip_slen = 0; -+ uip_connr->len = 1; -+ uip_connr->tcpstateflags = FIN_WAIT_1; -+ uip_connr->nrtx = 0; -+ BUF->flags = TCP_FIN | TCP_ACK; -+ goto tcp_send_nodata; -+ } -+ -+ /* If uip_slen > 0, the application has data to be sent. */ -+ if(uip_slen > 0) { -+ -+ /* If the connection has acknowledged data, the contents of -+ the ->len variable should be discarded. */ -+ if((uip_flags & UIP_ACKDATA) != 0) { -+ uip_connr->len = 0; -+ } -+ -+ /* If the ->len variable is non-zero the connection has -+ already data in transit and cannot send anymore right -+ now. */ -+ if(uip_connr->len == 0) { -+ -+ /* The application cannot send more than what is allowed by -+ the mss (the minumum of the MSS and the available -+ window). */ -+ if(uip_slen > uip_connr->mss) { -+ uip_slen = uip_connr->mss; -+ } -+ -+ /* Remember how much data we send out now so that we know -+ when everything has been acknowledged. */ -+ uip_connr->len = uip_slen; -+ } else { -+ -+ /* If the application already had unacknowledged data, we -+ make sure that the application does not send (i.e., -+ retransmit) out more than it previously sent out. */ -+ uip_slen = uip_connr->len; -+ } -+ } else { -+ uip_connr->len = 0; -+ } -+ uip_connr->nrtx = 0; -+ apprexmit: -+ uip_appdata = uip_sappdata; -+ -+ /* If the application has data to be sent, or if the incoming -+ packet had new data in it, we must send out a packet. */ -+ if(uip_slen > 0 && uip_connr->len > 0) { -+ /* Add the length of the IP and TCP headers. */ -+ uip_len = uip_connr->len + UIP_TCPIP_HLEN; -+ /* We always set the ACK flag in response packets. */ -+ BUF->flags = TCP_ACK | TCP_PSH; -+ /* Send the packet. */ -+ goto tcp_send_noopts; -+ } -+ /* If there is no data to send, just send out a pure ACK if -+ there is newdata. */ -+ if(uip_flags & UIP_NEWDATA) { -+ uip_len = UIP_TCPIP_HLEN; -+ BUF->flags = TCP_ACK; -+ goto tcp_send_noopts; -+ } -+ } -+ goto drop; -+ case LAST_ACK: -+ /* We can close this connection if the peer has acknowledged our -+ FIN. This is indicated by the UIP_ACKDATA flag. */ -+ if(uip_flags & UIP_ACKDATA) { -+ uip_connr->tcpstateflags = CLOSED; -+ uip_flags = UIP_CLOSE; -+ UIP_APPCALL(); -+ } -+ break; -+ -+ case FIN_WAIT_1: -+ /* The application has closed the connection, but the remote host -+ hasn't closed its end yet. Thus we do nothing but wait for a -+ FIN from the other side. */ -+ if(uip_len > 0) { -+ uip_add_rcv_nxt(uip_len); -+ } -+ if(BUF->flags & TCP_FIN) { -+ if(uip_flags & UIP_ACKDATA) { -+ uip_connr->tcpstateflags = TIME_WAIT; -+ uip_connr->timer = 0; -+ uip_connr->len = 0; -+ } else { -+ uip_connr->tcpstateflags = CLOSING; -+ } -+ uip_add_rcv_nxt(1); -+ uip_flags = UIP_CLOSE; -+ UIP_APPCALL(); -+ goto tcp_send_ack; -+ } else if(uip_flags & UIP_ACKDATA) { -+ uip_connr->tcpstateflags = FIN_WAIT_2; -+ uip_connr->len = 0; -+ goto drop; -+ } -+ if(uip_len > 0) { -+ goto tcp_send_ack; -+ } -+ goto drop; -+ -+ case FIN_WAIT_2: -+ if(uip_len > 0) { -+ uip_add_rcv_nxt(uip_len); -+ } -+ if(BUF->flags & TCP_FIN) { -+ uip_connr->tcpstateflags = TIME_WAIT; -+ uip_connr->timer = 0; -+ uip_add_rcv_nxt(1); -+ uip_flags = UIP_CLOSE; -+ UIP_APPCALL(); -+ goto tcp_send_ack; -+ } -+ if(uip_len > 0) { -+ goto tcp_send_ack; -+ } -+ goto drop; -+ -+ case TIME_WAIT: -+ goto tcp_send_ack; -+ -+ case CLOSING: -+ if(uip_flags & UIP_ACKDATA) { -+ uip_connr->tcpstateflags = TIME_WAIT; -+ uip_connr->timer = 0; -+ } -+ } -+ goto drop; -+ -+ -+ /* We jump here when we are ready to send the packet, and just want -+ to set the appropriate TCP sequence numbers in the TCP header. */ -+ tcp_send_ack: -+ BUF->flags = TCP_ACK; -+ tcp_send_nodata: -+ uip_len = 40; -+ tcp_send_noopts: -+ BUF->tcpoffset = 5 << 4; -+ tcp_send: -+ /* We're done with the input processing. We are now ready to send a -+ reply. Our job is to fill in all the fields of the TCP and IP -+ headers before calculating the checksum and finally send the -+ packet. */ -+ BUF->ackno[0] = uip_connr->rcv_nxt[0]; -+ BUF->ackno[1] = uip_connr->rcv_nxt[1]; -+ BUF->ackno[2] = uip_connr->rcv_nxt[2]; -+ BUF->ackno[3] = uip_connr->rcv_nxt[3]; -+ -+ BUF->seqno[0] = uip_connr->snd_nxt[0]; -+ BUF->seqno[1] = uip_connr->snd_nxt[1]; -+ BUF->seqno[2] = uip_connr->snd_nxt[2]; -+ BUF->seqno[3] = uip_connr->snd_nxt[3]; -+ -+ BUF->proto = UIP_PROTO_TCP; -+ -+ BUF->srcport = uip_connr->lport; -+ BUF->destport = uip_connr->rport; -+ -+ BUF->srcipaddr[0] = uip_hostaddr[0]; -+ BUF->srcipaddr[1] = uip_hostaddr[1]; -+ BUF->destipaddr[0] = uip_connr->ripaddr[0]; -+ BUF->destipaddr[1] = uip_connr->ripaddr[1]; -+ -+ -+ if(uip_connr->tcpstateflags & UIP_STOPPED) { -+ /* If the connection has issued uip_stop(), we advertise a zero -+ window so that the remote host will stop sending data. */ -+ BUF->wnd[0] = BUF->wnd[1] = 0; -+ } else { -+ BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); -+ BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); -+ } -+ -+ tcp_send_noconn: -+ -+ BUF->len[0] = (uip_len >> 8); -+ BUF->len[1] = (uip_len & 0xff); -+ -+ /* Calculate TCP checksum. */ -+ BUF->tcpchksum = 0; -+ BUF->tcpchksum = ~(uip_tcpchksum()); -+ -+ //ip_send_nolen: -+ -+ BUF->vhl = 0x45; -+ BUF->tos = 0; -+ BUF->ipoffset[0] = BUF->ipoffset[1] = 0; -+ BUF->ttl = UIP_TTL; -+ ++ipid; -+ BUF->ipid[0] = ipid >> 8; -+ BUF->ipid[1] = ipid & 0xff; -+ -+ /* Calculate IP checksum. */ -+ BUF->ipchksum = 0; -+ BUF->ipchksum = ~(uip_ipchksum()); -+ -+ UIP_STAT(++uip_stat.tcp.sent); -+ send: -+ UIP_STAT(++uip_stat.ip.sent); -+ /* Return and let the caller do the actual transmission. */ -+ return; -+ drop: -+ uip_len = 0; -+ return; -+} -+/*-----------------------------------------------------------------------------------*/ -+/*unsigned short int -+htons(unsigned short int val) -+{ -+ return HTONS(val); -+}*/ -+/*-----------------------------------------------------------------------------------*/ -+/** @} */ ---- /dev/null -+++ b/net/uip-0.9/uip.h -@@ -0,0 +1,1066 @@ -+/** -+ * \addtogroup uip -+ * @{ -+ */ -+ -+/** -+ * \file -+ * Header file for the uIP TCP/IP stack. -+ * \author Adam Dunkels <adam@dunkels.com> -+ * -+ * The uIP TCP/IP stack header file contains definitions for a number -+ * of C macros that are used by uIP programs as well as internal uIP -+ * structures, TCP/IP header structures and function declarations. -+ * -+ */ -+ -+ -+/* -+ * Copyright (c) 2001-2003, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ -+ * -+ */ -+ -+#ifndef __UIP_H__ -+#define __UIP_H__ -+#include <linux/types.h> -+#include <linux/string.h> -+#include <linux/ctype.h> -+#include <malloc.h> -+#include <common.h> -+ -+ -+#include "uipopt.h" -+ -+/*-----------------------------------------------------------------------------------*/ -+/* First, the functions that should be called from the -+ * system. Initialization, the periodic timer and incoming packets are -+ * handled by the following three functions. -+ */ -+ -+/** -+ * \defgroup uipconffunc uIP configuration functions -+ * @{ -+ * -+ * The uIP configuration functions are used for setting run-time -+ * parameters in uIP such as IP addresses. -+ */ -+ -+/** -+ * Set the IP address of this host. -+ * -+ * The IP address is represented as a 4-byte array where the first -+ * octet of the IP address is put in the first member of the 4-byte -+ * array. -+ * -+ * \param addr A pointer to a 4-byte representation of the IP address. -+ * -+ * \hideinitializer -+ */ -+#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ -+ uip_hostaddr[1] = addr[1]; } while(0) -+ -+/** -+ * Get the IP address of this host. -+ * -+ * The IP address is represented as a 4-byte array where the first -+ * octet of the IP address is put in the first member of the 4-byte -+ * array. -+ * -+ * \param addr A pointer to a 4-byte array that will be filled in with -+ * the currently configured IP address. -+ * -+ * \hideinitializer -+ */ -+#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ -+ addr[1] = uip_hostaddr[1]; } while(0) -+ -+/** @} */ -+ -+/** -+ * \defgroup uipinit uIP initialization functions -+ * @{ -+ * -+ * The uIP initialization functions are used for booting uIP. -+ */ -+ -+/** -+ * uIP initialization function. -+ * -+ * This function should be called at boot up to initilize the uIP -+ * TCP/IP stack. -+ */ -+void uip_init(void); -+ -+/** @} */ -+ -+/** -+ * \defgroup uipdevfunc uIP device driver functions -+ * @{ -+ * -+ * These functions are used by a network device driver for interacting -+ * with uIP. -+ */ -+ -+/** -+ * Process an incoming packet. -+ * -+ * This function should be called when the device driver has received -+ * a packet from the network. The packet from the device driver must -+ * be present in the uip_buf buffer, and the length of the packet -+ * should be placed in the uip_len variable. -+ * -+ * When the function returns, there may be an outbound packet placed -+ * in the uip_buf packet buffer. If so, the uip_len variable is set to -+ * the length of the packet. If no packet is to be sent out, the -+ * uip_len variable is set to 0. -+ * -+ * The usual way of calling the function is presented by the source -+ * code below. -+ \code -+ uip_len = devicedriver_poll(); -+ if(uip_len > 0) { -+ uip_input(); -+ if(uip_len > 0) { -+ devicedriver_send(); -+ } -+ } -+ \endcode -+ * -+ * \note If you are writing a uIP device driver that needs ARP -+ * (Address Resolution Protocol), e.g., when running uIP over -+ * Ethernet, you will need to call the uIP ARP code before calling -+ * this function: -+ \code -+ #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) -+ uip_len = ethernet_devicedrver_poll(); -+ if(uip_len > 0) { -+ if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { -+ uip_arp_ipin(); -+ uip_input(); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ ethernet_devicedriver_send(); -+ } -+ } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { -+ uip_arp_arpin(); -+ if(uip_len > 0) { -+ ethernet_devicedriver_send(); -+ } -+ } -+ \endcode -+ * -+ * \hideinitializer -+ */ -+#define uip_input() uip_process(UIP_DATA) -+ -+/** -+ * Periodic processing for a connection identified by its number. -+ * -+ * This function does the necessary periodic processing (timers, -+ * polling) for a uIP TCP conneciton, and should be called when the -+ * periodic uIP timer goes off. It should be called for every -+ * connection, regardless of whether they are open of closed. -+ * -+ * When the function returns, it may have an outbound packet waiting -+ * for service in the uIP packet buffer, and if so the uip_len -+ * variable is set to a value larger than zero. The device driver -+ * should be called to send out the packet. -+ * -+ * The ususal way of calling the function is through a for() loop like -+ * this: -+ \code -+ for(i = 0; i < UIP_CONNS; ++i) { -+ uip_periodic(i); -+ if(uip_len > 0) { -+ devicedriver_send(); -+ } -+ } -+ \endcode -+ * -+ * \note If you are writing a uIP device driver that needs ARP -+ * (Address Resolution Protocol), e.g., when running uIP over -+ * Ethernet, you will need to call the uip_arp_out() function before -+ * calling the device driver: -+ \code -+ for(i = 0; i < UIP_CONNS; ++i) { -+ uip_periodic(i); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ ethernet_devicedriver_send(); -+ } -+ } -+ \endcode -+ * -+ * \param conn The number of the connection which is to be periodically polled. -+ * -+ * \hideinitializer -+ */ -+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ -+ uip_process(UIP_TIMER); } while (0) -+ -+/** -+ * Periodic processing for a connection identified by a pointer to its structure. -+ * -+ * Same as uip_periodic() but takes a pointer to the actual uip_conn -+ * struct instead of an integer as its argument. This function can be -+ * used to force periodic processing of a specific connection. -+ * -+ * \param conn A pointer to the uip_conn struct for the connection to -+ * be processed. -+ * -+ * \hideinitializer -+ */ -+#define uip_periodic_conn(conn) do { uip_conn = conn; \ -+ uip_process(UIP_TIMER); } while (0) -+ -+#if UIP_UDP -+/** -+ * Periodic processing for a UDP connection identified by its number. -+ * -+ * This function is essentially the same as uip_prerioic(), but for -+ * UDP connections. It is called in a similar fashion as the -+ * uip_periodic() function: -+ \code -+ for(i = 0; i < UIP_UDP_CONNS; i++) { -+ uip_udp_periodic(i); -+ if(uip_len > 0) { -+ devicedriver_send(); -+ } -+ } -+ \endcode -+ * -+ * \note As for the uip_periodic() function, special care has to be -+ * taken when using uIP together with ARP and Ethernet: -+ \code -+ for(i = 0; i < UIP_UDP_CONNS; i++) { -+ uip_udp_periodic(i); -+ if(uip_len > 0) { -+ uip_arp_out(); -+ ethernet_devicedriver_send(); -+ } -+ } -+ \endcode -+ * -+ * \param conn The number of the UDP connection to be processed. -+ * -+ * \hideinitializer -+ */ -+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ -+ uip_process(UIP_UDP_TIMER); } while (0) -+ -+/** -+ * Periodic processing for a UDP connection identified by a pointer to -+ * its structure. -+ * -+ * Same as uip_udp_periodic() but takes a pointer to the actual -+ * uip_conn struct instead of an integer as its argument. This -+ * function can be used to force periodic processing of a specific -+ * connection. -+ * -+ * \param conn A pointer to the uip_udp_conn struct for the connection -+ * to be processed. -+ * -+ * \hideinitializer -+ */ -+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ -+ uip_process(UIP_UDP_TIMER); } while (0) -+ -+ -+#endif /* UIP_UDP */ -+ -+/** -+ * The uIP packet buffer. -+ * -+ * The uip_buf array is used to hold incoming and outgoing -+ * packets. The device driver should place incoming data into this -+ * buffer. When sending data, the device driver should read the link -+ * level headers and the TCP/IP headers from this buffer. The size of -+ * the link level headers is configured by the UIP_LLH_LEN define. -+ * -+ * \note The application data need not be placed in this buffer, so -+ * the device driver must read it from the place pointed to by the -+ * uip_appdata pointer as illustrated by the following example: -+ \code -+ void -+ devicedriver_send(void) -+ { -+ hwsend(&uip_buf[0], UIP_LLH_LEN); -+ hwsend(&uip_buf[UIP_LLH_LEN], 40); -+ hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); -+ } -+ \endcode -+ */ -+extern u8_t uip_buf[UIP_BUFSIZE+2]; -+ -+/** @} */ -+ -+/*-----------------------------------------------------------------------------------*/ -+/* Functions that are used by the uIP application program. Opening and -+ * closing connections, sending and receiving data, etc. is all -+ * handled by the functions below. -+*/ -+/** -+ * \defgroup uipappfunc uIP application functions -+ * @{ -+ * -+ * Functions used by an application running of top of uIP. -+ */ -+ -+/** -+ * Start listening to the specified port. -+ * -+ * \note Since this function expects the port number in network byte -+ * order, a conversion using HTONS() or htons() is necessary. -+ * -+ \code -+ uip_listen(HTONS(80)); -+ \endcode -+ * -+ * \param port A 16-bit port number in network byte order. -+ */ -+void uip_listen(u16_t port); -+ -+/** -+ * Stop listening to the specified port. -+ * -+ * \note Since this function expects the port number in network byte -+ * order, a conversion using HTONS() or htons() is necessary. -+ * -+ \code -+ uip_unlisten(HTONS(80)); -+ \endcode -+ * -+ * \param port A 16-bit port number in network byte order. -+ */ -+void uip_unlisten(u16_t port); -+ -+/** -+ * Connect to a remote host using TCP. -+ * -+ * This function is used to start a new connection to the specified -+ * port on the specied host. It allocates a new connection identifier, -+ * sets the connection to the SYN_SENT state and sets the -+ * retransmission timer to 0. This will cause a TCP SYN segment to be -+ * sent out the next time this connection is periodically processed, -+ * which usually is done within 0.5 seconds after the call to -+ * uip_connect(). -+ * -+ * \note This function is avaliable only if support for active open -+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. -+ * -+ * \note Since this function requires the port number to be in network -+ * byte order, a convertion using HTONS() or htons() is necessary. -+ * -+ \code -+ u16_t ipaddr[2]; -+ -+ uip_ipaddr(ipaddr, 192,168,1,2); -+ uip_connect(ipaddr, HTONS(80)); -+ \endcode -+ * -+ * \param ripaddr A pointer to a 4-byte array representing the IP -+ * address of the remote hot. -+ * -+ * \param port A 16-bit port number in network byte order. -+ * -+ * \return A pointer to the uIP connection identifier for the new connection, -+ * or NULL if no connection could be allocated. -+ * -+ */ -+struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); -+ -+ -+ -+/** -+ * \internal -+ * -+ * Check if a connection has outstanding (i.e., unacknowledged) data. -+ * -+ * \param conn A pointer to the uip_conn structure for the connection. -+ * -+ * \hideinitializer -+ */ -+#define uip_outstanding(conn) ((conn)->len) -+ -+/** -+ * Send data on the current connection. -+ * -+ * This function is used to send out a single segment of TCP -+ * data. Only applications that have been invoked by uIP for event -+ * processing can send data. -+ * -+ * The amount of data that actually is sent out after a call to this -+ * funcion is determined by the maximum amount of data TCP allows. uIP -+ * will automatically crop the data so that only the appropriate -+ * amount of data is sent. The function uip_mss() can be used to query -+ * uIP for the amount of data that actually will be sent. -+ * -+ * \note This function does not guarantee that the sent data will -+ * arrive at the destination. If the data is lost in the network, the -+ * application will be invoked with the uip_rexmit() event being -+ * set. The application will then have to resend the data using this -+ * function. -+ * -+ * \param data A pointer to the data which is to be sent. -+ * -+ * \param len The maximum amount of data bytes to be sent. -+ * -+ * \hideinitializer -+ */ -+#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) -+ -+/** -+ * The length of any incoming data that is currently avaliable (if avaliable) -+ * in the uip_appdata buffer. -+ * -+ * The test function uip_data() must first be used to check if there -+ * is any data available at all. -+ * -+ * \hideinitializer -+ */ -+#define uip_datalen() uip_len -+ -+/** -+ * The length of any out-of-band data (urgent data) that has arrived -+ * on the connection. -+ * -+ * \note The configuration parameter UIP_URGDATA must be set for this -+ * function to be enabled. -+ * -+ * \hideinitializer -+ */ -+#define uip_urgdatalen() uip_urglen -+ -+/** -+ * Close the current connection. -+ * -+ * This function will close the current connection in a nice way. -+ * -+ * \hideinitializer -+ */ -+#define uip_close() (uip_flags = UIP_CLOSE) -+ -+/** -+ * Abort the current connection. -+ * -+ * This function will abort (reset) the current connection, and is -+ * usually used when an error has occured that prevents using the -+ * uip_close() function. -+ * -+ * \hideinitializer -+ */ -+#define uip_abort() (uip_flags = UIP_ABORT) -+ -+/** -+ * Tell the sending host to stop sending data. -+ * -+ * This function will close our receiver's window so that we stop -+ * receiving data for the current connection. -+ * -+ * \hideinitializer -+ */ -+#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) -+ -+/** -+ * Find out if the current connection has been previously stopped with -+ * uip_stop(). -+ * -+ * \hideinitializer -+ */ -+#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) -+ -+/** -+ * Restart the current connection, if is has previously been stopped -+ * with uip_stop(). -+ * -+ * This function will open the receiver's window again so that we -+ * start receiving data for the current connection. -+ * -+ * \hideinitializer -+ */ -+#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ -+ uip_conn->tcpstateflags &= ~UIP_STOPPED; \ -+ } while(0) -+ -+ -+/* uIP tests that can be made to determine in what state the current -+ connection is, and what the application function should do. */ -+ -+/** -+ * Is new incoming data available? -+ * -+ * Will reduce to non-zero if there is new data for the application -+ * present at the uip_appdata pointer. The size of the data is -+ * avaliable through the uip_len variable. -+ * -+ * \hideinitializer -+ */ -+#define uip_newdata() (uip_flags & UIP_NEWDATA) -+ -+/** -+ * Has previously sent data been acknowledged? -+ * -+ * Will reduce to non-zero if the previously sent data has been -+ * acknowledged by the remote host. This means that the application -+ * can send new data. -+ * -+ * \hideinitializer -+ */ -+#define uip_acked() (uip_flags & UIP_ACKDATA) -+ -+/** -+ * Has the connection just been connected? -+ * -+ * Reduces to non-zero if the current connection has been connected to -+ * a remote host. This will happen both if the connection has been -+ * actively opened (with uip_connect()) or passively opened (with -+ * uip_listen()). -+ * -+ * \hideinitializer -+ */ -+#define uip_connected() (uip_flags & UIP_CONNECTED) -+ -+/** -+ * Has the connection been closed by the other end? -+ * -+ * Is non-zero if the connection has been closed by the remote -+ * host. The application may then do the necessary clean-ups. -+ * -+ * \hideinitializer -+ */ -+#define uip_closed() (uip_flags & UIP_CLOSE) -+ -+/** -+ * Has the connection been aborted by the other end? -+ * -+ * Non-zero if the current connection has been aborted (reset) by the -+ * remote host. -+ * -+ * \hideinitializer -+ */ -+#define uip_aborted() (uip_flags & UIP_ABORT) -+ -+/** -+ * Has the connection timed out? -+ * -+ * Non-zero if the current connection has been aborted due to too many -+ * retransmissions. -+ * -+ * \hideinitializer -+ */ -+#define uip_timedout() (uip_flags & UIP_TIMEDOUT) -+ -+/** -+ * Do we need to retransmit previously data? -+ * -+ * Reduces to non-zero if the previously sent data has been lost in -+ * the network, and the application should retransmit it. The -+ * application should send the exact same data as it did the last -+ * time, using the uip_send() function. -+ * -+ * \hideinitializer -+ */ -+#define uip_rexmit() (uip_flags & UIP_REXMIT) -+ -+/** -+ * Is the connection being polled by uIP? -+ * -+ * Is non-zero if the reason the application is invoked is that the -+ * current connection has been idle for a while and should be -+ * polled. -+ * -+ * The polling event can be used for sending data without having to -+ * wait for the remote host to send data. -+ * -+ * \hideinitializer -+ */ -+#define uip_poll() (uip_flags & UIP_POLL) -+ -+/** -+ * Get the initial maxium segment size (MSS) of the current -+ * connection. -+ * -+ * \hideinitializer -+ */ -+#define uip_initialmss() (uip_conn->initialmss) -+ -+/** -+ * Get the current maxium segment size that can be sent on the current -+ * connection. -+ * -+ * The current maxiumum segment size that can be sent on the -+ * connection is computed from the receiver's window and the MSS of -+ * the connection (which also is available by calling -+ * uip_initialmss()). -+ * -+ * \hideinitializer -+ */ -+#define uip_mss() (uip_conn->mss) -+ -+/** -+ * Set up a new UDP connection. -+ * -+ * \param ripaddr A pointer to a 4-byte structure representing the IP -+ * address of the remote host. -+ * -+ * \param rport The remote port number in network byte order. -+ * -+ * \return The uip_udp_conn structure for the new connection or NULL -+ * if no connection could be allocated. -+ */ -+struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); -+ -+/** -+ * Removed a UDP connection. -+ * -+ * \param conn A pointer to the uip_udp_conn structure for the connection. -+ * -+ * \hideinitializer -+ */ -+#define uip_udp_remove(conn) (conn)->lport = 0 -+ -+/** -+ * Send a UDP datagram of length len on the current connection. -+ * -+ * This function can only be called in response to a UDP event (poll -+ * or newdata). The data must be present in the uip_buf buffer, at the -+ * place pointed to by the uip_appdata pointer. -+ * -+ * \param len The length of the data in the uip_buf buffer. -+ * -+ * \hideinitializer -+ */ -+#define uip_udp_send(len) uip_slen = (len) -+ -+/** @} */ -+ -+/* uIP convenience and converting functions. */ -+ -+/** -+ * \defgroup uipconvfunc uIP conversion functions -+ * @{ -+ * -+ * These functions can be used for converting between different data -+ * formats used by uIP. -+ */ -+ -+/** -+ * Pack an IP address into a 4-byte array which is used by uIP to -+ * represent IP addresses. -+ * -+ * Example: -+ \code -+ u16_t ipaddr[2]; -+ -+ uip_ipaddr(&ipaddr, 192,168,1,2); -+ \endcode -+ * -+ * \param addr A pointer to a 4-byte array that will be filled in with -+ * the IP addres. -+ * \param addr0 The first octet of the IP address. -+ * \param addr1 The second octet of the IP address. -+ * \param addr2 The third octet of the IP address. -+ * \param addr3 The forth octet of the IP address. -+ * -+ * \hideinitializer -+ */ -+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ -+ (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ -+ (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ -+ } while(0) -+ -+/** -+ * Convert 16-bit quantity from host byte order to network byte order. -+ * -+ * This macro is primarily used for converting constants from host -+ * byte order to network byte order. For converting variables to -+ * network byte order, use the htons() function instead. -+ * -+ * \hideinitializer -+ */ -+#ifndef HTONS -+# if BYTE_ORDER == BIG_ENDIAN -+# define HTONS(n) (n) -+# else /* BYTE_ORDER == BIG_ENDIAN */ -+# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) -+# endif /* BYTE_ORDER == BIG_ENDIAN */ -+#endif /* HTONS */ -+ -+/** -+ * Convert 16-bit quantity from host byte order to network byte order. -+ * -+ * This function is primarily used for converting variables from host -+ * byte order to network byte order. For converting constants to -+ * network byte order, use the HTONS() macro instead. -+ */ -+#ifndef htons -+u16_t htons(u16_t val); -+#endif /* htons */ -+ -+/** @} */ -+ -+/** -+ * Pointer to the application data in the packet buffer. -+ * -+ * This pointer points to the application data when the application is -+ * called. If the application wishes to send data, the application may -+ * use this space to write the data into before calling uip_send(). -+ */ -+extern volatile u8_t *uip_appdata; -+extern volatile u8_t *uip_sappdata; -+ -+#if UIP_URGDATA > 0 -+/* u8_t *uip_urgdata: -+ * -+ * This pointer points to any urgent data that has been received. Only -+ * present if compiled with support for urgent data (UIP_URGDATA). -+ */ -+extern volatile u8_t *uip_urgdata; -+#endif /* UIP_URGDATA > 0 */ -+ -+ -+/* u[8|16]_t uip_len: -+ * -+ * When the application is called, uip_len contains the length of any -+ * new data that has been received from the remote host. The -+ * application should set this variable to the size of any data that -+ * the application wishes to send. When the network device driver -+ * output function is called, uip_len should contain the length of the -+ * outgoing packet. -+ */ -+extern volatile u16_t uip_len, uip_slen; -+ -+#if UIP_URGDATA > 0 -+extern volatile u8_t uip_urglen, uip_surglen; -+#endif /* UIP_URGDATA > 0 */ -+ -+ -+/** -+ * Representation of a uIP TCP connection. -+ * -+ * The uip_conn structure is used for identifying a connection. All -+ * but one field in the structure are to be considered read-only by an -+ * application. The only exception is the appstate field whos purpose -+ * is to let the application store application-specific state (e.g., -+ * file pointers) for the connection. The size of this field is -+ * configured in the "uipopt.h" header file. -+ */ -+struct uip_conn { -+ u16_t ripaddr[2]; /**< The IP address of the remote host. */ -+ -+ u16_t lport; /**< The local TCP port, in network byte order. */ -+ u16_t rport; /**< The local remote TCP port, in network byte -+ order. */ -+ -+ u8_t rcv_nxt[4]; /**< The sequence number that we expect to -+ receive next. */ -+ u8_t snd_nxt[4]; /**< The sequence number that was last sent by -+ us. */ -+ u16_t len; /**< Length of the data that was previously sent. */ -+ u16_t mss; /**< Current maximum segment size for the -+ connection. */ -+ u16_t initialmss; /**< Initial maximum segment size for the -+ connection. */ -+ u8_t sa; /**< Retransmission time-out calculation state -+ variable. */ -+ u8_t sv; /**< Retransmission time-out calculation state -+ variable. */ -+ u8_t rto; /**< Retransmission time-out. */ -+ u8_t tcpstateflags; /**< TCP state and flags. */ -+ u8_t timer; /**< The retransmission timer. */ -+ u8_t nrtx; /**< The number of retransmissions for the last -+ segment sent. */ -+ -+ /** The application state. */ -+ u8_t appstate[UIP_APPSTATE_SIZE]; -+}; -+ -+ -+/* Pointer to the current connection. */ -+extern struct uip_conn *uip_conn; -+/* The array containing all uIP connections. */ -+extern struct uip_conn uip_conns[UIP_CONNS]; -+/** -+ * \addtogroup uiparch -+ * @{ -+ */ -+ -+/** -+ * 4-byte array used for the 32-bit sequence number calculations. -+ */ -+extern volatile u8_t uip_acc32[4]; -+ -+/** @} */ -+ -+ -+#if UIP_UDP -+/** -+ * Representation of a uIP UDP connection. -+ */ -+struct uip_udp_conn { -+ u16_t ripaddr[2]; /**< The IP address of the remote peer. */ -+ u16_t lport; /**< The local port number in network byte order. */ -+ u16_t rport; /**< The remote port number in network byte order. */ -+}; -+ -+extern struct uip_udp_conn *uip_udp_conn; -+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -+#endif /* UIP_UDP */ -+ -+/** -+ * The structure holding the TCP/IP statistics that are gathered if -+ * UIP_STATISTICS is set to 1. -+ * -+ */ -+struct uip_stats { -+ struct { -+ uip_stats_t drop; /**< Number of dropped packets at the IP -+ layer. */ -+ uip_stats_t recv; /**< Number of received packets at the IP -+ layer. */ -+ uip_stats_t sent; /**< Number of sent packets at the IP -+ layer. */ -+ uip_stats_t vhlerr; /**< Number of packets dropped due to wrong -+ IP version or header length. */ -+ uip_stats_t hblenerr; /**< Number of packets dropped due to wrong -+ IP length, high byte. */ -+ uip_stats_t lblenerr; /**< Number of packets dropped due to wrong -+ IP length, low byte. */ -+ uip_stats_t fragerr; /**< Number of packets dropped since they -+ were IP fragments. */ -+ uip_stats_t chkerr; /**< Number of packets dropped due to IP -+ checksum errors. */ -+ uip_stats_t protoerr; /**< Number of packets dropped since they -+ were neither ICMP, UDP nor TCP. */ -+ } ip; /**< IP statistics. */ -+ struct { -+ uip_stats_t drop; /**< Number of dropped ICMP packets. */ -+ uip_stats_t recv; /**< Number of received ICMP packets. */ -+ uip_stats_t sent; /**< Number of sent ICMP packets. */ -+ uip_stats_t typeerr; /**< Number of ICMP packets with a wrong -+ type. */ -+ } icmp; /**< ICMP statistics. */ -+ struct { -+ uip_stats_t drop; /**< Number of dropped TCP segments. */ -+ uip_stats_t recv; /**< Number of recived TCP segments. */ -+ uip_stats_t sent; /**< Number of sent TCP segments. */ -+ uip_stats_t chkerr; /**< Number of TCP segments with a bad -+ checksum. */ -+ uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK -+ number. */ -+ uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ -+ uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ -+ uip_stats_t syndrop; /**< Number of dropped SYNs due to too few -+ connections was avaliable. */ -+ uip_stats_t synrst; /**< Number of SYNs for closed ports, -+ triggering a RST. */ -+ } tcp; /**< TCP statistics. */ -+}; -+ -+/** -+ * The uIP TCP/IP statistics. -+ * -+ * This is the variable in which the uIP TCP/IP statistics are gathered. -+ */ -+extern struct uip_stats uip_stat; -+ -+ -+/*-----------------------------------------------------------------------------------*/ -+/* All the stuff below this point is internal to uIP and should not be -+ * used directly by an application or by a device driver. -+ */ -+/*-----------------------------------------------------------------------------------*/ -+/* u8_t uip_flags: -+ * -+ * When the application is called, uip_flags will contain the flags -+ * that are defined in this file. Please read below for more -+ * infomation. -+ */ -+extern volatile u8_t uip_flags; -+ -+/* The following flags may be set in the global variable uip_flags -+ before calling the application callback. The UIP_ACKDATA and -+ UIP_NEWDATA flags may both be set at the same time, whereas the -+ others are mutualy exclusive. Note that these flags should *NOT* be -+ accessed directly, but through the uIP functions/macros. */ -+ -+#define UIP_ACKDATA 1 /* Signifies that the outstanding data was -+ acked and the application should send -+ out new data instead of retransmitting -+ the last data. */ -+#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent -+ us new data. */ -+#define UIP_REXMIT 4 /* Tells the application to retransmit the -+ data that was last sent. */ -+#define UIP_POLL 8 /* Used for polling the application, to -+ check if the application has data that -+ it wants to send. */ -+#define UIP_CLOSE 16 /* The remote host has closed the -+ connection, thus the connection has -+ gone away. Or the application signals -+ that it wants to close the -+ connection. */ -+#define UIP_ABORT 32 /* The remote host has aborted the -+ connection, thus the connection has -+ gone away. Or the application signals -+ that it wants to abort the -+ connection. */ -+#define UIP_CONNECTED 64 /* We have got a connection from a remote -+ host and have set up a new connection -+ for it, or an active connection has -+ been successfully established. */ -+ -+#define UIP_TIMEDOUT 128 /* The connection has been aborted due to -+ too many retransmissions. */ -+ -+ -+/* uip_process(flag): -+ * -+ * The actual uIP function which does all the work. -+ */ -+void uip_process(u8_t flag); -+ -+/* The following flags are passed as an argument to the uip_process() -+ function. They are used to distinguish between the two cases where -+ uip_process() is called. It can be called either because we have -+ incoming data that should be processed, or because the periodic -+ timer has fired. */ -+ -+#define UIP_DATA 1 /* Tells uIP that there is incoming data in -+ the uip_buf buffer. The length of the -+ data is stored in the global variable -+ uip_len. */ -+#define UIP_TIMER 2 /* Tells uIP that the periodic timer has -+ fired. */ -+#if UIP_UDP -+#define UIP_UDP_TIMER 3 -+#endif /* UIP_UDP */ -+ -+/* The TCP states used in the uip_conn->tcpstateflags. */ -+#define CLOSED 0 -+#define SYN_RCVD 1 -+#define SYN_SENT 2 -+#define ESTABLISHED 3 -+#define FIN_WAIT_1 4 -+#define FIN_WAIT_2 5 -+#define CLOSING 6 -+#define TIME_WAIT 7 -+#define LAST_ACK 8 -+#define TS_MASK 15 -+ -+#define UIP_STOPPED 16 -+ -+#define UIP_TCPIP_HLEN 40 -+ -+/* The TCP and IP headers. */ -+typedef struct { -+ /* IP header. */ -+ u8_t vhl, -+ tos, -+ len[2], -+ ipid[2], -+ ipoffset[2], -+ ttl, -+ proto; -+ u16_t ipchksum; -+ u16_t srcipaddr[2], -+ destipaddr[2]; -+ -+ /* TCP header. */ -+ u16_t srcport, -+ destport; -+ u8_t seqno[4], -+ ackno[4], -+ tcpoffset, -+ flags, -+ wnd[2]; -+ u16_t tcpchksum; -+ u8_t urgp[2]; -+ u8_t optdata[4]; -+} uip_tcpip_hdr; -+ -+/* The ICMP and IP headers. */ -+typedef struct { -+ /* IP header. */ -+ u8_t vhl, -+ tos, -+ len[2], -+ ipid[2], -+ ipoffset[2], -+ ttl, -+ proto; -+ u16_t ipchksum; -+ u16_t srcipaddr[2], -+ destipaddr[2]; -+ /* ICMP (echo) header. */ -+ u8_t type, icode; -+ u16_t icmpchksum; -+ u16_t id, seqno; -+} uip_icmpip_hdr; -+ -+ -+/* The UDP and IP headers. */ -+typedef struct { -+ /* IP header. */ -+ u8_t vhl, -+ tos, -+ len[2], -+ ipid[2], -+ ipoffset[2], -+ ttl, -+ proto; -+ u16_t ipchksum; -+ u16_t srcipaddr[2], -+ destipaddr[2]; -+ -+ /* UDP header. */ -+ u16_t srcport, -+ destport; -+ u16_t udplen; -+ u16_t udpchksum; -+} uip_udpip_hdr; -+ -+#define UIP_PROTO_ICMP 1 -+#define UIP_PROTO_TCP 6 -+#define UIP_PROTO_UDP 17 -+ -+#if UIP_FIXEDADDR -+extern const u16_t uip_hostaddr[2]; -+#else /* UIP_FIXEDADDR */ -+extern u16_t uip_hostaddr[2]; -+#endif /* UIP_FIXEDADDR */ -+ -+#endif /* __UIP_H__ */ -+ -+ -+/** @} */ -+ ---- /dev/null -+++ b/net/uip-0.9/uip_arch.c -@@ -0,0 +1,145 @@ -+/* -+ * Copyright (c) 2001, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ -+ * -+ */ -+ -+ -+#include "uip.h" -+#include "uip_arch.h" -+ -+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -+#define IP_PROTO_TCP 6 -+ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_add32(u8_t *op32, u16_t op16) -+{ -+ -+ uip_acc32[3] = op32[3] + (op16 & 0xff); -+ uip_acc32[2] = op32[2] + (op16 >> 8); -+ uip_acc32[1] = op32[1]; -+ uip_acc32[0] = op32[0]; -+ -+ if(uip_acc32[2] < (op16 >> 8)) { -+ ++uip_acc32[1]; -+ if(uip_acc32[1] == 0) { -+ ++uip_acc32[0]; -+ } -+ } -+ -+ -+ if(uip_acc32[3] < (op16 & 0xff)) { -+ ++uip_acc32[2]; -+ if(uip_acc32[2] == 0) { -+ ++uip_acc32[1]; -+ if(uip_acc32[1] == 0) { -+ ++uip_acc32[0]; -+ } -+ } -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -+u16_t -+uip_chksum(u16_t *sdata, u16_t len) -+{ -+ u16_t acc; -+ -+ for(acc = 0; len > 1; len -= 2) { -+ acc += *sdata; -+ if(acc < *sdata) { -+ /* Overflow, so we add the carry to acc (i.e., increase by -+ one). */ -+ ++acc; -+ } -+ ++sdata; -+ } -+ -+ /* add up any odd byte */ -+ if(len == 1) { -+ acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); -+ if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { -+ ++acc; -+ } -+ } -+ -+ return acc; -+} -+/*-----------------------------------------------------------------------------------*/ -+u16_t -+uip_ipchksum(void) -+{ -+ return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); -+} -+/*-----------------------------------------------------------------------------------*/ -+u16_t -+uip_tcpchksum(void) -+{ -+ u16_t hsum, sum; -+ -+ -+ /* Compute the checksum of the TCP header. */ -+ hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); -+ -+ /* Compute the checksum of the data in the TCP packet and add it to -+ the TCP header checksum. */ -+ sum = uip_chksum((u16_t *)uip_appdata, -+ (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); -+ -+ if((sum += hsum) < hsum) { -+ ++sum; -+ } -+ -+ if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { -+ ++sum; -+ } -+ if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { -+ ++sum; -+ } -+ if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { -+ ++sum; -+ } -+ if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { -+ ++sum; -+ } -+ if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { -+ ++sum; -+ } -+ -+ hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); -+ -+ if((sum += hsum) < hsum) { -+ ++sum; -+ } -+ -+ return sum; -+} -+/*-----------------------------------------------------------------------------------*/ ---- /dev/null -+++ b/net/uip-0.9/uip_arch.h -@@ -0,0 +1,130 @@ -+/** -+ * \defgroup uiparch Architecture specific uIP functions -+ * @{ -+ * -+ * The functions in the architecture specific module implement the IP -+ * check sum and 32-bit additions. -+ * -+ * The IP checksum calculation is the most computationally expensive -+ * operation in the TCP/IP stack and it therefore pays off to -+ * implement this in efficient assembler. The purpose of the uip-arch -+ * module is to let the checksum functions to be implemented in -+ * architecture specific assembler. -+ * -+ */ -+ -+/** -+ * \file -+ * Declarations of architecture specific functions. -+ * \author Adam Dunkels <adam@dunkels.com> -+ */ -+ -+/* -+ * Copyright (c) 2001, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ -+ * -+ */ -+ -+#ifndef __UIP_ARCH_H__ -+#define __UIP_ARCH_H__ -+ -+#include "uip.h" -+ -+/** -+ * Carry out a 32-bit addition. -+ * -+ * Because not all architectures for which uIP is intended has native -+ * 32-bit arithmetic, uIP uses an external C function for doing the -+ * required 32-bit additions in the TCP protocol processing. This -+ * function should add the two arguments and place the result in the -+ * global variable uip_acc32. -+ * -+ * \note The 32-bit integer pointed to by the op32 parameter and the -+ * result in the uip_acc32 variable are in network byte order (big -+ * endian). -+ * -+ * \param op32 A pointer to a 4-byte array representing a 32-bit -+ * integer in network byte order (big endian). -+ * -+ * \param op16 A 16-bit integer in host byte order. -+ */ -+void uip_add32(u8_t *op32, u16_t op16); -+ -+/** -+ * Calculate the Internet checksum over a buffer. -+ * -+ * The Internet checksum is the one's complement of the one's -+ * complement sum of all 16-bit words in the buffer. -+ * -+ * See RFC1071. -+ * -+ * \note This function is not called in the current version of uIP, -+ * but future versions might make use of it. -+ * -+ * \param buf A pointer to the buffer over which the checksum is to be -+ * computed. -+ * -+ * \param len The length of the buffer over which the checksum is to -+ * be computed. -+ * -+ * \return The Internet checksum of the buffer. -+ */ -+u16_t uip_chksum(u16_t *buf, u16_t len); -+ -+/** -+ * Calculate the IP header checksum of the packet header in uip_buf. -+ * -+ * The IP header checksum is the Internet checksum of the 20 bytes of -+ * the IP header. -+ * -+ * \return The IP header checksum of the IP header in the uip_buf -+ * buffer. -+ */ -+u16_t uip_ipchksum(void); -+ -+/** -+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. -+ * -+ * The TCP checksum is the Internet checksum of data contents of the -+ * TCP segment, and a pseudo-header as defined in RFC793. -+ * -+ * \note The uip_appdata pointer that points to the packet data may -+ * point anywhere in memory, so it is not possible to simply calculate -+ * the Internet checksum of the contents of the uip_buf buffer. -+ * -+ * \return The TCP checksum of the TCP segment in uip_buf and pointed -+ * to by uip_appdata. -+ */ -+u16_t uip_tcpchksum(void); -+ -+/** @} */ -+ -+#endif /* __UIP_ARCH_H__ */ ---- /dev/null -+++ b/net/uip-0.9/uip_arp.c -@@ -0,0 +1,421 @@ -+/** -+ * \addtogroup uip -+ * @{ -+ */ -+ -+/** -+ * \defgroup uiparp uIP Address Resolution Protocol -+ * @{ -+ * -+ * The Address Resolution Protocol ARP is used for mapping between IP -+ * addresses and link level addresses such as the Ethernet MAC -+ * addresses. ARP uses broadcast queries to ask for the link level -+ * address of a known IP address and the host which is configured with -+ * the IP address for which the query was meant, will respond with its -+ * link level address. -+ * -+ * \note This ARP implementation only supports Ethernet. -+ */ -+ -+/** -+ * \file -+ * Implementation of the ARP Address Resolution Protocol. -+ * \author Adam Dunkels <adam@dunkels.com> -+ * -+ */ -+ -+/* -+ * Copyright (c) 2001-2003, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ -+ * -+ */ -+ -+ -+#include "uip_arp.h" -+ -+struct arp_hdr { -+ struct uip_eth_hdr ethhdr; -+ u16_t hwtype; -+ u16_t protocol; -+ u8_t hwlen; -+ u8_t protolen; -+ u16_t opcode; -+ struct uip_eth_addr shwaddr; -+ u16_t sipaddr[2]; -+ struct uip_eth_addr dhwaddr; -+ u16_t dipaddr[2]; -+}; -+ -+struct ethip_hdr { -+ struct uip_eth_hdr ethhdr; -+ /* IP header. */ -+ u8_t vhl, -+ tos, -+ len[2], -+ ipid[2], -+ ipoffset[2], -+ ttl, -+ proto; -+ u16_t ipchksum; -+ u16_t srcipaddr[2], -+ destipaddr[2]; -+}; -+ -+#define ARP_REQUEST 1 -+#define ARP_REPLY 2 -+ -+#define ARP_HWTYPE_ETH 1 -+ -+struct arp_entry { -+ u16_t ipaddr[2]; -+ struct uip_eth_addr ethaddr; -+ u8_t time; -+}; -+ -+struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, -+ UIP_ETHADDR1, -+ UIP_ETHADDR2, -+ UIP_ETHADDR3, -+ UIP_ETHADDR4, -+ UIP_ETHADDR5}}; -+ -+static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; -+static u16_t ipaddr[2]; -+static u8_t i, c; -+ -+static u8_t arptime; -+static u8_t tmpage; -+ -+#define BUF ((struct arp_hdr *)&uip_buf[0]) -+#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) -+/*-----------------------------------------------------------------------------------*/ -+/** -+ * Initialize the ARP module. -+ * -+ */ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_arp_init(void) -+{ -+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { -+ memset(arp_table[i].ipaddr, 0, 4); -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -+/** -+ * Periodic ARP processing function. -+ * -+ * This function performs periodic timer processing in the ARP module -+ * and should be called at regular intervals. The recommended interval -+ * is 10 seconds between the calls. -+ * -+ */ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_arp_timer(void) -+{ -+ struct arp_entry *tabptr; -+ -+ ++arptime; -+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { -+ tabptr = &arp_table[i]; -+ if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && -+ arptime - tabptr->time >= UIP_ARP_MAXAGE) { -+ memset(tabptr->ipaddr, 0, 4); -+ } -+ } -+ -+} -+/*-----------------------------------------------------------------------------------*/ -+static void -+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) -+{ -+ register struct arp_entry *tabptr = 0; -+ /* Walk through the ARP mapping table and try to find an entry to -+ update. If none is found, the IP -> MAC address mapping is -+ inserted in the ARP table. */ -+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { -+ -+ tabptr = &arp_table[i]; -+ /* Only check those entries that are actually in use. */ -+ if(tabptr->ipaddr[0] != 0 && -+ tabptr->ipaddr[1] != 0) { -+ -+ /* Check if the source IP address of the incoming packet matches -+ the IP address in this ARP table entry. */ -+ if(ipaddr[0] == tabptr->ipaddr[0] && -+ ipaddr[1] == tabptr->ipaddr[1]) { -+ -+ /* An old entry found, update this and return. */ -+ memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); -+ tabptr->time = arptime; -+ -+ return; -+ } -+ } -+ } -+ -+ /* If we get here, no existing ARP table entry was found, so we -+ create one. */ -+ -+ /* First, we try to find an unused entry in the ARP table. */ -+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { -+ tabptr = &arp_table[i]; -+ if(tabptr->ipaddr[0] == 0 && -+ tabptr->ipaddr[1] == 0) { -+ break; -+ } -+ } -+ -+ /* If no unused entry is found, we try to find the oldest entry and -+ throw it away. */ -+ if(i == UIP_ARPTAB_SIZE) { -+ tmpage = 0; -+ c = 0; -+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { -+ tabptr = &arp_table[i]; -+ if(arptime - tabptr->time > tmpage) { -+ tmpage = arptime - tabptr->time; -+ c = i; -+ } -+ } -+ i = c; -+ } -+ -+ /* Now, i is the ARP table entry which we will fill with the new -+ information. */ -+ memcpy(tabptr->ipaddr, ipaddr, 4); -+ memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); -+ tabptr->time = arptime; -+} -+/*-----------------------------------------------------------------------------------*/ -+/** -+ * ARP processing for incoming IP packets -+ * -+ * This function should be called by the device driver when an IP -+ * packet has been received. The function will check if the address is -+ * in the ARP cache, and if so the ARP cache entry will be -+ * refreshed. If no ARP cache entry was found, a new one is created. -+ * -+ * This function expects an IP packet with a prepended Ethernet header -+ * in the uip_buf[] buffer, and the length of the packet in the global -+ * variable uip_len. -+ */ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_arp_ipin(void) -+{ -+ uip_len -= sizeof(struct uip_eth_hdr); -+ -+ /* Only insert/update an entry if the source IP address of the -+ incoming IP packet comes from a host on the local network. */ -+ if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != -+ (uip_hostaddr[0] & uip_arp_netmask[0])) { -+ return; -+ } -+ if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != -+ (uip_hostaddr[1] & uip_arp_netmask[1])) { -+ return; -+ } -+ uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); -+ -+ return; -+} -+/*-----------------------------------------------------------------------------------*/ -+/** -+ * ARP processing for incoming ARP packets. -+ * -+ * This function should be called by the device driver when an ARP -+ * packet has been received. The function will act differently -+ * depending on the ARP packet type: if it is a reply for a request -+ * that we previously sent out, the ARP cache will be filled in with -+ * the values from the ARP reply. If the incoming ARP packet is an ARP -+ * request for our IP address, an ARP reply packet is created and put -+ * into the uip_buf[] buffer. -+ * -+ * When the function returns, the value of the global variable uip_len -+ * indicates whether the device driver should send out a packet or -+ * not. If uip_len is zero, no packet should be sent. If uip_len is -+ * non-zero, it contains the length of the outbound packet that is -+ * present in the uip_buf[] buffer. -+ * -+ * This function expects an ARP packet with a prepended Ethernet -+ * header in the uip_buf[] buffer, and the length of the packet in the -+ * global variable uip_len. -+ */ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_arp_arpin(void) -+{ -+ -+ if(uip_len < sizeof(struct arp_hdr)) { -+ uip_len = 0; -+ return; -+ } -+ -+ uip_len = 0; -+ -+ switch(BUF->opcode) { -+ case HTONS(ARP_REQUEST): -+ /* ARP request. If it asked for our address, we send out a -+ reply. */ -+ if(BUF->dipaddr[0] == uip_hostaddr[0] && -+ BUF->dipaddr[1] == uip_hostaddr[1]) { -+ /* The reply opcode is 2. */ -+ BUF->opcode = HTONS(2); -+ -+ memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); -+ memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); -+ memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); -+ memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); -+ -+ BUF->dipaddr[0] = BUF->sipaddr[0]; -+ BUF->dipaddr[1] = BUF->sipaddr[1]; -+ BUF->sipaddr[0] = uip_hostaddr[0]; -+ BUF->sipaddr[1] = uip_hostaddr[1]; -+ -+ BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); -+ uip_len = sizeof(struct arp_hdr); -+ } -+ break; -+ case HTONS(ARP_REPLY): -+ /* ARP reply. We insert or update the ARP table if it was meant -+ for us. */ -+ if(BUF->dipaddr[0] == uip_hostaddr[0] && -+ BUF->dipaddr[1] == uip_hostaddr[1]) { -+ -+ uip_arp_update(BUF->sipaddr, &BUF->shwaddr); -+ } -+ break; -+ } -+ -+ return; -+} -+/*-----------------------------------------------------------------------------------*/ -+/** -+ * Prepend Ethernet header to an outbound IP packet and see if we need -+ * to send out an ARP request. -+ * -+ * This function should be called before sending out an IP packet. The -+ * function checks the destination IP address of the IP packet to see -+ * what Ethernet MAC address that should be used as a destination MAC -+ * address on the Ethernet. -+ * -+ * If the destination IP address is in the local network (determined -+ * by logical ANDing of netmask and our IP address), the function -+ * checks the ARP cache to see if an entry for the destination IP -+ * address is found. If so, an Ethernet header is prepended and the -+ * function returns. If no ARP cache entry is found for the -+ * destination IP address, the packet in the uip_buf[] is replaced by -+ * an ARP request packet for the IP address. The IP packet is dropped -+ * and it is assumed that they higher level protocols (e.g., TCP) -+ * eventually will retransmit the dropped packet. -+ * -+ * If the destination IP address is not on the local network, the IP -+ * address of the default router is used instead. -+ * -+ * When the function returns, a packet is present in the uip_buf[] -+ * buffer, and the length of the packet is in the global variable -+ * uip_len. -+ */ -+/*-----------------------------------------------------------------------------------*/ -+void -+uip_arp_out(void) -+{ -+ struct arp_entry *tabptr = 0; -+ /* Find the destination IP address in the ARP table and construct -+ the Ethernet header. If the destination IP addres isn't on the -+ local network, we use the default router's IP address instead. -+ -+ If not ARP table entry is found, we overwrite the original IP -+ packet with an ARP request for the IP address. */ -+ -+ /* Check if the destination address is on the local network. */ -+ if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != -+ (uip_hostaddr[0] & uip_arp_netmask[0]) || -+ (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != -+ (uip_hostaddr[1] & uip_arp_netmask[1])) { -+ /* Destination address was not on the local network, so we need to -+ use the default router's IP address instead of the destination -+ address when determining the MAC address. */ -+ ipaddr[0] = uip_arp_draddr[0]; -+ ipaddr[1] = uip_arp_draddr[1]; -+ } else { -+ /* Else, we use the destination IP address. */ -+ ipaddr[0] = IPBUF->destipaddr[0]; -+ ipaddr[1] = IPBUF->destipaddr[1]; -+ } -+ -+ for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { -+ tabptr = &arp_table[i]; -+ if(ipaddr[0] == tabptr->ipaddr[0] && -+ ipaddr[1] == tabptr->ipaddr[1]) -+ break; -+ } -+ -+ if(i == UIP_ARPTAB_SIZE) { -+ /* The destination address was not in our ARP table, so we -+ overwrite the IP packet with an ARP request. */ -+ -+ memset(BUF->ethhdr.dest.addr, 0xff, 6); -+ memset(BUF->dhwaddr.addr, 0x00, 6); -+ memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); -+ memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); -+ -+ BUF->dipaddr[0] = ipaddr[0]; -+ BUF->dipaddr[1] = ipaddr[1]; -+ BUF->sipaddr[0] = uip_hostaddr[0]; -+ BUF->sipaddr[1] = uip_hostaddr[1]; -+ BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ -+ BUF->hwtype = HTONS(ARP_HWTYPE_ETH); -+ BUF->protocol = HTONS(UIP_ETHTYPE_IP); -+ BUF->hwlen = 6; -+ BUF->protolen = 4; -+ BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); -+ -+ uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; -+ -+ uip_len = sizeof(struct arp_hdr); -+ return; -+ } -+ -+ /* Build an ethernet header. */ -+ memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); -+ memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); -+ -+ IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); -+ -+ uip_len += sizeof(struct uip_eth_hdr); -+} -+/*-----------------------------------------------------------------------------------*/ -+ -+/** @} */ -+/** @} */ ---- /dev/null -+++ b/net/uip-0.9/uip_arp.h -@@ -0,0 +1,201 @@ -+/** -+ * \addtogroup uip -+ * @{ -+ */ -+ -+/** -+ * \addtogroup uiparp -+ * @{ -+ */ -+ -+/** -+ * \file -+ * Macros and definitions for the ARP module. -+ * \author Adam Dunkels <adam@dunkels.com> -+ */ -+ -+ -+/* -+ * Copyright (c) 2001-2003, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ -+ * -+ */ -+ -+#ifndef __UIP_ARP_H__ -+#define __UIP_ARP_H__ -+ -+#include "uip.h" -+ -+ -+/** -+ * Representation of a 48-bit Ethernet address. -+ */ -+struct uip_eth_addr { -+ u8_t addr[6]; -+}; -+ -+extern struct uip_eth_addr uip_ethaddr; -+ -+/** -+ * The Ethernet header. -+ */ -+struct uip_eth_hdr { -+ struct uip_eth_addr dest; -+ struct uip_eth_addr src; -+ u16_t type; -+}; -+ -+#define UIP_ETHTYPE_ARP 0x0806 -+#define UIP_ETHTYPE_IP 0x0800 -+#define UIP_ETHTYPE_IP6 0x86dd -+ -+ -+/* The uip_arp_init() function must be called before any of the other -+ ARP functions. */ -+void uip_arp_init(void); -+ -+/* The uip_arp_ipin() function should be called whenever an IP packet -+ arrives from the Ethernet. This function refreshes the ARP table or -+ inserts a new mapping if none exists. The function assumes that an -+ IP packet with an Ethernet header is present in the uip_buf buffer -+ and that the length of the packet is in the uip_len variable. */ -+void uip_arp_ipin(void); -+ -+/* The uip_arp_arpin() should be called when an ARP packet is received -+ by the Ethernet driver. This function also assumes that the -+ Ethernet frame is present in the uip_buf buffer. When the -+ uip_arp_arpin() function returns, the contents of the uip_buf -+ buffer should be sent out on the Ethernet if the uip_len variable -+ is > 0. */ -+void uip_arp_arpin(void); -+ -+/* The uip_arp_out() function should be called when an IP packet -+ should be sent out on the Ethernet. This function creates an -+ Ethernet header before the IP header in the uip_buf buffer. The -+ Ethernet header will have the correct Ethernet MAC destination -+ address filled in if an ARP table entry for the destination IP -+ address (or the IP address of the default router) is present. If no -+ such table entry is found, the IP packet is overwritten with an ARP -+ request and we rely on TCP to retransmit the packet that was -+ overwritten. In any case, the uip_len variable holds the length of -+ the Ethernet frame that should be transmitted. */ -+void uip_arp_out(void); -+ -+/* The uip_arp_timer() function should be called every ten seconds. It -+ is responsible for flushing old entries in the ARP table. */ -+void uip_arp_timer(void); -+ -+/** @} */ -+ -+/** -+ * \addtogroup uipconffunc -+ * @{ -+ */ -+ -+/** -+ * Set the default router's IP address. -+ * -+ * \param addr A pointer to a 4-byte array containing the IP address -+ * of the default router. -+ * -+ * \hideinitializer -+ */ -+#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ -+ uip_arp_draddr[1] = addr[1]; } while(0) -+ -+/** -+ * Set the netmask. -+ * -+ * \param addr A pointer to a 4-byte array containing the IP address -+ * of the netmask. -+ * -+ * \hideinitializer -+ */ -+#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ -+ uip_arp_netmask[1] = addr[1]; } while(0) -+ -+ -+/** -+ * Get the default router's IP address. -+ * -+ * \param addr A pointer to a 4-byte array that will be filled in with -+ * the IP address of the default router. -+ * -+ * \hideinitializer -+ */ -+#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ -+ addr[1] = uip_arp_draddr[1]; } while(0) -+ -+/** -+ * Get the netmask. -+ * -+ * \param addr A pointer to a 4-byte array that will be filled in with -+ * the value of the netmask. -+ * -+ * \hideinitializer -+ */ -+#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ -+ addr[1] = uip_arp_netmask[1]; } while(0) -+ -+ -+/** -+ * Specifiy the Ethernet MAC address. -+ * -+ * The ARP code needs to know the MAC address of the Ethernet card in -+ * order to be able to respond to ARP queries and to generate working -+ * Ethernet headers. -+ * -+ * \note This macro only specifies the Ethernet MAC address to the ARP -+ * code. It cannot be used to change the MAC address of the Ethernet -+ * card. -+ * -+ * \param eaddr A pointer to a struct uip_eth_addr containing the -+ * Ethernet MAC address of the Ethernet card. -+ * -+ * \hideinitializer -+ */ -+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ -+ uip_ethaddr.addr[1] = eaddr.addr[1];\ -+ uip_ethaddr.addr[2] = eaddr.addr[2];\ -+ uip_ethaddr.addr[3] = eaddr.addr[3];\ -+ uip_ethaddr.addr[4] = eaddr.addr[4];\ -+ uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) -+ -+/** @} */ -+ -+/** -+ * \internal Internal variables that are set using the macros -+ * uip_setdraddr and uip_setnetmask. -+ */ -+extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -+#endif /* __UIP_ARP_H__ */ -+ -+ ---- /dev/null -+++ b/net/uip-0.9/uipopt.h -@@ -0,0 +1,557 @@ -+/** -+ * \defgroup uipopt Configuration options for uIP -+ * @{ -+ * -+ * uIP is configured using the per-project configuration file -+ * "uipopt.h". This file contains all compile-time options for uIP and -+ * should be tweaked to match each specific project. The uIP -+ * distribution contains a documented example "uipopt.h" that can be -+ * copied and modified for each project. -+ */ -+ -+/** -+ * \file -+ * Configuration options for uIP. -+ * \author Adam Dunkels <adam@dunkels.com> -+ * -+ * This file is used for tweaking various configuration options for -+ * uIP. You should make a copy of this file into one of your project's -+ * directories instead of editing this example "uipopt.h" file that -+ * comes with the uIP distribution. -+ */ -+ -+/* -+ * Copyright (c) 2001-2003, Adam Dunkels. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This file is part of the uIP TCP/IP stack. -+ * -+ * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ -+ * -+ */ -+ -+#ifndef __UIPOPT_H__ -+#define __UIPOPT_H__ -+ -+/*------------------------------------------------------------------------------*/ -+/** -+ * \defgroup uipopttypedef uIP type definitions -+ * @{ -+ */ -+ -+/** -+ * The 8-bit unsigned data type. -+ * -+ * This may have to be tweaked for your particular compiler. "unsigned -+ * char" works for most compilers. -+ */ -+typedef unsigned char u8_t; -+ -+/** -+ * The 16-bit unsigned data type. -+ * -+ * This may have to be tweaked for your particular compiler. "unsigned -+ * short" works for most compilers. -+ */ -+typedef unsigned short u16_t; -+ -+/** -+ * The statistics data type. -+ * -+ * This datatype determines how high the statistics counters are able -+ * to count. -+ */ -+typedef unsigned short uip_stats_t; -+ -+/** @} */ -+ -+/*------------------------------------------------------------------------------*/ -+ -+/** -+ * \defgroup uipoptstaticconf Static configuration options -+ * @{ -+ * -+ * These configuration options can be used for setting the IP address -+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The -+ * configuration options for a specific node includes IP address, -+ * netmask and default router as well as the Ethernet address. The -+ * netmask, default router and Ethernet address are appliciable only -+ * if uIP should be run over Ethernet. -+ * -+ * All of these should be changed to suit your project. -+*/ -+ -+/** -+ * Determines if uIP should use a fixed IP address or not. -+ * -+ * If uIP should use a fixed IP address, the settings are set in the -+ * uipopt.h file. If not, the macros uip_sethostaddr(), -+ * uip_setdraddr() and uip_setnetmask() should be used instead. -+ * -+ * \hideinitializer -+ */ -+#define UIP_FIXEDADDR 0 -+ -+/** -+ * Ping IP address asignment. -+ * -+ * uIP uses a "ping" packets for setting its own IP address if this -+ * option is set. If so, uIP will start with an empty IP address and -+ * the destination IP address of the first incoming "ping" (ICMP echo) -+ * packet will be used for setting the hosts IP address. -+ * -+ * \note This works only if UIP_FIXEDADDR is 0. -+ * -+ * \hideinitializer -+ */ -+#define UIP_PINGADDRCONF 0 -+ -+#define UIP_IPADDR0 192 /**< The first octet of the IP address of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_IPADDR1 168 /**< The second octet of the IP address of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_IPADDR2 0 /**< The third octet of the IP address of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_IPADDR3 250 /**< The fourth octet of the IP address of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+ -+#define UIP_NETMASK0 255 /**< The first octet of the netmask of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_NETMASK1 255 /**< The second octet of the netmask of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_NETMASK2 255 /**< The third octet of the netmask of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of -+ this uIP node, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+ -+#define UIP_DRIPADDR0 192 /**< The first octet of the IP address of -+ the default router, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_DRIPADDR1 168 /**< The second octet of the IP address of -+ the default router, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_DRIPADDR2 0 /**< The third octet of the IP address of -+ the default router, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+#define UIP_DRIPADDR3 1 /**< The fourth octet of the IP address of -+ the default router, if UIP_FIXEDADDR is -+ 1. \hideinitializer */ -+ -+/** -+ * Specifies if the uIP ARP module should be compiled with a fixed -+ * Ethernet MAC address or not. -+ * -+ * If this configuration option is 0, the macro uip_setethaddr() can -+ * be used to specify the Ethernet address at run-time. -+ * -+ * \hideinitializer -+ */ -+#define UIP_FIXEDETHADDR 0 -+ -+#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet -+ address if UIP_FIXEDETHADDR is -+ 1. \hideinitializer */ -+#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet -+ address if UIP_FIXEDETHADDR is -+ 1. \hideinitializer */ -+#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet -+ address if UIP_FIXEDETHADDR is -+ 1. \hideinitializer */ -+#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet -+ address if UIP_FIXEDETHADDR is -+ 1. \hideinitializer */ -+#define UIP_ETHADDR4 0x05 /**< The fifth octet of the Ethernet -+ address if UIP_FIXEDETHADDR is -+ 1. \hideinitializer */ -+#define UIP_ETHADDR5 0x71 /**< The sixth octet of the Ethernet -+ address if UIP_FIXEDETHADDR is -+ 1. \hideinitializer */ -+ -+/** @} */ -+/*------------------------------------------------------------------------------*/ -+/** -+ * \defgroup uipoptip IP configuration options -+ * @{ -+ * -+ */ -+/** -+ * The IP TTL (time to live) of IP packets sent by uIP. -+ * -+ * This should normally not be changed. -+ */ -+#define UIP_TTL 255 -+ -+/** -+ * Turn on support for IP packet reassembly. -+ * -+ * uIP supports reassembly of fragmented IP packets. This features -+ * requires an additonal amount of RAM to hold the reassembly buffer -+ * and the reassembly code size is approximately 700 bytes. The -+ * reassembly buffer is of the same size as the uip_buf buffer -+ * (configured by UIP_BUFSIZE). -+ * -+ * \note IP packet reassembly is not heavily tested. -+ * -+ * \hideinitializer -+ */ -+#define UIP_REASSEMBLY 0 -+ -+/** -+ * The maximum time an IP fragment should wait in the reassembly -+ * buffer before it is dropped. -+ * -+ */ -+#define UIP_REASS_MAXAGE 40 -+ -+/** @} */ -+ -+/*------------------------------------------------------------------------------*/ -+/** -+ * \defgroup uipoptudp UDP configuration options -+ * @{ -+ * -+ * \note The UDP support in uIP is still not entirely complete; there -+ * is no support for sending or receiving broadcast or multicast -+ * packets, but it works well enough to support a number of vital -+ * applications such as DNS queries, though -+ */ -+ -+/** -+ * Toggles wether UDP support should be compiled in or not. -+ * -+ * \hideinitializer -+ */ -+#define UIP_UDP 0 -+ -+/** -+ * Toggles if UDP checksums should be used or not. -+ * -+ * \note Support for UDP checksums is currently not included in uIP, -+ * so this option has no function. -+ * -+ * \hideinitializer -+ */ -+#define UIP_UDP_CHECKSUMS 0 -+ -+/** -+ * The maximum amount of concurrent UDP connections. -+ * -+ * \hideinitializer -+ */ -+#define UIP_UDP_CONNS 10 -+ -+/** -+ * The name of the function that should be called when UDP datagrams arrive. -+ * -+ * \hideinitializer -+ */ -+#define UIP_UDP_APPCALL udp_appcall -+ -+/** @} */ -+/*------------------------------------------------------------------------------*/ -+/** -+ * \defgroup uipopttcp TCP configuration options -+ * @{ -+ */ -+ -+/** -+ * Determines if support for opening connections from uIP should be -+ * compiled in. -+ * -+ * If the applications that are running on top of uIP for this project -+ * do not need to open outgoing TCP connections, this configration -+ * option can be turned off to reduce the code size of uIP. -+ * -+ * \hideinitializer -+ */ -+#define UIP_ACTIVE_OPEN 1 -+ -+/** -+ * The maximum number of simultaneously open TCP connections. -+ * -+ * Since the TCP connections are statically allocated, turning this -+ * configuration knob down results in less RAM used. Each TCP -+ * connection requires approximatly 30 bytes of memory. -+ * -+ * \hideinitializer -+ */ -+#define UIP_CONNS 10 -+ -+/** -+ * The maximum number of simultaneously listening TCP ports. -+ * -+ * Each listening TCP port requires 2 bytes of memory. -+ * -+ * \hideinitializer -+ */ -+#define UIP_LISTENPORTS 10 -+ -+/** -+ * The size of the advertised receiver's window. -+ * -+ * Should be set low (i.e., to the size of the uip_buf buffer) is the -+ * application is slow to process incoming data, or high (32768 bytes) -+ * if the application processes data quickly. -+ * -+ * \hideinitializer -+ */ -+#define UIP_RECEIVE_WINDOW 32768 -+ -+/** -+ * Determines if support for TCP urgent data notification should be -+ * compiled in. -+ * -+ * Urgent data (out-of-band data) is a rarely used TCP feature that -+ * very seldom would be required. -+ * -+ * \hideinitializer -+ */ -+#define UIP_URGDATA 1 -+ -+/** -+ * The initial retransmission timeout counted in timer pulses. -+ * -+ * This should not be changed. -+ */ -+#define UIP_RTO 3 -+ -+/** -+ * The maximum number of times a segment should be retransmitted -+ * before the connection should be aborted. -+ * -+ * This should not be changed. -+ */ -+#define UIP_MAXRTX 8 -+ -+/** -+ * The maximum number of times a SYN segment should be retransmitted -+ * before a connection request should be deemed to have been -+ * unsuccessful. -+ * -+ * This should not need to be changed. -+ */ -+#define UIP_MAXSYNRTX 3 -+ -+/** -+ * The TCP maximum segment size. -+ * -+ * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. -+ */ -+#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) -+ -+/** -+ * How long a connection should stay in the TIME_WAIT state. -+ * -+ * This configiration option has no real implication, and it should be -+ * left untouched. -+ */ -+#define UIP_TIME_WAIT_TIMEOUT 120 -+ -+ -+/** @} */ -+/*------------------------------------------------------------------------------*/ -+/** -+ * \defgroup uipoptarp ARP configuration options -+ * @{ -+ */ -+ -+/** -+ * The size of the ARP table. -+ * -+ * This option should be set to a larger value if this uIP node will -+ * have many connections from the local network. -+ * -+ * \hideinitializer -+ */ -+#define UIP_ARPTAB_SIZE 8 -+ -+/** -+ * The maxium age of ARP table entries measured in 10ths of seconds. -+ * -+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD -+ * default). -+ */ -+#define UIP_ARP_MAXAGE 120 -+ -+/** @} */ -+ -+/*------------------------------------------------------------------------------*/ -+ -+/** -+ * \defgroup uipoptgeneral General configuration options -+ * @{ -+ */ -+ -+/** -+ * The size of the uIP packet buffer. -+ * -+ * The uIP packet buffer should not be smaller than 60 bytes, and does -+ * not need to be larger than 1500 bytes. Lower size results in lower -+ * TCP throughput, larger size results in higher TCP throughput. -+ * -+ * \hideinitializer -+ */ -+#define UIP_BUFSIZE 1500 -+ -+ -+/** -+ * Determines if statistics support should be compiled in. -+ * -+ * The statistics is useful for debugging and to show the user. -+ * -+ * \hideinitializer -+ */ -+#define UIP_STATISTICS 1 -+ -+/** -+ * Determines if logging of certain events should be compiled in. -+ * -+ * This is useful mostly for debugging. The function uip_log() -+ * must be implemented to suit the architecture of the project, if -+ * logging is turned on. -+ * -+ * \hideinitializer -+ */ -+#define UIP_LOGGING 0 -+ -+/** -+ * Print out a uIP log message. -+ * -+ * This function must be implemented by the module that uses uIP, and -+ * is called by uIP whenever a log message is generated. -+ */ -+void uip_log(char *msg); -+ -+/** -+ * The link level header length. -+ * -+ * This is the offset into the uip_buf where the IP header can be -+ * found. For Ethernet, this should be set to 14. For SLIP, this -+ * should be set to 0. -+ * -+ * \hideinitializer -+ */ -+#define UIP_LLH_LEN 14 -+ -+ -+/** @} */ -+/*------------------------------------------------------------------------------*/ -+/** -+ * \defgroup uipoptcpu CPU architecture configuration -+ * @{ -+ * -+ * The CPU architecture configuration is where the endianess of the -+ * CPU on which uIP is to be run is specified. Most CPUs today are -+ * little endian, and the most notable exception are the Motorolas -+ * which are big endian. The BYTE_ORDER macro should be changed to -+ * reflect the CPU architecture on which uIP is to be run. -+ */ -+#ifndef LITTLE_ENDIAN -+#define LITTLE_ENDIAN 3412 -+#endif /* LITTLE_ENDIAN */ -+#ifndef BIG_ENDIAN -+#define BIG_ENDIAN 1234 -+#endif /* BIGE_ENDIAN */ -+ -+/** -+ * The byte order of the CPU architecture on which uIP is to be run. -+ * -+ * This option can be either BIG_ENDIAN (Motorola byte order) or -+ * LITTLE_ENDIAN (Intel byte order). -+ * -+ * \hideinitializer -+ */ -+/*#ifndef BYTE_ORDER*/ -+#define BYTE_ORDER BIG_ENDIAN -+/*#endif*/ /* BYTE_ORDER */ -+ -+/** @} */ -+/*------------------------------------------------------------------------------*/ -+ -+/** -+ * \defgroup uipoptapp Appication specific configurations -+ * @{ -+ * -+ * An uIP application is implemented using a single application -+ * function that is called by uIP whenever a TCP/IP event occurs. The -+ * name of this function must be registered with uIP at compile time -+ * using the UIP_APPCALL definition. -+ * -+ * uIP applications can store the application state within the -+ * uip_conn structure by specifying the size of the application -+ * structure with the UIP_APPSTATE_SIZE macro. -+ * -+ * The file containing the definitions must be included in the -+ * uipopt.h file. -+ * -+ * The following example illustrates how this can look. -+ \code -+ -+void httpd_appcall(void); -+#define UIP_APPCALL httpd_appcall -+ -+struct httpd_state { -+ u8_t state; -+ u16_t count; -+ char *dataptr; -+ char *script; -+}; -+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) -+ \endcode -+ */ -+ -+/** -+ * \var #define UIP_APPCALL -+ * -+ * The name of the application function that uIP should call in -+ * response to TCP/IP events. -+ * -+ */ -+ -+/** -+ * \var #define UIP_APPSTATE_SIZE -+ * -+ * The size of the application state that is to be stored in the -+ * uip_conn structure. -+ */ -+/** @} */ -+ -+/* Include the header file for the application program that should be -+ used. If you don't use the example web server, you should change -+ this. */ -+#include "httpd.h" -+ -+ -+#endif /* __UIPOPT_H__ */ ---- a/board/infineon/easy50712/danube.c -+++ b/board/infineon/easy50712/danube.c -@@ -354,7 +354,7 @@ int do_http_upgrade(const unsigned char - } - /* write the image to the flash */ - puts("http ugrade ...\n"); -- sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size); -+ sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size); - return run_command(buf, 0); - } - ---- a/common/main.c -+++ b/common/main.c -@@ -273,6 +273,8 @@ static __inline__ int abortboot(int boot - - void main_loop (void) - { -+ int ret; -+ - #ifndef CONFIG_SYS_HUSH_PARSER - static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, }; - int len; -@@ -403,12 +407,22 @@ void main_loop (void) - # endif - - # ifndef CONFIG_SYS_HUSH_PARSER -- run_command (s, 0); -+ ret = run_command (s, 0); - # else -- parse_string_outer(s, FLAG_PARSE_SEMICOLON | -+ ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON | - FLAG_EXIT_FROM_LOOP); - # endif - -+# ifdef CONFIG_CMD_HTTPD -+ if (ret != 0) { -+ printf("Failed to execute bootcmd " -+ "(maybe invalid u-boot environment?), " -+ "starting httpd to update firmware...\n"); -+ NetLoopHttpd(); -+ } -+# endif -+ -+ - # ifdef CONFIG_AUTOBOOT_KEYED - disable_ctrlc(prev); /* restore Control C checking */ - # endif ---- a/include/configs/easy50712.h -+++ b/include/configs/easy50712.h -@@ -114,4 +114,7 @@ - - #define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */ - -+#define CONFIG_IPADDR 192.168.0.119 -+#define CONFIG_ETHADDR 00:01:02:03:04:05 -+ - #endif /* __CONFIG_H */ ---- a/lib_mips/time.c -+++ b/lib_mips/time.c -@@ -29,6 +29,8 @@ static unsigned long timestamp; - /* how many counter cycles in a jiffy */ - #define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ - -+unsigned long ifx_get_cpuclk(void); -+ - /* - * timer without interrupts - */ ---- a/net/httpd.c -+++ b/net/httpd.c -@@ -35,12 +35,14 @@ HttpdHandler (void) - } - } - -+#if 0 - static void - HttpdTimeout (void) - { - puts ("T "); - NetSetTimeout (TIMEOUT * 1000, HttpdTimeout); - } -+#endif - - void - HttpdStart (void) ---- a/net/net.c -+++ b/net/net.c -@@ -1966,7 +1966,7 @@ NetSendHttpd(void) - void - NetReceiveHttpd(volatile uchar * inpkt, int len) - { -- memcpy(uip_buf, inpkt, len); -+ memcpy(uip_buf, (const void *)inpkt, len); - uip_len = len; - if(BUF->type == htons(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); -@@ -1989,6 +1989,7 @@ NetLoopHttpd(void) - unsigned long long tout = 0; - bd_t *bd = gd->bd; - unsigned short int ip[2]; -+ struct uip_eth_addr eaddr; - - #ifdef CONFIG_NET_MULTI - NetRestarted = 0; -@@ -2039,6 +2040,15 @@ restart: - eth_getenv_enetaddr("ethaddr", NetOurEther); - #endif - -+ eaddr.addr[0] = NetOurEther[0]; -+ eaddr.addr[1] = NetOurEther[1]; -+ eaddr.addr[2] = NetOurEther[2]; -+ eaddr.addr[3] = NetOurEther[3]; -+ eaddr.addr[4] = NetOurEther[4]; -+ eaddr.addr[5] = NetOurEther[5]; -+ -+ uip_setethaddr(eaddr); -+ - NetCopyIP(&NetOurIP, &bd->bi_ip_addr); - NetOurGatewayIP = getenv_IPaddr ("gatewayip"); - NetOurSubnetMask= getenv_IPaddr ("netmask"); -@@ -2072,6 +2082,14 @@ restart: - tout = t1; - } - } -+ -+ if (ctrlc()) { -+ eth_halt(); -+ puts ("\nAbort\n"); -+ return (-1); -+ } -+ -+ - if(!httpd_upload_complete) - continue; - printf("Bytes transferred = %ld (%lx hex)\n", ---- a/net/uip-0.9/fsdata.c -+++ b/net/uip-0.9/fsdata.c -@@ -1,199 +1,108 @@ --static const char data_flashing_html[] = { -- /* /flashing.html */ -- 0x2f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x69, 0x6e, 0x67, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -- 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, -- 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, -- 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, -- 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, -- 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, -- 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, -- 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, -- 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, -- 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, -- 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0x3c, 0x62, -- 0x6f, 0x64, 0x79, 0x20, 0x73, 0x74, 0x79, 0x6c, 0x65, 0x3d, -- 0x22, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e, 0x3a, 0x20, 0x30, -- 0x70, 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x3b, 0x20, 0x68, -- 0x65, 0x69, 0x67, 0x68, 0x74, 0x3a, 0x31, 0x30, 0x30, 0x25, -- 0x3b, 0x20, 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, -- 0x66, 0x66, 0x66, 0x3b, 0x20, 0x62, 0x61, 0x63, 0x6b, 0x67, -- 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, 0x63, 0x6f, 0x6c, 0x6f, -- 0x72, 0x3a, 0x20, 0x23, 0x66, 0x62, 0x62, 0x30, 0x33, 0x34, -- 0x3b, 0x22, 0x3e, 0x3c, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, -- 0x3e, 0x3c, 0x68, 0x31, 0x3e, 0x55, 0x70, 0x67, 0x72, 0x61, -- 0x64, 0x69, 0x6e, 0x67, 0x20, 0x73, 0x79, 0x73, 0x74, 0x65, -- 0x6d, 0x20, 0x2e, 0x2e, 0x2e, 0x2e, 0x3c, 0x2f, 0x68, 0x31, -- 0x3e, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, -- 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0x3c, 0x2f, 0x68, -- 0x74, 0x6d, 0x6c, 0x3e, 0xa, }; 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-- --static const char data_index_html[] = { -- /* /index.html */ -- 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -- 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, -- 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, -- 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, -- 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, -- 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, -- 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, -- 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, -- 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, -- 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, -- 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x9, -- 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x9, 0x9, 0x3c, -- 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 0xa, 0x9, 0x9, 0x9, -- 0x4c, 0x61, 0x46, 0x6f, 0x6e, 0x65, 0x72, 0x61, 0x20, 0x46, -- 0x61, 0x69, 0x6c, 0x73, 0x61, 0x66, 0x65, 0x20, 0x55, 0x49, -- 0xa, 0x9, 0x9, 0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, -- 0x3e, 0xa, 0x9, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x3e, -- 0xa, 0x9, 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x73, 0x74, -- 0x79, 0x6c, 0x65, 0x3d, 0x22, 0x6d, 0x61, 0x72, 0x67, 0x69, -- 0x6e, 0x3a, 0x20, 0x30, 0x70, 0x74, 0x20, 0x61, 0x75, 0x74, -- 0x6f, 0x3b, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3a, -- 0x31, 0x30, 0x30, 0x25, 0x3b, 0x20, 0x63, 0x6f, 0x6c, 0x6f, -- 0x72, 0x3a, 0x20, 0x23, 0x30, 0x30, 0x30, 0x3b, 0x20, 0x62, -- 0x61, 0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, -- 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, 0x66, 0x62, -- 0x62, 0x30, 0x33, 0x34, 0x3b, 0x22, 0x3e, 0xa, 0x9, 0x9, -- 0x3c, 0x68, 0x31, 0x3e, 0x4c, 0x61, 0x46, 0x6f, 0x6e, 0x65, -- 0x72, 0x61, 0x20, 0x46, 0x61, 0x69, 0x6c, 0x73, 0x61, 0x66, -- 0x65, 0x20, 0x55, 0x49, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 0xa, -- 0x9, 0x9, 0x3c, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x6d, 0x65, -- 0x74, 0x68, 0x6f, 0x64, 0x3d, 0x22, 0x70, 0x6f, 0x73, 0x74, -- 0x22, 0x20, 0x65, 0x6e, 0x63, 0x74, 0x79, 0x70, 0x65, 0x3d, -- 0x22, 0x6d, 0x75, 0x6c, 0x74, 0x69, 0x70, 0x61, 0x72, 0x74, -- 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x2d, 0x64, 0x61, 0x74, 0x61, -- 0x22, 0x3e, 0xa, 0x9, 0x9, 0x9, 0x3c, 0x69, 0x6e, 0x70, -- 0x75, 0x74, 0x20, 0x74, 0x79, 0x70, 0x65, 0x3d, 0x66, 0x69, -- 0x6c, 0x65, 0x20, 0x6e, 0x61, 0x6d, 0x65, 0x3d, 0x66, 0x69, -- 0x72, 0x6d, 0x77, 0x61, 0x72, 0x65, 0x3e, 0xa, 0x9, 0x9, -- 0x9, 0x3c, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x20, 0x74, 0x79, -- 0x70, 0x65, 0x3d, 0x73, 0x75, 0x62, 0x6d, 0x69, 0x74, 0x3e, -- 0xa, 0x9, 0x9, 0x3c, 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x3e, -- 0xa, 0x9, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, -- 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, }; -- --static const char data_flash_html[] = { -- /* /flash.html */ -- 0x2f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, -- 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, -- 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, -- 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, -- 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, -- 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, -- 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, -- 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, -- 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, -- 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, -- 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x9, -- 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x9, 0x9, 0x3c, -- 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 0xa, 0x9, 0x9, 0x9, -- 0x4c, 0x61, 0x46, 0x6f, 0x6e, 0x65, 0x72, 0x61, 0x20, 0x46, -- 0x61, 0x69, 0x6c, 0x73, 0x61, 0x66, 0x65, 0x20, 0x55, 0x49, -- 0xa, 0x9, 0x9, 0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, -- 0x3e, 0xa, 0x9, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x3e, -- 0xa, 0x9, 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x73, 0x74, -- 0x79, 0x6c, 0x65, 0x3d, 0x22, 0x6d, 0x61, 0x72, 0x67, 0x69, -- 0x6e, 0x3a, 0x20, 0x30, 0x70, 0x74, 0x20, 0x61, 0x75, 0x74, -- 0x6f, 0x3b, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3a, -- 0x31, 0x30, 0x30, 0x25, 0x3b, 0x20, 0x63, 0x6f, 0x6c, 0x6f, -- 0x72, 0x3a, 0x20, 0x23, 0x30, 0x30, 0x30, 0x3b, 0x20, 0x62, -- 0x61, 0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, -- 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, 0x66, 0x62, -- 0x62, 0x30, 0x33, 0x34, 0x3b, 0x22, 0x3e, 0xa, 0x9, 0x9, -- 0x3c, 0x68, 0x31, 0x3e, 0x46, 0x6c, 0x61, 0x73, 0x68, 0x69, -- 0x6e, 0x67, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 0xa, 0x9, 0x9, -- 0x54, 0x68, 0x65, 0x20, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, -- 0x20, 0x69, 0x73, 0x20, 0x6e, 0x6f, 0x77, 0x20, 0x74, 0x72, -- 0x79, 0x69, 0x6e, 0x67, 0x20, 0x74, 0x6f, 0x20, 0x66, 0x6c, -- 0x61, 0x73, 0x68, 0x2e, 0x20, 0x49, 0x66, 0x20, 0x74, 0x68, -- 0x65, 0x72, 0x65, 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x70, -- 0x72, 0x6f, 0x62, 0x6c, 0x65, 0x6d, 0x2c, 0x20, 0x74, 0x68, -- 0x65, 0x20, 0x6c, 0x65, 0x64, 0x73, 0x20, 0x77, 0x69, 0x6c, -- 0x6c, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x6f, -- 0x20, 0x62, 0x6c, 0x69, 0x6e, 0x6b, 0x2e, 0xa, 0xa, 0x9, -- 0x9, 0x41, 0x66, 0x74, 0x65, 0x72, 0x20, 0x61, 0x20, 0x73, -- 0x75, 0x63, 0x63, 0x65, 0x73, 0x73, 0x66, 0x75, 0x6c, 0x6c, -- 0x20, 0x75, 0x70, 0x64, 0x61, 0x74, 0x65, 0x20, 0x74, 0x68, -- 0x65, 0x20, 0x62, 0x6f, 0x78, 0x20, 0x77, 0x69, 0x6c, 0x6c, -- 0x20, 0x72, 0x65, 0x62, 0x6f, 0x6f, 0x74, 0xa, 0x9, 0x3c, -- 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, -- 0x74, 0x6d, 0x6c, 0x3e, 0xa, }; -- --const struct fsdata_file file_flashing_html[] = {{NULL, data_flashing_html, data_flashing_html + 15, sizeof(data_flashing_html) - 15}}; -+static const char data_flashing_html[] = -+"HTTP/1.0 200 OK\n" -+"Server: uIP/0.9 (http://dunkels.com/adam/uip/)\n" -+"Content-type: text/html\n" -+"\n" -+"<html>\n" -+"\t<head>\n" -+"\t\t<title>\n" -+"\t\t\tFailsafe UI\n" -+"\t\t</title>\n" -+"\t</head>\n" -+"\t<body>\n" -+"\t\t<center><h1>Upgrading system...</h1></center>\n" -+"\t</body>\n" -+"</html>\n"; -+ -+static const char data_fail_html[] = -+"HTTP/1.0 200 OK\n" -+"Server: uIP/0.9 (http://dunkels.com/adam/uip/)\n" -+"Content-type: text/html\n" -+"\n" -+"<html>\n" -+"\t<head>\n" -+"\t\t<title>\n" -+"\t\t\tFailsafe UI\n" -+"\t\t</title>\n" -+"\t</head>\n" -+"\t<body>\n" -+"\t\t<h1>Flashing failed</h1>\n" -+"\t\tERROR - the image you uploaded failed to pass verification.<br>\n" -+"\t\tPlease make sure to use an official update provided by http://lantiq.com/\n" -+"\t</body>\n" -+"</html>\n"; -+ -+static const char data_404_html[] = -+"HTTP/1.0 404 File not found\n" -+"Server: uIP/0.9 (http://dunkels.com/adam/uip/)\n" -+"Content-type: text/html\n" -+"\n" -+"<html>\n" -+"\t<head>\n" -+"\t\t<title>\n" -+"\t\t\tFailsafe UI\n" -+"\t\t</title>\n" -+"\t</head>\n" -+"\t<body>\n" -+"\t\t<center><h1>404 - file not found</h1></center>\n" -+"\t</body>\n" -+"</html>\n"; -+ -+static const char data_index_html[] = -+"HTTP/1.0 200 OK\n" -+"Server: uIP/0.9 (http://dunkels.com/adam/uip/)\n" -+"Content-type: text/html\n" -+"\n" -+"<html>\n" -+"\t<head>\n" -+"\t\t<title>\n" -+"\t\t\tFailsafe UI\n" -+"\t\t</title>\n" -+"\t</head>\n" -+"\t<body>\n" -+"\t\t<h1>Failsafe UI</h1>\n" -+"\t\t<form method=\"post\" enctype=\"multipart/form-data\">\n" -+"\t\t\t<input type=file name=firmware>\n" -+"\t\t\t<input type=submit>\n" -+"\t\t</form>\n" -+"\t</body>\n" -+"</html>\n"; -+ -+static const char data_flash_html[] = -+"HTTP/1.0 200 OK\n" -+"Server: uIP/0.9 (http://dunkels.com/adam/uip/)\n" -+"Content-type: text/html\n" -+"\n" -+"<html>\n" -+"\t<head>\n" -+"\t\t<title>\n" -+"\t\t\tFailsafe UI\n" -+"\t\t</title>\n" -+"\t</head>\n" -+"\t<body>\n" -+"\t\t<h1>Flashing...</h1>\n" -+"\t\tThe system is now trying to flash. If there is a problem, the LEDs will " -+"start to blink.<br>\n" -+"\n" -+"\t\tAfter a successful update the box will reboot\n" -+"\t</body>\n" -+"</html>\n"; -+ -+const struct fsdata_file file_flashing_html[] = -+{{NULL, "/flashing.html", data_flashing_html, sizeof(data_flashing_html)}}; -+ -+const struct fsdata_file file_fail_html[] = -+{{file_flashing_html, "/fail.html", data_fail_html, sizeof(data_fail_html)}}; - --const struct fsdata_file file_fail_html[] = {{file_flashing_html, data_fail_html, data_fail_html + 11, sizeof(data_fail_html) - 11}}; -+const struct fsdata_file file_404_html[] = -+{{file_fail_html, "/404.html", data_404_html, sizeof(data_404_html)}}; - --const struct fsdata_file file_404_html[] = {{file_fail_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; -+const struct fsdata_file file_index_html[] = -+{{file_404_html, "/index.html", data_index_html, sizeof(data_index_html)}}; - --const struct fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; -- --const struct fsdata_file file_flash_html[] = {{file_index_html, data_flash_html, data_flash_html + 12, sizeof(data_flash_html) - 12}}; -+const struct fsdata_file file_flash_html[] = -+{{file_index_html, "/flash.html", data_flash_html, sizeof(data_flash_html)}}; - - #define FS_ROOT file_flash_html - --#define FS_NUMFILES 5 -\ No newline at end of file -+#define FS_NUMFILES 5 ---- a/net/uip-0.9/httpd.c -+++ b/net/uip-0.9/httpd.c -@@ -130,7 +130,7 @@ httpd_appcall(void) - if(!fs_open((const char *)&uip_appdata[4], &fsfile)) - { - PRINTLN("couldn't open file"); -- fs_open(file_index_html.name, &fsfile); -+ fs_open(file_404_html.name, &fsfile); - } - } - hs->script = 0; -@@ -141,7 +141,7 @@ httpd_appcall(void) - if(hs->state == HTTP_FIRMWARE) - { - unsigned char *start = (unsigned char*)uip_appdata; -- char *clen = strstr(start, "Content-Length:"); -+ char *clen = strstr((char *)start, "Content-Length:"); - int len = 0; - unsigned char *next, *end; - unsigned char *boundary_start; -@@ -150,14 +150,14 @@ httpd_appcall(void) - if(clen) - { - clen += sizeof("Content-Length:"); -- next = strstr(clen, eol); -+ next = (unsigned char *)strstr(clen, eol); - if(next) - { - len = atoi(clen); - next++; - printf("expecting %d bytes\n", len); - upload_data = httpd_upload_data = (unsigned char *)do_http_tmp_address(); -- printf("received data will be stored at 0x%08X\n", upload_data); -+ printf("received data will be stored at %p\n", upload_data); - if(!upload_data) - { - printf("failed to allocate memory\n"); -@@ -174,14 +174,14 @@ httpd_appcall(void) - uip_close(); - return; - } -- boundary_start = strstr(next, "---"); -+ boundary_start = (unsigned char *)strstr((char *)next, "---"); - if(!boundary_start) - { - uip_close(); - return; - } -- end = strstr(boundary_start, eol); -- if(!eol) -+ end = (unsigned char *)strstr((char *)boundary_start, eol); -+ if(!end) - { - uip_close(); - return; -@@ -189,13 +189,13 @@ httpd_appcall(void) - boundary_len = end - boundary_start; - memcpy(boundary, boundary_start, boundary_len); - boundary[boundary_len] = 0; -- next = strstr(boundary_start, "name=\"firmware\";"); -+ next = (unsigned char *)strstr((char *)boundary_start, "name=\"firmware\";"); - if(!next) - { - uip_close(); - return; - } -- next = strstr(next, eol2); -+ next = (unsigned char *)strstr((char *)next, eol2); - if(!next) - { - printf("could not find start of data\n"); -@@ -259,7 +259,6 @@ httpd_appcall(void) - { - if(upload_running) - { -- int i; - httpd_upload_complete = 1; - // for(i = 0; i < hs->upload_total; i++) - // printf("%c", httpd_upload_data[i]); -@@ -267,7 +266,7 @@ httpd_appcall(void) - uip_close(); - } - } -- uip_send(hs->dataptr, hs->count); -+ uip_send((unsigned char *)hs->dataptr, hs->count); - } - break; - diff --git a/package/uboot-lantiq/patches/300-arcadyan.patch b/package/uboot-lantiq/patches/300-arcadyan.patch deleted file mode 100644 index a91ac589f9..0000000000 --- a/package/uboot-lantiq/patches/300-arcadyan.patch +++ /dev/null @@ -1,98 +0,0 @@ ---- a/common/Makefile -+++ b/common/Makefile -@@ -127,7 +127,9 @@ - ifdef CONFIG_PCI - COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o - endif -+ifdef CONFIG_CMD_PCMCIA - COBJS-y += cmd_pcmcia.o -+endif - COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o - COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o - COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o ---- a/drivers/pcmcia/Makefile -+++ b/drivers/pcmcia/Makefile -@@ -28,9 +28,11 @@ - COBJS-$(CONFIG_I82365) += i82365.o - COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o - COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o --COBJS-y += rpx_pcmcia.o -+#COBJS-y += rpx_pcmcia.o -+COBJS-$(CONFIG_RPX_PCMCIA) += rpx_pcmcia.o - COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o --COBJS-y += tqm8xx_pcmcia.o -+#COBJS-y += tqm8xx_pcmcia.o -+COBJS-$(CONFIG_TQM8XX_PCMCIA) += tqm8xx_pcmcia.o - COBJS-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o - - COBJS := $(COBJS-y) ---- a/drivers/usb/phy/Makefile -+++ b/drivers/usb/phy/Makefile -@@ -23,7 +23,7 @@ - LIB := $(obj)libusb_phy.a - - COBJS-$(CONFIG_TWL4030_USB) += twl4030.o --COBJS-y := twl4030.o -+#COBJS-y := twl4030.o - - COBJS := $(COBJS-y) - SRCS := $(COBJS:.o=.c) ---- a/Makefile -+++ b/Makefile -@@ -3414,6 +3414,42 @@ - ## MIPS32 ifxcpe - ######################################################################### - -+define arcadyan -+$(1) : unconfig -+ @mkdir -p $(obj)include -+ @mkdir -p $(obj)board/arcadyan/ -+ @[ -z "$$(findstring brnboot,$$@)" ] || \ -+ { echo "TEXT_BASE = 0x80002000" >$(obj)board/arcadyan/config.tmp ; \ -+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \ -+ echo "#define CONFIG_SYS_BRNBOOT" >>$(obj)include/config.h ; \ -+ $(XECHO) "... with brnboot configuration" ; \ -+ } -+ @[ -z "$$(findstring ramboot,$$@)" ] || \ -+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/arcadyan/config.tmp ; \ -+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \ -+ $(XECHO) "... with ramboot configuration" ; \ -+ } -+ @if [ "$$(findstring flash,$$@)" ] ; then \ -+ echo "#TEXT_BASE = 0xB0050000" >$(obj)board/arcadyan/config.tmp ; \ -+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \ -+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \ -+ echo "#define CONFIG_USE_DDR_RAM_CFG_psc166" >>$(obj)include/config.h ; \ -+ fi -+ @$(MKCONFIG) -a $$(word 1,$$(subst _, ,$$@)) mips mips arcadyan "" danube -+endef -+ -+$(eval $(call arcadyan, arv3527P%config)) -+$(eval $(call arcadyan, arv4520PW%config)) -+$(eval $(call arcadyan, arv452CPW%config)) -+$(eval $(call arcadyan, arv4525PW%config)) -+$(eval $(call arcadyan, arv4510PW%config)) -+$(eval $(call arcadyan, arv4518PW%config)) -+$(eval $(call arcadyan, arv4519PW%config)) -+$(eval $(call arcadyan, arv7518PW%config)) -+$(eval $(call arcadyan, arv7525PW%config)) -+$(eval $(call arcadyan, arv752DPW%config)) -+$(eval $(call arcadyan, arv752DPW22%config)) -+ - easy50712%config : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/infineon/easy50712 ---- a/net/tftp.c -+++ b/net/tftp.c -@@ -11,9 +11,9 @@ - #include "bootp.h" - - #define WELL_KNOWN_PORT 69 /* Well known TFTP port # */ --#define TIMEOUT 5000UL /* Millisecs to timeout for lost pkt */ -+#define TIMEOUT 10000UL /* Millisecs to timeout for lost pkt */ - #ifndef CONFIG_NET_RETRY_COUNT --# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */ -+# define TIMEOUT_COUNT 200 /* # of timeouts before giving up */ - #else - # define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2) - #endif diff --git a/package/uboot-lantiq/patches/400-lzma.patch b/package/uboot-lantiq/patches/400-lzma.patch deleted file mode 100644 index b2f498ac5a..0000000000 --- a/package/uboot-lantiq/patches/400-lzma.patch +++ /dev/null @@ -1,1687 +0,0 @@ ---- a/.gitignore -+++ b/.gitignore -@@ -23,6 +23,11 @@ - /u-boot.hex - /u-boot.map - /u-boot.bin -+/u-boot.bin.bz2 -+/u-boot.bin.gz -+/u-boot.bin.lzma -+/u-boot.bin.lzo -+/u-boot.dis - /u-boot.srec - /u-boot.ldr - /u-boot.ldr.hex -@@ -30,6 +35,20 @@ - /u-boot.lds - /u-boot-onenand.bin - /u-boot-flexonenand.bin -+/u-boot-bootstrap -+/u-boot-bootstrap.hex -+/u-boot-bootstrap.map -+/u-boot-bootstrap.bin -+/u-boot-bootstrap.bin.bz2 -+/u-boot-bootstrap.bin.gz -+/u-boot-bootstrap.bin.lzma -+/u-boot-bootstrap.bin.lzo -+/u-boot-bootstrap.dis -+/u-boot-bootstrap.srec -+/u-boot-bootstrap.ldr -+/u-boot-bootstrap.ldr.hex -+/u-boot-bootstrap.ldr.srec -+/u-boot-bootstrap.lds - - # - # Generated files -@@ -38,6 +57,7 @@ - *.depend - /LOG - /errlog -+/.payload.s - /reloc_off - - # stgit generated dirs -@@ -63,3 +83,6 @@ - /onenand_ipl/onenand-ipl* - /onenand_ipl/board/*/onenand* - /onenand_ipl/board/*/*.S -+examples/standalone/ -+ -+setvars ---- a/Makefile -+++ b/Makefile -@@ -183,6 +183,12 @@ - - OBJS := $(addprefix $(obj),$(OBJS)) - -+ifeq ($(CONFIG_BOOTSTRAP),y) -+BOOTSTRAP_OBJS = cpu/$(ARCH)/start_bootstrap.o -+ -+BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_OBJS)) -+endif -+ - LIBS = lib_generic/libgeneric.a - LIBS += lib_generic/lzma/liblzma.a - LIBS += lib_generic/lzo/liblzo.a -@@ -254,6 +260,25 @@ - LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a - LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) - -+ifeq ($(CONFIG_BOOTSTRAP),y) -+BOOTSTRAP_LIBS = lib_generic/libgeneric_bootstrap.a -+BOOTSTRAP_LIBS += cpu/$(ARCH)/lib$(ARCH)_bootstrap.a -+BOOTSTRAP_LIBS += lib_$(ARCH)/lib$(ARCH)_bootstrap.a -+BOOTSTRAP_LIBS += common/libcommon_bootstrap.a -+BOOTSTRAP_LIBS-$(CONFIG_BOOTSTRAP_SERIAL) += drivers/serial/libserial.a -+ -+BOOTSTRAP_LIBS-$(CONFIG_BOOTSTRAP_LZMA) += lib_generic/lzma/liblzma.a -+BOOTSTRAP_LIBS-$(CONFIG_BOOTSTRAP_LZO) += lib/lzo/liblzo.a -+BOOTSTRAP_LIBS += $(BOOTSTRAP_LIBS-y) -+ -+BOOTSTRAP_LIBS := $(addprefix $(obj),$(BOOTSTRAP_LIBS)) -+.PHONY : $(BOOTSTRAP_LIBS) -+ -+BOOTSTRAP_LIBBOARD = board/$(BOARDDIR)/lib$(BOARD)_bootstrap.a -+BOOTSTRAP_LIBBOARD := $(addprefix $(obj),$(BOOTSTRAP_LIBBOARD)) -+endif -+ -+ - # Add GCC lib - ifdef USE_PRIVATE_LIBGCC - ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -@@ -267,6 +292,9 @@ - PLATFORM_LIBS += $(PLATFORM_LIBGCC) - export PLATFORM_LIBS - -+BOOTSTRAP_PLATFORM_LIBS += $(PLATFORM_LIBGCC) -+export BOOTSTRAP_PLATFORM_LIBS -+ - # Special flags for CPP when processing the linker script. - # Pass the version down so we can handle backwards compatibility - # on the fly. -@@ -289,12 +317,19 @@ - __OBJS := $(subst $(obj),,$(OBJS)) - __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) - -+__BOOTSTRAP_OBJS := $(subst $(obj),,$(BOOTSTRAP_OBJS)) -+__BOOTSTRAP_LIBS := $(subst $(obj),,$(BOOTSTRAP_LIBS)) $(subst $(obj),,$(BOOTSTRAP_LIBBOARD)) -+ - ######################################################################### - ######################################################################### - - # Always append ALL so that arch config.mk's can add custom ones - ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) - -+ifeq ($(CONFIG_BOOTSTRAP),y) -+ALL += $(obj)u-boot-bootstrap.srec $(obj)u-boot-bootstrap.bin -+endif -+ - all: $(ALL) - - $(obj)u-boot.hex: $(obj)u-boot -@@ -306,6 +341,19 @@ - $(obj)u-boot.bin: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -+$(obj)u-boot.bin.gz: $(obj)u-boot.bin -+ gzip -c $< > $@ -+ -+$(obj)u-boot.bin.lzma: $(obj)u-boot.bin -+ echo lzma -e -z -c $< $@ -+ lzma e $< $@ -+ -+$(obj)u-boot.bin.lzo: $(obj)u-boot.bin -+ lzop -9 -c $< > $@ -+ -+$(obj)u-boot.bin.bz2: $(obj)u-boot.bin -+ bzip2 --best -z -c $< > $@ -+ - $(obj)u-boot.ldr: $(obj)u-boot - $(CREATE_LDR_ENV) - $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) -@@ -335,12 +383,12 @@ - $(obj)tools/ubsha1 $(obj)u-boot.bin - - $(obj)u-boot.dis: $(obj)u-boot -- $(OBJDUMP) -d $< > $@ -+ $(OBJDUMP) -S -d $< > $@ - - GEN_UBOOT = \ - UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ - sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ -- cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ -+ cd $(LNDIR) && $(LD) --gc-sections $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot.map -o u-boot - $(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds -@@ -362,6 +410,120 @@ - $(LIBBOARD): depend $(LIBS) - $(MAKE) -C $(dir $(subst $(obj),,$@)) - -+# Bootstrap targets -+ -+ifeq ($(CONFIG_BOOTSTRAP),y) -+$(obj)u-boot-bootstrap.hex: $(obj)u-boot-bootstrap -+ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -+ -+$(obj)u-boot-bootstrap.srec: $(obj)u-boot-bootstrap -+ $(OBJCOPY) -O srec $< $@ -+ -+$(obj)u-boot-bootstrap.bin: $(obj)u-boot-bootstrap -+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -+ $(BOARD_SIZE_CHECK) -+ -+$(obj)u-boot-bootstrap.bin.gz: $(obj)u-boot-bootstrap.bin -+ gzip -c $< > $@ -+ -+$(obj)u-boot-bootstrap.bin.lzma: $(obj)u-boot-bootstrap.bin -+ lzma -e -z -c $< > $@ -+ -+$(obj)u-boot.bin-bootstrap.lzo: $(obj)u-boot-bootstrap.bin -+ lzop -9 -c $< > $@ -+ -+$(obj)u-boot.bin-bootstrap.bz2: $(obj)u-boot-bootstrap.bin -+ bzip2 --best -z -c $< > $@ -+ -+$(obj)u-boot-bootstrap.ldr: $(obj)u-boot-bootstrap -+ $(CREATE_LDR_ENV) -+ $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) -+ $(BOARD_SIZE_CHECK) -+ -+$(obj)u-boot-bootstrap.ldr.hex: $(obj)u-boot-bootstrap.ldr -+ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary -+ -+$(obj)u-boot-bootstrap.ldr.srec: $(obj)u-boot-bootstrap.ldr -+ $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary -+ -+$(obj)u-boot-bootstrap.img: $(obj)u-boot-bootstrap.bin -+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ -+ -a $(CONFIG_BOOTSTRAP_BASE) -e 0 \ -+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ -+ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -+ -d $< $@ -+ -+$(obj)u-boot-bootstrap.imx: $(obj)u-boot-bootstrap.bin -+ $(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \ -+ -e $(CONFIG_BOOTSTRAP_BASE) -d $< $@ -+ -+$(obj)u-boot-bootstrap.kwb: $(obj)u-boot-bootstrap.bin -+ $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ -+ -+$(obj)u-boot-bootstrap.sha1: $(obj)u-boot-bootstrap.bin -+ $(obj)tools/ubsha1 $(obj)u-boot-bootstrap.bin -+ -+$(obj)u-boot-bootstrap.dis: $(obj)u-boot-bootstrap -+ echo $(OBJDUMP) -S -d $< > $@ -+ $(OBJDUMP) -S -d $< > $@ -+ -+PAYLOAD_FILE_BASE=$(obj)u-boot.bin -+ifeq ($(CONFIG_BOOTSTRAP_GZIP),y) -+PAYLOAD_FILE_EXT:=.gz -+endif -+ifeq ($(CONFIG_BOOTSTRAP_LZMA),y) -+PAYLOAD_FILE_EXT:=.lzma -+endif -+ifeq ($(CONFIG_BOOTSTRAP_LZO),y) -+PAYLOAD_FILE_EXT:=.lzo -+endif -+ifeq ($(CONFIG_BOOTSTRAP_BZIP2),y) -+PAYLOAD_FILE_EXT:=.bz2 -+endif -+ -+PAYLOAD_FILE := $(PAYLOAD_FILE_BASE)$(PAYLOAD_FILE_EXT) -+ -+$(obj).payload.s: $(PAYLOAD_FILE) -+ echo ".globl payload_start" > $@ -+ echo ".globl payload_end" >> $@ -+ echo ".globl payload_size" >> $@ -+ echo ".globl payload_uncsize" >> $@ -+ echo .section .payload,\"a\",@progbits >> $@ -+ echo "payload_size:" >> $@ -+ echo -n ".word " >> $@ -+ wc -c $(PAYLOAD_FILE) | cut -f1 -d' ' >> $@ -+ echo "payload_uncsize:" >> $@ -+ echo -n ".word " >> $@ -+ wc -c $(obj)u-boot.bin | cut -f1 -d' ' >> $@ -+ echo "payload_start:" >> $@ -+ echo .incbin \"$(PAYLOAD_FILE)\" >> $@ -+ echo "payload_end:" >> $@ -+ -+ -+GEN_UBOOT_BOOTSTRAP = \ -+ UNDEF_SYM=`$(OBJDUMP) -x $(BOOTSTRAP_LIBBOARD) $(BOOTSTRAP_LIBS) | \ -+ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ -+ cd $(LNDIR) && $(LD) --gc-sections $(BOOTSTRAP_LDFLAGS) $$UNDEF_SYM $(obj).payload.o $(__BOOTSTRAP_OBJS) \ -+ --start-group $(__BOOTSTRAP_LIBS) --end-group $(BOOTSTRAP_PLATFORM_LIBS) \ -+ -Map u-boot-bootstrap.map -o u-boot-bootstrap -+ -+$(obj)u-boot-bootstrap: depend $(SUBDIRS) $(BOOTSTRAP_OBJS) $(BOOTSTRAP_LIBS) $(BOOTSTRAP_LDSCRIPT) $(obj)u-boot-bootstrap.lds $(obj).payload.o #$(BOOTSTRAP_LIBBOARD) -+ #echo "--------$(BOOTSTRAP_LIBBOARD)" -+ #echo "$(GEN_UBOOT_BOOTSTRAP)" -+ $(GEN_UBOOT_BOOTSTRAP) -+ifeq ($(CONFIG_KALLSYMS),y) -+ smap=`$(call SYSTEM_MAP,u-boot-bootstrap) | \ -+ awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ -+ $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \ -+ -c common/system_map.c -o $(obj)common/system_map.o -+ $(GEN_UBOOT_BOOTSTRAP) $(obj)common/system_map.o -+endif -+ -+$(BOOTSTRAP_LIBBOARD): depend $(BOOTSTRAP_LIBS) -+ $(MAKE) -C $(dir $(subst $(obj),,$@)) $(notdir $@) -+endif -+ - $(SUBDIRS): depend - $(MAKE) -C $@ all - -@@ -371,6 +533,9 @@ - $(obj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -+$(obj)u-boot-bootstrap.lds: $(BOOTSTRAP_LDSCRIPT) -+ $(CPP) $(CPPFLAGS) $(BOOTSTRAP_LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ -+ - $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C nand_spl/board/$(BOARDDIR) all - -@@ -3829,6 +3994,7 @@ - $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ - $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ - $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ -+ $(obj)u-boot-bootstrap.lds \ - $(obj)lib_blackfin/u-boot.lds \ - $(obj)u-boot.lds \ - $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] -@@ -3853,6 +4019,12 @@ - @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) - @rm -f $(obj)u-boot.kwb - @rm -f $(obj)u-boot.imx -+ @rm -f $(obj)u-boot.bin{.gz,.lzma,.lzo,.bz2} -+ @rm -f $(obj)u-boot-bootstrap $(obj)u-boot-bootstrap.map $(obj)u-boot-bootstrap.hex -+ @rm -f $(obj)u-boot-bootstrap.kwb -+ @rm -f $(obj)u-boot-bootstrap.imx -+ @rm -f $(obj)u-boot-bootstrap.bin{.gz,.lzma,.lzo,.bz2} -+ @rm -f $(obj).payload.s - @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} - @rm -f $(obj)cpu/mpc824x/bedbug_603e.c - @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm ---- a/lib_mips/config.mk -+++ b/lib_mips/config.mk -@@ -47,6 +47,6 @@ - # On the other hand, we want PIC in the U-Boot code to relocate it from ROM - # to RAM. $28 is always used as gp. - # --PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -g - PLATFORM_CPPFLAGS += -msoft-float - PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib ---- /dev/null -+++ b/cpu/mips/reset.c -@@ -0,0 +1,39 @@ -+/* -+ * (C) Copyright 2003 -+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+#include <command.h> -+#include <asm/mipsregs.h> -+#include <asm/reboot.h> -+ -+void __attribute__((weak)) _machine_restart(void) -+{ -+} -+ -+int __attribute__((weak)) do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -+{ -+ _machine_restart(); -+ -+ fprintf(stderr, "*** reset failed ***\n"); -+ return 0; -+} ---- /dev/null -+++ b/cpu/mips/reset_bootstrap.c -@@ -0,0 +1,39 @@ -+/* -+ * (C) Copyright 2003 -+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+#include <command.h> -+#include <asm/mipsregs.h> -+#include <asm/reboot.h> -+ -+void __attribute__((weak)) _machine_restart(void) -+{ -+} -+ -+int __attribute__((weak)) do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -+{ -+ _machine_restart(); -+ -+ printf("*** reset failed ***\n"); -+ return 0; -+} ---- /dev/null -+++ b/cpu/mips/start_bootstrap.S -@@ -0,0 +1,534 @@ -+/* -+ * Startup Code for MIPS32 CPU-core base on start.S source -+ * -+ * Copyright (c) 2010 Industrie Dial Face S.p.A. -+ * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> -+ * -+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+//#include <generated/generic-asm-offsets.h> -+#include <config.h> -+#include <asm/regdef.h> -+//#include <asm/mipsregs.h> -+#define CP0_INDEX $0 -+#define CP0_RANDOM $1 -+#define CP0_ENTRYLO0 $2 -+#define CP0_ENTRYLO1 $3 -+#define CP0_CONF $3 -+#define CP0_CONTEXT $4 -+#define CP0_PAGEMASK $5 -+#define CP0_WIRED $6 -+#define CP0_INFO $7 -+#define CP0_BADVADDR $8 -+#define CP0_COUNT $9 -+#define CP0_ENTRYHI $10 -+#define CP0_COMPARE $11 -+#define CP0_STATUS $12 -+#define CP0_CAUSE $13 -+#define CP0_EPC $14 -+#define CP0_PRID $15 -+#define CP0_EBASE $15,1 -+#define CP0_CONFIG $16 -+#define CP0_LLADDR $17 -+#define CP0_WATCHLO $18 -+#define CP0_WATCHHI $19 -+#define CP0_XCONTEXT $20 -+#define CP0_FRAMEMASK $21 -+#define CP0_DIAGNOSTIC $22 -+#define CP0_DEBUG $23 -+#define CP0_DEPC $24 -+#define CP0_PERFORMANCE $25 -+#define CP0_ECC $26 -+#define CP0_CACHEERR $27 -+#define CP0_TAGLO $28 -+#define CP0_TAGHI $29 -+#define CP0_ERROREPC $30 -+#define CP0_DESAVE $31 -+#define ST0_CU0 0x10000000 -+#define CONF_CM_UNCACHED 2 -+#define CONF_CM_CACHABLE_NONCOHERENT 3 -+#define EBASEB_CPUNUM 0 -+#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM) -+#define MIPS_CONF7_RPS 4 //((unsigned long)(1) << 2) -+#define CONF_CM_CACHABLE_NONCOHERENT 3 -+#ifndef CONFIG_SYS_MIPS_CACHE_OPER_MODE -+#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NONCOHERENT -+#endif -+ -+ /* -+ * For the moment disable interrupts, mark the kernel mode and -+ * set ST0_KX so that the CPU does not spit fire when using -+ * 64-bit addresses. -+ */ -+ .macro setup_c0_status set clr -+ .set push -+ mfc0 t0, CP0_STATUS -+ or t0, ST0_CU0 | \set | 0x1f | \clr -+ xor t0, 0x1f | \clr -+ mtc0 t0, CP0_STATUS -+ .set noreorder -+ sll zero, 3 # ehb -+ .set pop -+ .endm -+ -+ .macro setup_c0_status_reset -+#ifdef CONFIG_64BIT -+ setup_c0_status ST0_KX 0 -+#else -+ setup_c0_status 0 0 -+#endif -+ .endm -+ -+#define RVECENT(f,n) \ -+ b f; nop -+#define XVECENT(f,bev) \ -+ b f ; \ -+ li k0,bev -+ -+ .set noreorder -+ -+ .globl _start -+ .text -+_start: -+ RVECENT(reset,0) /* U-boot entry point */ -+ RVECENT(reset,1) /* software reboot */ -+#if defined(CONFIG_INCA_IP) -+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -+ .word 0x00000000 /* phase of the flash */ -+#elif defined(CONFIG_PURPLE) -+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -+#else -+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -+ .word 0x00000000 /* phase of the flash */ -+#endif -+ RVECENT(romReserved,3) -+ RVECENT(romReserved,4) -+ RVECENT(romReserved,5) -+ RVECENT(romReserved,6) -+ RVECENT(romReserved,7) -+ RVECENT(romReserved,8) -+ RVECENT(romReserved,9) -+ RVECENT(romReserved,10) -+ RVECENT(romReserved,11) -+ RVECENT(romReserved,12) -+ RVECENT(romReserved,13) -+ RVECENT(romReserved,14) -+ RVECENT(romReserved,15) -+ RVECENT(romReserved,16) -+ RVECENT(romReserved,17) -+ RVECENT(romReserved,18) -+ RVECENT(romReserved,19) -+ RVECENT(romReserved,20) -+ RVECENT(romReserved,21) -+ RVECENT(romReserved,22) -+ RVECENT(romReserved,23) -+ RVECENT(romReserved,24) -+ RVECENT(romReserved,25) -+ RVECENT(romReserved,26) -+ RVECENT(romReserved,27) -+ RVECENT(romReserved,28) -+ RVECENT(romReserved,29) -+ RVECENT(romReserved,30) -+ RVECENT(romReserved,31) -+ RVECENT(romReserved,32) -+ RVECENT(romReserved,33) -+ RVECENT(romReserved,34) -+ RVECENT(romReserved,35) -+ RVECENT(romReserved,36) -+ RVECENT(romReserved,37) -+ RVECENT(romReserved,38) -+ RVECENT(romReserved,39) -+ RVECENT(romReserved,40) -+ RVECENT(romReserved,41) -+ RVECENT(romReserved,42) -+ RVECENT(romReserved,43) -+ RVECENT(romReserved,44) -+ RVECENT(romReserved,45) -+ RVECENT(romReserved,46) -+ RVECENT(romReserved,47) -+ RVECENT(romReserved,48) -+ RVECENT(romReserved,49) -+ RVECENT(romReserved,50) -+ RVECENT(romReserved,51) -+ RVECENT(romReserved,52) -+ RVECENT(romReserved,53) -+ RVECENT(romReserved,54) -+ RVECENT(romReserved,55) -+ RVECENT(romReserved,56) -+ RVECENT(romReserved,57) -+ RVECENT(romReserved,58) -+ RVECENT(romReserved,59) -+ RVECENT(romReserved,60) -+ RVECENT(romReserved,61) -+ RVECENT(romReserved,62) -+ RVECENT(romReserved,63) -+ XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ -+ RVECENT(romReserved,65) -+ RVECENT(romReserved,66) -+ RVECENT(romReserved,67) -+ RVECENT(romReserved,68) -+ RVECENT(romReserved,69) -+ RVECENT(romReserved,70) -+ RVECENT(romReserved,71) -+ RVECENT(romReserved,72) -+ RVECENT(romReserved,73) -+ RVECENT(romReserved,74) -+ RVECENT(romReserved,75) -+ RVECENT(romReserved,76) -+ RVECENT(romReserved,77) -+ RVECENT(romReserved,78) -+ RVECENT(romReserved,79) -+ XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ -+ RVECENT(romReserved,81) -+ RVECENT(romReserved,82) -+ RVECENT(romReserved,83) -+ RVECENT(romReserved,84) -+ RVECENT(romReserved,85) -+ RVECENT(romReserved,86) -+ RVECENT(romReserved,87) -+ RVECENT(romReserved,88) -+ RVECENT(romReserved,89) -+ RVECENT(romReserved,90) -+ RVECENT(romReserved,91) -+ RVECENT(romReserved,92) -+ RVECENT(romReserved,93) -+ RVECENT(romReserved,94) -+ RVECENT(romReserved,95) -+ XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ -+ RVECENT(romReserved,97) -+ RVECENT(romReserved,98) -+ RVECENT(romReserved,99) -+ RVECENT(romReserved,100) -+ RVECENT(romReserved,101) -+ RVECENT(romReserved,102) -+ RVECENT(romReserved,103) -+ RVECENT(romReserved,104) -+ RVECENT(romReserved,105) -+ RVECENT(romReserved,106) -+ RVECENT(romReserved,107) -+ RVECENT(romReserved,108) -+ RVECENT(romReserved,109) -+ RVECENT(romReserved,110) -+ RVECENT(romReserved,111) -+ XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ -+ RVECENT(romReserved,113) -+ RVECENT(romReserved,114) -+ RVECENT(romReserved,115) -+ RVECENT(romReserved,116) -+ RVECENT(romReserved,116) -+ RVECENT(romReserved,118) -+ RVECENT(romReserved,119) -+ RVECENT(romReserved,120) -+ RVECENT(romReserved,121) -+ RVECENT(romReserved,122) -+ RVECENT(romReserved,123) -+ RVECENT(romReserved,124) -+ RVECENT(romReserved,125) -+ RVECENT(romReserved,126) -+ RVECENT(romReserved,127) -+ -+ /* We hope there are no more reserved vectors! -+ * 128 * 8 == 1024 == 0x400 -+ * so this is address R_VEC+0x400 == 0xbfc00400 -+ */ -+#if 1 -+ XVECENT(romExcHandle,0x400); /* bfc00400: Int, CauseIV=1 */ -+ RVECENT(romReserved,129); -+ RVECENT(romReserved,130); -+ RVECENT(romReserved,131); -+ RVECENT(romReserved,132); -+ RVECENT(romReserved,133); -+ RVECENT(romReserved,134); -+ RVECENT(romReserved,135); -+ RVECENT(romReserved,136); -+ RVECENT(romReserved,137); -+ RVECENT(romReserved,138); -+ RVECENT(romReserved,139); -+ RVECENT(romReserved,140); -+ RVECENT(romReserved,141); -+ RVECENT(romReserved,142); -+ RVECENT(romReserved,143); -+ XVECENT(romExcHandle,0x480); /* bfc00480: EJTAG debug exception */ -+#elif defined(CONFIG_PURPLE) -+/* 0xbfc00400 */ -+ .word 0xdc870000 -+ .word 0xfca70000 -+ .word 0x20840008 -+ .word 0x20a50008 -+ .word 0x20c6ffff -+ .word 0x14c0fffa -+ .word 0x00000000 -+ .word 0x03e00008 -+ .word 0x00000000 -+ .word 0x00000000 -+/* 0xbfc00428 */ -+ .word 0xdc870000 -+ .word 0xfca70000 -+ .word 0x20840008 -+ .word 0x20a50008 -+ .word 0x20c6ffff -+ .word 0x14c0fffa -+ .word 0x00000000 -+ .word 0x03e00008 -+ .word 0x00000000 -+ .word 0x00000000 -+#endif /* CONFIG_PURPLE */ -+ .align 4 -+reset: -+#ifdef CONFIG_SYS_MIPS_MULTI_CPU -+ mfc0 k0, CP0_EBASE -+ and k0, EBASEF_CPUNUM -+ bne k0, zero, ifx_mips_handler_cpux -+ nop -+#endif -+ /* Clear watch registers. -+ */ -+ mtc0 zero, CP0_WATCHLO -+ mtc0 zero, CP0_WATCHHI -+ -+ /* WP(Watch Pending), SW0/1 should be cleared. */ -+ mtc0 zero, CP0_CAUSE -+ -+ setup_c0_status_reset -+#if defined(CONFIG_MIPS24KEC) || defined(CONFIG_MIPS34KC) -+ /* CONFIG7 register */ -+ /* Erratum "RPS May Cause Incorrect Instruction Execution" -+ * for 24KEC and 34KC */ -+ mfc0 k0, CP0_CONFIG, 7 -+ li k1, MIPS_CONF7_RPS -+ or k0, k1 -+ mtc0 k0, CP0_CONFIG, 7 -+#endif -+ -+ /* Init Timer */ -+ mtc0 zero, CP0_COUNT -+ mtc0 zero, CP0_COMPARE -+ -+ /* CONFIG0 register */ -+ li t0, CONF_CM_UNCACHED -+ mtc0 t0, CP0_CONFIG -+ -+ /* Initialize $gp. -+ */ -+ bal 1f -+ nop -+ .word _gp -+1: -+ lw gp, 0(ra) -+ -+ /* Initialize any external memory. -+ */ -+ la t9, lowlevel_init -+ jalr t9 -+ nop -+ -+ /* Initialize caches... -+ */ -+ la t9, mips_cache_reset -+ jalr t9 -+ nop -+ -+ /* ... and enable them. -+ */ -+ li t0, CONF_CM_CACHABLE_NONCOHERENT /*CONFIG_SYS_MIPS_CACHE_OPER_MODE*/ -+ mtc0 t0, CP0_CONFIG -+ -+ /* Set up temporary stack. -+ */ -+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS -+ li a0, CONFIG_SYS_INIT_SP_OFFSET -+ la t9, mips_cache_lock -+ jalr t9 -+ nop -+#endif -+ -+ li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET -+ la sp, 0(t0) -+ -+ la t9, bootstrap_board_init_f -+ jr t9 -+ nop -+ -+/* -+ * void relocate_code (addr_sp, gd, addr_moni) -+ * -+ * This "function" does not return, instead it continues in RAM -+ * after relocating the monitor code. -+ * -+ * a0 = addr_sp -+ * a1 = gd -+ * a2 = destination address -+ */ -+ .globl relocate_code -+ .ent relocate_code -+relocate_code: -+ move sp, a0 /* Set new stack pointer */ -+ -+ li t0, CONFIG_BOOTSTRAP_TEXT_BASE -+ la t3, in_ram -+ lw t2, -12(t3) /* t2 <-- uboot_end_data */ -+ move t1, a2 -+ move s2, a2 /* s2 <-- destination address */ -+ -+ /* -+ * Fix $gp: -+ * -+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address -+ */ -+ move t6, gp -+ sub gp, CONFIG_BOOTSTRAP_TEXT_BASE -+ add gp, a2 /* gp now adjusted */ -+ sub s1, gp, t6 /* s1 <-- relocation offset */ -+ -+ /* -+ * t0 = source address -+ * t1 = target address -+ * t2 = source end address -+ */ -+ -+ /* -+ * Save destination address and size for later usage in flush_cache() -+ */ -+ move s0, a1 /* save gd in s0 */ -+ move a0, t1 /* a0 <-- destination addr */ -+ sub a1, t2, t0 /* a1 <-- size */ -+ -+ /* On the purple board we copy the code earlier in a special way -+ * in order to solve flash problems -+ */ -+#ifndef CONFIG_PURPLE -+1: -+ lw t3, 0(t0) -+ sw t3, 0(t1) -+ addu t0, 4 -+ ble t0, t2, 1b -+ addu t1, 4 /* delay slot */ -+#endif -+ -+ /* If caches were enabled, we would have to flush them here. -+ */ -+ -+ /* a0 & a1 are already set up for flush_cache(start, size) */ -+ la t9, flush_cache -+ jalr t9 -+ nop -+ -+ /* Jump to where we've relocated ourselves. -+ */ -+ addi t0, s2, in_ram - _start -+ jr t0 -+ nop -+ -+ .word _gp -+ .word _GLOBAL_OFFSET_TABLE_ -+ .word uboot_end_data -+ .word uboot_end -+ .word num_got_entries -+ -+in_ram: -+ /* -+ * Now we want to update GOT. -+ * -+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object -+ * generated by GNU ld. Skip these reserved entries from relocation. -+ */ -+ lw t3, -4(t0) /* t3 <-- num_got_entries */ -+ lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */ -+ lw t5, -20(t0) /* t5 <-- _gp */ -+ sub t4, t5 /* compute offset*/ -+ add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */ -+ addi t4, t4, 8 /* Skipping first two entries. */ -+ li t2, 2 -+1: -+ lw t1, 0(t4) -+ beqz t1, 2f -+ add t1, s1 -+ sw t1, 0(t4) -+2: -+ addi t2, 1 -+ blt t2, t3, 1b -+ addi t4, 4 /* delay slot */ -+ -+ /* Clear BSS. -+ */ -+ lw t1, -12(t0) /* t1 <-- uboot_end_data */ -+ lw t2, -8(t0) /* t2 <-- uboot_end */ -+ add t1, s1 /* adjust pointers */ -+ add t2, s1 -+ -+ sub t1, 4 -+1: -+ addi t1, 4 -+ bltl t1, t2, 1b -+ sw zero, 0(t1) /* delay slot */ -+ -+ move a0, s0 /* a0 <-- gd */ -+ la t9, bootstrap_board_init_r -+ jr t9 -+ move a1, s2 /* delay slot */ -+ -+ .end relocate_code -+ -+/* -+ * void copy_and_jump (void) -+ * -+ * This function copies/unzips the u-boot image and runs it. -+ * This "function" does not return -+ * -+*/ -+ .globl copy_and_jump -+ .ent copy_and_jump -+copy_and_jump: -+ -+ /* copy_uboot(CONFIG_SYS_MONITOR_BASE, payload_uncsize, payload_start, payload_size) */ -+ li a0, CONFIG_SYS_MONITOR_BASE -+ la a1, payload_uncsize -+ lw a1, 0(a1) -+ la a2, payload_start -+ la a3, payload_size -+ la t9, copy_uboot -+ jalr t9 -+ lw a3, 0(a3) /* delay slot */ -+ -+ li t9, CONFIG_SYS_MONITOR_BASE -+ jr t9 -+ nop -+ -+ .end copy_and_jump -+ -+ /* Exception handlers. -+ */ -+romReserved: -+ b romReserved -+ -+romExcHandle: -+ b romExcHandle -+#ifdef CONFIG_SYS_MIPS_MULTI_CPU -+/* -+ * Stop Slave CPUs -+ */ -+ifx_mips_handler_cpux: -+ wait; -+ b ifx_mips_handler_cpux; -+ nop; -+#endif ---- a/lib_mips/Makefile -+++ b/lib_mips/Makefile -@@ -24,6 +24,9 @@ - include $(TOPDIR)/config.mk - - LIB = $(obj)lib$(ARCH).a -+BOOTSTRAP_LIB = $(obj)lib$(ARCH)_bootstrap.a -+ -+BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - - SOBJS-y += - -@@ -35,12 +38,21 @@ - endif - COBJS-y += time.o - --SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += board_bootstrap.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += time.o -+ -+BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y) $(BOOTSTRAP_COBJS-y)) -+ -+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c) - OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - -+all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB) - $(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -+$(BOOTSTRAP_LIB): $(obj).depend $(BOOTSTRAP_OBJS) -+ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) -+ - ######################################################################### - - # defines $(obj).depend target ---- /dev/null -+++ b/lib_mips/board_bootstrap.c -@@ -0,0 +1,270 @@ -+/* -+ * (C) Copyright 2010 Industrie Dial Face S.p.A. -+ * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com -+ * -+ * (C) Copyright 2003 -+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+#include <command.h> -+#include <malloc.h> -+#include <stdio_dev.h> -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+extern int timer_init(void); -+ -+extern int incaip_set_cpuclk(void); -+ -+extern ulong uboot_end_data; -+extern ulong uboot_end; -+ -+#ifdef CONFIG_BOOTSTRAP_SERIAL -+static char *failed = "*** failed ***\n"; -+#endif -+/* -+ * mips_io_port_base is the begin of the address space to which x86 style -+ * I/O ports are mapped. -+ */ -+unsigned long mips_io_port_base = -1; -+ -+int __board_early_init_f(void) -+{ -+ /* -+ * Nothing to do in this dummy implementation -+ */ -+ return 0; -+} -+ -+int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f"))); -+int bootstrap_board_early_init_f(void) __attribute__((weak, alias("board_early_init_f"))); -+ -+static int bootstrap_init_func_ram (void) -+{ -+ if ((gd->ram_size = bootstrap_initdram (0)) > 0) { -+ return (0); -+ } -+#ifdef CONFIG_BOOTSTRAP_SERIAL -+ puts (failed); -+#endif -+ return (1); -+} -+ -+static int bootstrap_display_banner(void) -+{ -+#ifdef CONFIG_BOOTSTRAP_SERIAL -+ puts ("bootstrap..."); -+#endif -+ return (0); -+} -+ -+static int bootstrap_init_baudrate (void) -+{ -+#if defined(CONFIG_BOOTSTRAP_BAUDRATE) -+ gd->baudrate = CONFIG_BOOTSTRAP_BAUDRATE; -+#else -+ gd->baudrate = CONFIG_BAUDRATE; -+#endif -+ return 0; -+} -+ -+/* -+ * Breath some life into the board... -+ * -+ * The first part of initialization is running from Flash memory; -+ * its main purpose is to initialize the RAM so that we -+ * can relocate the monitor code to RAM. -+ */ -+ -+/* -+ * All attempts to come up with a "common" initialization sequence -+ * that works for all boards and architectures failed: some of the -+ * requirements are just _too_ different. To get rid of the resulting -+ * mess of board dependend #ifdef'ed code we now make the whole -+ * initialization sequence configurable to the user. -+ * -+ * The requirements for any new initalization function is simple: it -+ * receives a pointer to the "global data" structure as it's only -+ * argument, and returns an integer return code, where 0 means -+ * "continue" and != 0 means "fatal error, hang the system". -+ */ -+typedef int (init_fnc_t) (void); -+ -+static init_fnc_t *init_sequence[] = { -+ bootstrap_board_early_init_f, -+ timer_init, -+ bootstrap_init_baudrate,/* initialze baudrate settings */ -+#ifdef CONFIG_BOOTSTRAP_SERIAL -+ serial_init, /* serial communications setup */ -+#endif -+ bootstrap_display_banner, /* say that we are here */ -+ bootstrap_checkboard, -+ bootstrap_init_func_ram, -+ NULL, -+}; -+ -+ -+void bootstrap_board_init_f(ulong bootflag) -+{ -+ gd_t gd_data, *id; -+ bd_t *bd; -+ init_fnc_t **init_fnc_ptr; -+ ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_BOOTSTRAP_TEXT_BASE; -+ ulong *s; -+ -+ /* Pointer is writable since we allocated a register for it. -+ */ -+ gd = &gd_data; -+ /* compiler optimization barrier needed for GCC >= 3.4 */ -+ __asm__ __volatile__("": : :"memory"); -+ -+ memset ((void *)gd, 0, sizeof (gd_t)); -+ -+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { -+ if ((*init_fnc_ptr)() != 0) { -+ bootstrap_hang (); -+ } -+ } -+ -+ /* -+ * Now that we have DRAM mapped and working, we can -+ * relocate the code and continue running from DRAM. -+ */ -+ addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; -+ -+ /* We can reserve some RAM "on top" here. -+ */ -+ -+ /* round down to next 4 kB limit. -+ */ -+ addr &= ~(4096 - 1); -+ debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); -+ -+ /* Reserve memory for U-Boot code, data & bss -+ * round down to next 16 kB limit -+ */ -+ addr -= len; -+ addr &= ~(16 * 1024 - 1); -+ -+ debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); -+ -+ /* Reserve memory for malloc() arena. -+ */ -+ addr_sp = addr - CONFIG_SYS_MALLOC_LEN; -+ debug ("Reserving %dk for malloc() at: %08lx\n", -+ CONFIG_SYS_MALLOC_LEN >> 10, addr_sp); -+ -+ /* -+ * (permanently) allocate a Board Info struct -+ * and a permanent copy of the "global" data -+ */ -+ addr_sp -= sizeof(bd_t); -+ bd = (bd_t *)addr_sp; -+ gd->bd = bd; -+ debug ("Reserving %zu Bytes for Board Info at: %08lx\n", -+ sizeof(bd_t), addr_sp); -+ -+ addr_sp -= sizeof(gd_t); -+ id = (gd_t *)addr_sp; -+ debug ("Reserving %zu Bytes for Global Data at: %08lx\n", -+ sizeof (gd_t), addr_sp); -+ -+ /* Reserve memory for boot params. -+ */ -+ addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN; -+ bd->bi_boot_params = addr_sp; -+ debug ("Reserving %dk for boot params() at: %08lx\n", -+ CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp); -+ -+ /* -+ * Finally, we set up a new (bigger) stack. -+ * -+ * Leave some safety gap for SP, force alignment on 16 byte boundary -+ * Clear initial stack frame -+ */ -+ addr_sp -= 16; -+ addr_sp &= ~0xF; -+ s = (ulong *)addr_sp; -+ *s-- = 0; -+ *s-- = 0; -+ addr_sp = (ulong)s; -+ debug ("Stack Pointer at: %08lx\n", addr_sp); -+ -+ /* -+ * Save local variables to board info struct -+ */ -+ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */ -+ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ -+ bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ -+ -+ memcpy (id, (void *)gd, sizeof (gd_t)); -+ -+ /* On the purple board we copy the code in a special way -+ * in order to solve flash problems -+ */ -+ relocate_code (addr_sp, id, addr); -+ -+ /* NOTREACHED - relocate_code() does not return */ -+} -+/************************************************************************ -+ * -+ * This is the next part if the initialization sequence: we are now -+ * running from RAM and have a "normal" C environment, i. e. global -+ * data can be written, BSS has been cleared, the stack size in not -+ * that critical any more, etc. -+ * -+ ************************************************************************ -+ */ -+ -+void bootstrap_board_init_r (gd_t *id, ulong dest_addr) -+{ -+ extern void malloc_bin_reloc (void); -+ extern void copy_and_jump(void); -+ -+ bd_t *bd; -+ -+ gd = id; -+ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ -+ -+ debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); -+ -+ gd->reloc_off = dest_addr - CONFIG_BOOTSTRAP_TEXT_BASE; -+ -+ bd = gd->bd; -+ -+ /* The Malloc area is immediately below the monitor copy in DRAM */ -+ mem_malloc_init(CONFIG_BOOTSTRAP_BASE + gd->reloc_off - -+ CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); -+ malloc_bin_reloc(); -+ -+ copy_and_jump(); -+ -+ /* NOTREACHED - no way out of command loop except booting */ -+} -+ -+void bootstrap_hang (void) -+{ -+#ifdef CONFIG_BOOTSTRAP_SERIAL -+ puts ("### ERROR ### Please RESET the board ###\n"); -+#endif -+ for (;;); -+} ---- a/common/Makefile -+++ b/common/Makefile -@@ -24,6 +24,9 @@ - include $(TOPDIR)/config.mk - - LIB = $(obj)libcommon.a -+BOOTSTRAP_LIB = $(obj)libcommon_bootstrap.a -+ -+BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - - AOBJS = - -@@ -168,18 +171,27 @@ - COBJS-$(CONFIG_UPDATE_TFTP) += update.o - COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o - -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += dlmalloc.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_SERIAL) += console_bootstrap.o -+ -+BOOTSTRAP_COBJS := $(sort $(BOOTSTRAP_COBJS-y)) -+BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS)) -+ - - COBJS := $(sort $(COBJS-y)) --SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_COBJS:.o=.c) - OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) - - CPPFLAGS += -I.. - --all: $(LIB) $(AOBJS) -+all: $(LIB) $(BOOTSTRAP_LIB-y) $(AOBJS) - - $(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -+$(BOOTSTRAP_LIB): $(obj).depend $(BOOTSTRAP_OBJS) -+ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) -+ - $(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc - $(CC) $(AFLAGS) -Wa,--no-warn \ - -DENV_CRC=$(shell $(obj)../tools/envcrc) \ ---- /dev/null -+++ b/common/console_bootstrap.c -@@ -0,0 +1,81 @@ -+/* -+ * (C) Copyright 2000 -+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+#include <stdarg.h> -+#include <malloc.h> -+ -+/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/ -+ -+int getc(void) -+{ -+ /* Send directly to the handler */ -+ return serial_getc(); -+} -+ -+int tstc(void) -+{ -+ /* Send directly to the handler */ -+ return serial_tstc(); -+} -+ -+void putc(const char c) -+{ -+ /* Send directly to the handler */ -+ serial_putc(c); -+} -+ -+void puts(const char *s) -+{ -+ serial_puts(s); -+} -+ -+void printf(const char *fmt, ...) -+{ -+ va_list args; -+ char printbuffer[CONFIG_SYS_PBSIZE]; -+ -+ va_start(args, fmt); -+ -+ /* For this to work, printbuffer must be larger than -+ * anything we ever want to print. -+ */ -+ vsprintf(printbuffer, fmt, args); -+ va_end(args); -+ -+ /* Print the string */ -+ puts(printbuffer); -+} -+ -+void vprintf(const char *fmt, va_list args) -+{ -+ char printbuffer[CONFIG_SYS_PBSIZE]; -+ -+ /* For this to work, printbuffer must be larger than -+ * anything we ever want to print. -+ */ -+ vsprintf(printbuffer, fmt, args); -+ -+ /* Print the string */ -+ puts(printbuffer); -+} ---- a/config.mk -+++ b/config.mk -@@ -136,7 +136,7 @@ - ARFLAGS = crv - endif - RELFLAGS= $(PLATFORM_RELFLAGS) --DBGFLAGS= -g # -DDEBUG -+DBGFLAGS= -g - OPTFLAGS= -Os #-fomit-frame-pointer - ifndef LDSCRIPT - #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug -@@ -146,6 +146,11 @@ - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds - endif - endif -+ifeq ($(CONFIG_BOOTSTRAP),y) -+ifndef BOOTSTRAP_LDSCRIPT -+BOOTSTRAP_LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-bootstrap.lds -+endif -+endif - OBJCFLAGS += --gap-fill=0xff - - gccincdir := $(shell $(CC) -print-file-name=include) -@@ -156,6 +161,10 @@ - CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) - endif - -+ifneq ($(CONFIG_BOOTSTRAP_TEXT_BASE),) -+CPPFLAGS += -DCONFIG_BOOTSTRAP_TEXT_BASE=$(CONFIG_BOOTSTRAP_TEXT_BASE) -+endif -+ - ifneq ($(RESET_VECTOR_ADDRESS),) - CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) - endif -@@ -176,6 +185,7 @@ - endif - - CFLAGS += $(call cc-option,-fno-stack-protector) -+CFLAGS += $(call cc-option,-ffunction-sections) - - # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) - # this option have to be placed behind -Wall -- that's why it is here -@@ -203,6 +213,13 @@ - LDFLAGS += -Ttext $(TEXT_BASE) - endif - -+ifeq ($(CONFIG_BOOTSTRAP),y) -+BOOTSTRAP_LDFLAGS += -Bstatic -T $(obj)u-boot-bootstrap.lds $(PLATFORM_LDFLAGS) -+ifneq ($(CONFIG_BOOTSTRAP_TEXT_BASE),) -+BOOTSTRAP_LDFLAGS += -Ttext $(CONFIG_BOOTSTRAP_TEXT_BASE) -+endif -+endif -+ - # Location of a usable BFD library, where we define "usable" as - # "built for ${HOST}, supports ${TARGET}". Sensible values are - # - When cross-compiling: the root of the cross-environment ---- a/include/common.h -+++ b/include/common.h -@@ -722,6 +722,27 @@ - int cpu_release(int nr, int argc, char *argv[]); - #endif - -+/* Bootstrap specific code */ -+#ifdef CONFIG_BOOTSTRAP -+void bootstrap_hang(void) __attribute__ ((noreturn)); -+void bootstrap_board_init_f(ulong) __attribute__ ((noreturn)); -+void bootstrap_board_init_r(gd_t *, ulong) __attribute__ ((noreturn)); -+int bootstrap_checkboard(void); -+ -+int bootstrap_serial_init(void); -+void bootstrap_serial_exit(void); -+void bootstrap_serial_setbrg(void); -+void bootstrap_serial_putc(const char); -+void bootstrap_serial_putc_raw(const char); -+void bootstrap_serial_puts(const char *); -+int bootstrap_serial_getc(void); -+int bootstrap_serial_tstc(void); -+ -+phys_size_t bootstrap_initdram (int); -+ -+int copy_uboot(void *dst, size_t unc_size, void *src, size_t size); -+#endif -+ - #endif /* __ASSEMBLY__ */ - - /* Put only stuff here that the assembler can digest */ ---- a/lib_generic/Makefile -+++ b/lib_generic/Makefile -@@ -24,6 +24,9 @@ - include $(TOPDIR)/config.mk - - LIB = $(obj)libgeneric.a -+BOOTSTRAP_LIB = $(obj)libgeneric_bootstrap.a -+ -+BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - - COBJS-$(CONFIG_ADDR_MAP) += addr_map.o - COBJS-$(CONFIG_BZIP2) += bzlib.o -@@ -50,14 +53,37 @@ - COBJS-y += vsprintf.o - COBJS-$(CONFIG_ZLIB) += zlib.o - COBJS-$(CONFIG_RBTREE) += rbtree.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += string.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += vsprintf.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += div64.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += ctype.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += time.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += bootstrap.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_GZIP) += zlib.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_GZIP) += gunzip.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_GZIP) += crc32.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_crctable.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_decompress.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_randtable.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_BZIP2) += bzlib_huffman.o -+ -+BOOTSTRAP_COBJS := $(BOOTSTRAP_COBJS-y) -+BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS)) - - COBJS := $(COBJS-y) --SRCS := $(COBJS:.o=.c) -+SRCS := $(COBJS:.o=.c) $(BOOTSTRAP_COBJS:.o=.c) - OBJS := $(addprefix $(obj),$(COBJS)) - -+all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB-y) -+ - $(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -+$(BOOTSTRAP_LIB): $(obj).depend $(BOOTSTRAP_OBJS) -+ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) -+ -+ - ######################################################################### - - # defines $(obj).depend target ---- /dev/null -+++ b/lib_generic/bootstrap.c -@@ -0,0 +1,95 @@ -+/* -+ * (C) Copyright 2010 Industrie Dial Face S.p.A. -+ * Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com -+ * -+ * (C) Copyright 2003 -+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include <common.h> -+#include <command.h> -+#include <stdio_dev.h> -+ -+#ifdef CONFIG_BOOTSTRAP_LZMA -+#include <lzma/LzmaTypes.h> -+#include <lzma/LzmaDec.h> -+#include <lzma/LzmaTools.h> -+#endif /* CONFIG_BOOTSTRAP_LZMA */ -+ -+#ifdef CONFIG_BOOTSTRAP_LZO -+#include <linux/lzo.h> -+#endif /* CONFIG_BOOTSTRAP_LZO */ -+ -+#ifdef CONFIG_BOOTSTRAP_BZIP2 -+#include <bzlib.h> -+#endif -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#if defined(CONFIG_BOOTSTRAP_SERIAL) -+static const char *algo = -+#if defined(CONFIG_BOOTSTRAP_GZIP) -+ "gzip"; -+#elif defined(CONFIG_BOOTSTRAP_LZMA) -+ "lzma"; -+#elif defined(CONFIG_BOOTSTRAP_LZO) -+ "lzo"; -+#elif defined(CONFIG_BOOTSTRAP_BZIP2) -+ "bzip2"; -+#else -+ "flat"; -+#endif -+#endif -+ -+int copy_uboot(void *dst, size_t unc_size, void *src, size_t size) -+{ -+ int ret; -+ debug("copy from %p (%d) to %p (%d)\n", src, size, dst, unc_size); -+#if defined(CONFIG_BOOTSTRAP_SERIAL) -+ printf("Uncompressing payload (%s)...", algo); -+#endif -+#if defined(CONFIG_BOOTSTRAP_GZIP) -+ ret = gunzip(dst, unc_size, src, &size); -+#elif defined(CONFIG_BOOTSTRAP_LZMA) -+ SizeT outsize = unc_size; -+ ret = lzmaBuffToBuffDecompress(dst, &outsize, src, size); -+#elif defined(CONFIG_BOOTSTRAP_LZO) -+ uint unc_len = unc_size; -+ ret = lzop_decompress(src, size, dst, &unc_len); -+#elif defined(CONFIG_BOOTSTRAP_BZIP2) -+ uint unc_len = unc_size; -+ ret = BZ2_bzBuffToBuffDecompress ((char*)dst, &unc_len, (char *)src, size, CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); -+#else -+ memcpy(dst, src, size); -+ ret = 0; -+#endif -+ if (ret) { -+#if defined(CONFIG_BOOTSTRAP_SERIAL) -+ printf("failed with error %d.\n", ret); -+#endif -+ bootstrap_hang(); -+ } else { -+#if defined(CONFIG_BOOTSTRAP_SERIAL) -+ puts("done.\n"); -+#endif -+ } -+ return ret; -+} ---- a/lib_generic/lzma/Makefile -+++ b/lib_generic/lzma/Makefile -@@ -32,7 +32,9 @@ - - CFLAGS += -D_LZMA_PROB32 - --COBJS-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o -+COBJS-$(CONFIG_LZMA)$(CONFIG_BOOTSTRAP_LZMA) += LzmaDec.o LzmaTools.o -+ -+COBJS-y += $(COBJS-yy) - - COBJS = $(COBJS-y) - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ---- a/lib_generic/lzo/Makefile -+++ b/lib_generic/lzo/Makefile -@@ -27,7 +27,9 @@ - - SOBJS = - --COBJS-$(CONFIG_LZO) += lzo1x_decompress.o -+COBJS-$(CONFIG_LZO)$(CONFIG_BOOTSTRAP_LZO) += lzo1x_decompress.o -+ -+COBJS-y += $(OBJS-yy) - - COBJS = $(COBJS-y) - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ---- a/cpu/mips/Makefile -+++ b/cpu/mips/Makefile -@@ -24,25 +24,46 @@ - include $(TOPDIR)/config.mk - - LIB = $(obj)lib$(CPU).a -+BOOTSTRAP_LIB = $(obj)lib$(CPU)_bootstrap.a -+ -+BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB) - - START = start.o - SOBJS-y = cache.o --COBJS-y = cpu.o interrupts.o -+COBJS-y = cpu.o reset.o interrupts.o - - SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o - COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o -+#COBJS-$(CONFIG_IFX_ASC) += ifx_asc.o - COBJS-$(CONFIG_PURPLE) += asc_serial.o - COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o - --SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -+#BOOTSTRAP_START = start_bootstrap.o -+BOOTSTRAP_START-$(CONFIG_BOOTSTRAP) += start_bootstrap.o #$(BOOTSTRAP_START) -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) += cpu.o interrupts.o reset_bootstrap.o -+BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) += cache.o -+BOOTSTRAP_COBJS-$(CONFIG_DANUBE) += danube-clock.o -+BOOTSTRAP_COBJS-$(CONFIG_AR9) += ar9-clock.o -+BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP_SERIAL) += ifx_asc.o -+ -+BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y) $(BOOTSTRAP_COBJS-y)) -+BOOTSTRAP_START := $(addprefix $(obj),$(BOOTSTRAP_START-y)) -+ -+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) $(BOOTSTRAP_START-y:.o=.S) $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c) - OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) - START := $(addprefix $(obj),$(START)) - --all: $(obj).depend $(START) $(LIB) -+all: $(obj).depend $(START) $(LIB) $(BOOTSTRAP_START-y) $(BOOTSTRAP_LIB-y) - --$(LIB): $(OBJS) -+$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -+#$(BOOTSTRAP_START): $(obj).depend -+ -+$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) -+ $(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) -+ -+ - ######################################################################### - - # defines $(obj).depend target diff --git a/package/uboot-lantiq/patches/500-gigasx.patch b/package/uboot-lantiq/patches/500-gigasx.patch deleted file mode 100644 index fe384ef788..0000000000 --- a/package/uboot-lantiq/patches/500-gigasx.patch +++ /dev/null @@ -1,35 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -3613,6 +3613,32 @@ - $(eval $(call arcadyan, arv752DPW%config)) - $(eval $(call arcadyan, arv752DPW22%config)) - -+gigaSX76X%config : unconfig -+ @mkdir -p $(obj)include -+ @mkdir -p $(obj)board/infineon/easy50712 -+ @[ -z "$(findstring ramboot,$@)" ] || \ -+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/infineon/easy50712/config.tmp ; \ -+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \ -+ $(XECHO) "... with ramboot configuration" ; \ -+ } -+ @if [ "$(findstring _DDR,$@)" -a -z "$(findstring ramboot,$@)" ] ; then \ -+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \ -+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \ -+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \ -+ case "$${DDR}" in \ -+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \ -+ $(XECHO) "... with DDR RAM config $${DDR}" ; \ -+ echo "#define CONFIG_USE_DDR_RAM_CFG_$${DDR}" >>$(obj)include/config.h ;; \ -+ *) $(XECHO) "... DDR RAM config \\\"$${DDR}\\\" unknown, use default"; \ -+ esac; \ -+ fi -+ echo "#define CONFIG_SWITCH_PORT1 1" >>$(obj)include/config.h -+ echo "#define CONFIG_SWITCH_PIN 3" >>$(obj)include/config.h -+ echo "#define CONFIG_BUTTON_PORT0 1" >>$(obj)include/config.h -+ echo "#define CONFIG_BUTTON_PIN 14" >>$(obj)include/config.h -+ echo "#define CONFIG_BUTTON_LEVEL 1" >>$(obj)include/config.h -+ @$(MKCONFIG) -a easy50712 mips mips easy50712 infineon danube -+ - easy50712%config : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/infineon/easy50712 |