diff options
Diffstat (limited to 'package/rt2x00/src/rt2400pci.c')
| -rw-r--r-- | package/rt2x00/src/rt2400pci.c | 913 |
1 files changed, 441 insertions, 472 deletions
diff --git a/package/rt2x00/src/rt2400pci.c b/package/rt2x00/src/rt2400pci.c index 824c8233e8..31c1dd2716 100644 --- a/package/rt2x00/src/rt2400pci.c +++ b/package/rt2x00/src/rt2400pci.c @@ -29,20 +29,15 @@ */ #define DRV_NAME "rt2400pci" +#include <linux/delay.h> +#include <linux/etherdevice.h> +#include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> -#include <linux/init.h> #include <linux/pci.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/etherdevice.h> #include <linux/eeprom_93cx6.h> -#include <asm/io.h> - #include "rt2x00.h" -#include "rt2x00lib.h" #include "rt2x00pci.h" #include "rt2400pci.h" @@ -75,12 +70,12 @@ static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev) } static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev, - const u8 reg_id, const u8 value) + const unsigned int word, const u8 value) { u32 reg; /* - * Wait until the BBP becomes ready. + * Wait until the BBP becomes ready. */ reg = rt2400pci_bbp_check(rt2x00dev); if (rt2x00_get_field32(reg, BBPCSR_BUSY)) { @@ -93,7 +88,7 @@ static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev, */ reg = 0; rt2x00_set_field32(®, BBPCSR_VALUE, value); - rt2x00_set_field32(®, BBPCSR_REGNUM, reg_id); + rt2x00_set_field32(®, BBPCSR_REGNUM, word); rt2x00_set_field32(®, BBPCSR_BUSY, 1); rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); @@ -101,12 +96,12 @@ static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev, } static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev, - const u8 reg_id, u8 *value) + const unsigned int word, u8 *value) { u32 reg; /* - * Wait until the BBP becomes ready. + * Wait until the BBP becomes ready. */ reg = rt2400pci_bbp_check(rt2x00dev); if (rt2x00_get_field32(reg, BBPCSR_BUSY)) { @@ -118,14 +113,14 @@ static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev, * Write the request into the BBP. */ reg = 0; - rt2x00_set_field32(®, BBPCSR_REGNUM, reg_id); + rt2x00_set_field32(®, BBPCSR_REGNUM, word); rt2x00_set_field32(®, BBPCSR_BUSY, 1); rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); /* - * Wait until the BBP becomes ready. + * Wait until the BBP becomes ready. */ reg = rt2400pci_bbp_check(rt2x00dev); if (rt2x00_get_field32(reg, BBPCSR_BUSY)) { @@ -138,11 +133,14 @@ static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev, } static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev, - const u32 value) + const unsigned int word, const u32 value) { u32 reg; unsigned int i; + if (!word) + return; + for (i = 0; i < REGISTER_BUSY_COUNT; i++) { rt2x00pci_register_read(rt2x00dev, RFCSR, ®); if (!rt2x00_get_field32(reg, RFCSR_BUSY)) @@ -161,6 +159,7 @@ rf_write: rt2x00_set_field32(®, RFCSR_BUSY, 1); rt2x00pci_register_write(rt2x00dev, RFCSR, reg); + rt2x00_rf_write(rt2x00dev, word, value); } static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom) @@ -170,14 +169,12 @@ static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom) rt2x00pci_register_read(rt2x00dev, CSR21, ®); - eeprom->reg_data_in = !!rt2x00_get_field32(reg, - CSR21_EEPROM_DATA_IN); - eeprom->reg_data_out = !!rt2x00_get_field32(reg, - CSR21_EEPROM_DATA_OUT); - eeprom->reg_data_clock = !!rt2x00_get_field32(reg, - CSR21_EEPROM_DATA_CLOCK); - eeprom->reg_chip_select = !!rt2x00_get_field32(reg, - CSR21_EEPROM_CHIP_SELECT); + eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); + eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); + eeprom->reg_data_clock = + !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); + eeprom->reg_chip_select = + !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); } static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom) @@ -185,14 +182,12 @@ static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom) struct rt2x00_dev *rt2x00dev = eeprom->data; u32 reg = 0; - rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, - !!eeprom->reg_data_in); - rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, - !!eeprom->reg_data_out); + rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); + rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, - !!eeprom->reg_data_clock); + !!eeprom->reg_data_clock); rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, - !!eeprom->reg_chip_select); + !!eeprom->reg_chip_select); rt2x00pci_register_write(rt2x00dev, CSR21, reg); } @@ -200,62 +195,44 @@ static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom) #ifdef CONFIG_RT2X00_LIB_DEBUGFS #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) ) -static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev, - const unsigned long word, void *data) +static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev, + const unsigned int word, u32 *data) { rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data); } -static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev, - const unsigned long word, void *data) -{ - rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data)); -} - -static void rt2400pci_read_eeprom(struct rt2x00_dev *rt2x00dev, - const unsigned long word, void *data) -{ - rt2x00_eeprom_read(rt2x00dev, word, data); -} - -static void rt2400pci_write_eeprom(struct rt2x00_dev *rt2x00dev, - const unsigned long word, void *data) +static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev, + const unsigned int word, u32 data) { - rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data)); -} - -static void rt2400pci_read_bbp(struct rt2x00_dev *rt2x00dev, - const unsigned long word, void *data) -{ - rt2400pci_bbp_read(rt2x00dev, word, data); -} - -static void rt2400pci_write_bbp(struct rt2x00_dev *rt2x00dev, - const unsigned long word, void *data) -{ - rt2400pci_bbp_write(rt2x00dev, word, *((u8*)data)); + rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data); } static const struct rt2x00debug rt2400pci_rt2x00debug = { - .owner = THIS_MODULE, - .reg_csr = { + .owner = THIS_MODULE, + .csr = { .read = rt2400pci_read_csr, .write = rt2400pci_write_csr, .word_size = sizeof(u32), .word_count = CSR_REG_SIZE / sizeof(u32), }, - .reg_eeprom = { - .read = rt2400pci_read_eeprom, - .write = rt2400pci_write_eeprom, + .eeprom = { + .read = rt2x00_eeprom_read, + .write = rt2x00_eeprom_write, .word_size = sizeof(u16), .word_count = EEPROM_SIZE / sizeof(u16), }, - .reg_bbp = { - .read = rt2400pci_read_bbp, - .write = rt2400pci_write_bbp, + .bbp = { + .read = rt2400pci_bbp_read, + .write = rt2400pci_bbp_write, .word_size = sizeof(u8), .word_count = BBP_SIZE / sizeof(u8), }, + .rf = { + .read = rt2x00_rf_read, + .write = rt2400pci_rf_write, + .word_size = sizeof(u32), + .word_count = RF_SIZE / sizeof(u32), + }, }; #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ @@ -267,110 +244,114 @@ static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®); return rt2x00_get_field32(reg, GPIOCSR_BIT0); } +#else +#define rt2400pci_rfkill_poll NULL #endif /* CONFIG_RT2400PCI_RFKILL */ /* * Configuration handlers. */ -static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid) +static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, + __le32 *mac) { - u32 reg[2]; - - memset(®, 0, sizeof(reg)); - memcpy(®, bssid, ETH_ALEN); - - /* - * The BSSID is passed to us as an array of bytes, - * that array is little endian, so no need for byte ordering. - */ - rt2x00pci_register_multiwrite(rt2x00dev, CSR5, ®, sizeof(reg)); + rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac, + (2 * sizeof(__le32))); } -static void rt2400pci_config_promisc(struct rt2x00_dev *rt2x00dev, - const int promisc) +static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, + __le32 *bssid) { - u32 reg; - - rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); - rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, !promisc); - rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); + rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid, + (2 * sizeof(__le32))); } -static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type) +static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type, + const int tsf_sync) { u32 reg; rt2x00pci_register_write(rt2x00dev, CSR14, 0); /* - * Apply hardware packet filter. - */ - rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); - - if (!is_monitor_present(&rt2x00dev->interface) && - (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA)) - rt2x00_set_field32(®, RXCSR0_DROP_TODS, 1); - else - rt2x00_set_field32(®, RXCSR0_DROP_TODS, 0); - - rt2x00_set_field32(®, RXCSR0_DROP_CRC, 1); - if (is_monitor_present(&rt2x00dev->interface)) { - rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, 0); - rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, 0); - rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 0); - } else { - rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, 1); - rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, 1); - rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); - } - - rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); - - /* * Enable beacon config */ rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); rt2x00_set_field32(®, BCNCSR1_PRELOAD, - PREAMBLE + get_duration(IEEE80211_HEADER, 2)); + PREAMBLE + get_duration(IEEE80211_HEADER, 20)); rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); /* * Enable synchronisation. */ rt2x00pci_register_read(rt2x00dev, CSR14, ®); - if (is_interface_present(&rt2x00dev->interface)) { - rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); - rt2x00_set_field32(®, CSR14_TBCN, 1); - } - + rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); + rt2x00_set_field32(®, CSR14_TBCN, 1); rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); - if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP) - rt2x00_set_field32(®, CSR14_TSF_SYNC, 2); - else if (type == IEEE80211_IF_TYPE_STA) - rt2x00_set_field32(®, CSR14_TSF_SYNC, 1); - else if (is_monitor_present(&rt2x00dev->interface) && - !is_interface_present(&rt2x00dev->interface)) - rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); - + rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync); rt2x00pci_register_write(rt2x00dev, CSR14, reg); } -static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, - const int value, const int channel, const int txpower) +static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev, + const int short_preamble, + const int ack_timeout, + const int ack_consume_time) +{ + int preamble_mask; + u32 reg; + + /* + * When short preamble is enabled, we should set bit 0x08 + */ + preamble_mask = short_preamble << 3; + + rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); + rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout); + rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time); + rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); + + rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); + rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask); + rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); + rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10)); + rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); + + rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); + rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); + rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); + rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20)); + rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); + + rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); + rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); + rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); + rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55)); + rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); + + rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); + rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); + rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); + rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110)); + rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); +} + +static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev, + const int basic_rate_mask) { - u32 rf1 = rt2x00dev->rf1; - u32 rf2 = value; - u32 rf3 = rt2x00dev->rf3; + rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask); +} +static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, + struct rf_channel *rf) +{ /* * Switch on tuning bits. */ - rt2x00_set_field32(&rf1, RF1_TUNER, 1); - rt2x00_set_field32(&rf3, RF3_TUNER, 1); + rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); + rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); - rt2400pci_rf_write(rt2x00dev, rf1); - rt2400pci_rf_write(rt2x00dev, rf2); - rt2400pci_rf_write(rt2x00dev, rf3); + rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); + rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); + rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); /* * RF2420 chipset don't need any additional actions. @@ -383,38 +364,31 @@ static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, * reference clock rate to activate auto_tune. * After that we set the value back to the correct channel. */ - rt2400pci_rf_write(rt2x00dev, rf1); - rt2400pci_rf_write(rt2x00dev, 0x000c2a32); - rt2400pci_rf_write(rt2x00dev, rf3); + rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); + rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32); + rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); msleep(1); - rt2400pci_rf_write(rt2x00dev, rf1); - rt2400pci_rf_write(rt2x00dev, rf2); - rt2400pci_rf_write(rt2x00dev, rf3); + rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); + rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); + rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); msleep(1); /* * Switch off tuning bits. */ - rt2x00_set_field32(&rf1, RF1_TUNER, 0); - rt2x00_set_field32(&rf3, RF3_TUNER, 0); - - rt2400pci_rf_write(rt2x00dev, rf1); - rt2400pci_rf_write(rt2x00dev, rf3); + rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); + rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); - /* - * Update rf fields - */ - rt2x00dev->rf1 = rf1; - rt2x00dev->rf2 = rf2; - rt2x00dev->rf3 = rf3; + rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); + rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); /* * Clear false CRC during channel switch. */ - rt2x00pci_register_read(rt2x00dev, CNT0, &rf1); + rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1); } static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) @@ -423,7 +397,7 @@ static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) } static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev, - int antenna_tx, int antenna_rx) + int antenna_tx, int antenna_rx) { u8 r1; u8 r4; @@ -434,58 +408,56 @@ static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev, /* * Configure the TX antenna. */ - if (antenna_tx == ANTENNA_DIVERSITY) + switch (antenna_tx) { + case ANTENNA_SW_DIVERSITY: + case ANTENNA_HW_DIVERSITY: rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1); - else if (antenna_tx == ANTENNA_A) + break; + case ANTENNA_A: rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0); - else if (antenna_tx == ANTENNA_B) + break; + case ANTENNA_B: rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2); + break; + } /* * Configure the RX antenna. */ - if (antenna_rx == ANTENNA_DIVERSITY) + switch (antenna_rx) { + case ANTENNA_SW_DIVERSITY: + case ANTENNA_HW_DIVERSITY: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); - else if (antenna_rx == ANTENNA_A) + break; + case ANTENNA_A: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0); - else if (antenna_rx == ANTENNA_B) + break; + case ANTENNA_B: rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2); + break; + } rt2400pci_bbp_write(rt2x00dev, 4, r4); rt2400pci_bbp_write(rt2x00dev, 1, r1); } -static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, - struct ieee80211_tx_queue_params *params) -{ - u32 reg; - - rt2x00pci_register_read(rt2x00dev, CSR11, ®); - rt2x00_set_field32(®, CSR11_CWMIN, params->cw_min); - rt2x00_set_field32(®, CSR11_CWMAX, params->cw_max); - rt2x00pci_register_write(rt2x00dev, CSR11, reg); -} - static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev, - int short_slot_time, int beacon_int) + struct rt2x00lib_conf *libconf) { u32 reg; rt2x00pci_register_read(rt2x00dev, CSR11, ®); - rt2x00_set_field32(®, CSR11_SLOT_TIME, - short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME); + rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time); rt2x00pci_register_write(rt2x00dev, CSR11, reg); rt2x00pci_register_read(rt2x00dev, CSR18, ®); - rt2x00_set_field32(®, CSR18_SIFS, SIFS); - rt2x00_set_field32(®, CSR18_PIFS, - short_slot_time ? SHORT_PIFS : PIFS); + rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs); + rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs); rt2x00pci_register_write(rt2x00dev, CSR18, reg); rt2x00pci_register_read(rt2x00dev, CSR19, ®); - rt2x00_set_field32(®, CSR19_DIFS, - short_slot_time ? SHORT_DIFS : DIFS); - rt2x00_set_field32(®, CSR19_EIFS, EIFS); + rt2x00_set_field32(®, CSR19_DIFS, libconf->difs); + rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs); rt2x00pci_register_write(rt2x00dev, CSR19, reg); rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); @@ -494,86 +466,41 @@ static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev, rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); rt2x00pci_register_read(rt2x00dev, CSR12, ®); - rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, beacon_int * 16); - rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, beacon_int * 16); + rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, + libconf->conf->beacon_int * 16); + rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, + libconf->conf->beacon_int * 16); rt2x00pci_register_write(rt2x00dev, CSR12, reg); } -static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate) +static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, + const unsigned int flags, + struct rt2x00lib_conf *libconf) { - struct ieee80211_conf *conf = &rt2x00dev->hw->conf; - u32 reg; - u32 preamble; - u16 value; - - preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) - ? SHORT_PREAMBLE : PREAMBLE; - - reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE; - rt2x00pci_register_write(rt2x00dev, ARCSR1, reg); - - rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); - value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ? - SHORT_DIFS : DIFS) + - PLCP + preamble + get_duration(ACK_SIZE, 10); - rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, value); - value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10); - rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, value); - rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); - - preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00; - - rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); - rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble); - rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); - rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10)); - rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); - - rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); - rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble); - rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); - rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20)); - rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); - - rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); - rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble); - rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); - rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55)); - rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); - - rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); - rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble); - rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); - rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110)); - rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); + if (flags & CONFIG_UPDATE_PHYMODE) + rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates); + if (flags & CONFIG_UPDATE_CHANNEL) + rt2400pci_config_channel(rt2x00dev, &libconf->rf); + if (flags & CONFIG_UPDATE_TXPOWER) + rt2400pci_config_txpower(rt2x00dev, + libconf->conf->power_level); + if (flags & CONFIG_UPDATE_ANTENNA) + rt2400pci_config_antenna(rt2x00dev, + libconf->conf->antenna_sel_tx, + libconf->conf->antenna_sel_rx); + if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT)) + rt2400pci_config_duration(rt2x00dev, libconf); } -static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev, - const int phymode) -{ - struct ieee80211_hw_mode *mode; - struct ieee80211_rate *rate; - - rt2x00dev->curr_hwmode = HWMODE_B; - - mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode]; - rate = &mode->rates[mode->num_rates - 1]; - - rt2400pci_config_rate(rt2x00dev, rate->val2); -} - -static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr) +static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, + struct ieee80211_tx_queue_params *params) { - u32 reg[2]; - - memset(®, 0, sizeof(reg)); - memcpy(®, addr, ETH_ALEN); + u32 reg; - /* - * The MAC address is passed to us as an array of bytes, - * that array is little endian, so no need for byte ordering. - */ - rt2x00pci_register_multiwrite(rt2x00dev, CSR3, ®, sizeof(reg)); + rt2x00pci_register_read(rt2x00dev, CSR11, ®); + rt2x00_set_field32(®, CSR11_CWMIN, params->cw_min); + rt2x00_set_field32(®, CSR11_CWMAX, params->cw_max); + rt2x00pci_register_write(rt2x00dev, CSR11, reg); } /* @@ -615,10 +542,33 @@ static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev) /* * Link tuning */ +static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev) +{ + u32 reg; + u8 bbp; + + /* + * Update FCS error count from register. + */ + rt2x00pci_register_read(rt2x00dev, CNT0, ®); + rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); + + /* + * Update False CCA count from register. + */ + rt2400pci_bbp_read(rt2x00dev, 39, &bbp); + rt2x00dev->link.false_cca = bbp; +} + +static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev) +{ + rt2400pci_bbp_write(rt2x00dev, 13, 0x08); + rt2x00dev->link.vgc_level = 0x08; +} + static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev) { u8 reg; - char false_cca_delta; /* * The link tuner should not run longer then 60 seconds, @@ -628,29 +578,16 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev) return; /* - * Read false CCA counter. + * Base r13 link tuning on the false cca count. */ - rt2400pci_bbp_read(rt2x00dev, 39, ®); + rt2400pci_bbp_read(rt2x00dev, 13, ®); - /* - * Determine difference with previous CCA counter. - */ - false_cca_delta = reg - rt2x00dev->link.false_cca; - rt2x00dev->link.false_cca = reg; - - /* - * Check if the difference is higher than the - * threshold and if so, tune the link. - */ - if (false_cca_delta >= 8) { - /* - * Read and update RX AGC VGC. - */ - rt2400pci_bbp_read(rt2x00dev, 13, ®); - reg += 2; - if (reg < 0x20) - rt2400pci_bbp_write(rt2x00dev, 13, reg); - rt2x00dev->rx_status.noise = reg; + if (rt2x00dev->link.false_cca > 512 && reg < 0x20) { + rt2400pci_bbp_write(rt2x00dev, 13, ++reg); + rt2x00dev->link.vgc_level = reg; + } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) { + rt2400pci_bbp_write(rt2x00dev, 13, --reg); + rt2x00dev->link.vgc_level = reg; } } @@ -659,24 +596,24 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev) */ static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev) { + struct data_ring *ring = rt2x00dev->rx; struct data_desc *rxd; unsigned int i; u32 word; - memset(rt2x00dev->rx->data_addr, 0x00, - rt2x00_get_ring_size(rt2x00dev->rx)); + memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring)); - for (i = 0; i < rt2x00dev->rx->stats.limit; i++) { - rxd = rt2x00dev->rx->entry[i].priv; + for (i = 0; i < ring->stats.limit; i++) { + rxd = ring->entry[i].priv; rt2x00_desc_read(rxd, 2, &word); rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, - rt2x00dev->rx->data_size); + ring->data_size); rt2x00_desc_write(rxd, 2, word); rt2x00_desc_read(rxd, 1, &word); rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, - rt2x00dev->rx->entry[i].data_dma); + ring->entry[i].data_dma); rt2x00_desc_write(rxd, 1, word); rt2x00_desc_read(rxd, 0, &word); @@ -687,10 +624,9 @@ static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev) rt2x00_ring_index_clear(rt2x00dev->rx); } -static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, - const int queue) +static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue) { - struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue); + struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue); struct data_desc *txd; unsigned int i; u32 word; @@ -702,12 +638,12 @@ static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, rt2x00_desc_read(txd, 1, &word); rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, - ring->entry[i].data_dma); + ring->entry[i].data_dma); rt2x00_desc_write(txd, 1, word); rt2x00_desc_read(txd, 2, &word); rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, - ring->data_size); + ring->data_size); rt2x00_desc_write(txd, 2, word); rt2x00_desc_read(txd, 0, &word); @@ -737,45 +673,43 @@ static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev) */ rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); rt2x00_set_field32(®, TXCSR2_TXD_SIZE, - rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size); + rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size); rt2x00_set_field32(®, TXCSR2_NUM_TXD, - rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); + rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); rt2x00_set_field32(®, TXCSR2_NUM_ATIM, - rt2x00dev->bcn[1].stats.limit); + rt2x00dev->bcn[1].stats.limit); rt2x00_set_field32(®, TXCSR2_NUM_PRIO, - rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit); + rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit); rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, - rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma); + rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, - rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma); + rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, - rt2x00dev->bcn[1].data_dma); + rt2x00dev->bcn[1].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, - rt2x00dev->bcn[0].data_dma); + rt2x00dev->bcn[0].data_dma); rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); - rt2x00_set_field32(®, RXCSR1_RXD_SIZE, - rt2x00dev->rx->desc_size); - rt2x00_set_field32(®, RXCSR1_NUM_RXD, - rt2x00dev->rx->stats.limit); + rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); + rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit); rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, - rt2x00dev->rx->data_dma); + rt2x00dev->rx->data_dma); rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); return 0; @@ -785,14 +719,9 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) { u32 reg; - if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) - return -EBUSY; - - rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); - rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002); rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002); - rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002); + rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20); rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002); rt2x00pci_register_read(rt2x00dev, TIMECSR, ®); @@ -803,36 +732,39 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00pci_register_read(rt2x00dev, CSR9, ®); rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, - (rt2x00dev->rx->data_size / 128)); + (rt2x00dev->rx->data_size / 128)); rt2x00pci_register_write(rt2x00dev, CSR9, reg); rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000); - rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223); - rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); - - rt2x00pci_register_read(rt2x00dev, MACCSR2, ®); - rt2x00_set_field32(®, MACCSR2_DELAY, 64); - rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); + rt2x00pci_register_read(rt2x00dev, ARCSR0, ®); + rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); + rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); + rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); + rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); + rt2x00pci_register_write(rt2x00dev, ARCSR0, reg); rt2x00pci_register_read(rt2x00dev, RXCSR3, ®); - /* - * Tx power. - */ - rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); + rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); - /* - * Signal. - */ - rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); + rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); - /* - * Rssi. - */ - rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); + rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); rt2x00pci_register_write(rt2x00dev, RXCSR3, reg); + rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); + + if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) + return -EBUSY; + + rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223); + rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); + + rt2x00pci_register_read(rt2x00dev, MACCSR2, ®); + rt2x00_set_field32(®, MACCSR2_DELAY, 64); + rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); + rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®); rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); @@ -885,7 +817,6 @@ continue_csr_init: rt2400pci_bbp_write(rt2x00dev, 3, 0x27); rt2400pci_bbp_write(rt2x00dev, 4, 0x08); rt2400pci_bbp_write(rt2x00dev, 10, 0x0f); - rt2400pci_bbp_write(rt2x00dev, 13, 0x08); rt2400pci_bbp_write(rt2x00dev, 15, 0x72); rt2400pci_bbp_write(rt2x00dev, 16, 0x74); rt2400pci_bbp_write(rt2x00dev, 17, 0x20); @@ -905,7 +836,7 @@ continue_csr_init: reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n", - reg_id, value); + reg_id, value); rt2400pci_bbp_write(rt2x00dev, reg_id, value); } } @@ -918,25 +849,27 @@ continue_csr_init: * Device state switch handlers. */ static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev, - enum dev_state state) + enum dev_state state) { u32 reg; rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); rt2x00_set_field32(®, RXCSR0_DISABLE_RX, - state == STATE_RADIO_RX_OFF); + state == STATE_RADIO_RX_OFF); rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); } -static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, int enabled) +static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, + enum dev_state state) { + int mask = (state == STATE_RADIO_IRQ_OFF); u32 reg; /* * When interrupts are being enabled, the interrupt registers * should clear the register to assure a clean state. */ - if (enabled) { + if (state == STATE_RADIO_IRQ_ON) { rt2x00pci_register_read(rt2x00dev, CSR7, ®); rt2x00pci_register_write(rt2x00dev, CSR7, reg); } @@ -946,11 +879,11 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, int enabled) * Non-checked interrupt bits are disabled by default. */ rt2x00pci_register_read(rt2x00dev, CSR8, ®); - rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, !enabled); - rt2x00_set_field32(®, CSR8_TXDONE_TXRING, !enabled); - rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, !enabled); - rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, !enabled); - rt2x00_set_field32(®, CSR8_RXDONE, !enabled); + rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); + rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); + rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); + rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); + rt2x00_set_field32(®, CSR8_RXDONE, mask); rt2x00pci_register_write(rt2x00dev, CSR8, reg); } @@ -969,7 +902,7 @@ static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) /* * Enable interrupts. */ - rt2400pci_toggle_irq(rt2x00dev, 1); + rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON); /* * Enable LED @@ -1005,11 +938,11 @@ static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) /* * Disable interrupts. */ - rt2400pci_toggle_irq(rt2x00dev, 0); + rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF); } static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, - enum dev_state state) + enum dev_state state) { u32 reg; unsigned int i; @@ -1041,36 +974,36 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, } NOTICE(rt2x00dev, "Device failed to enter state %d, " - "current device state: bbp %d and rf %d.\n", - state, bbp_state, rf_state); + "current device state: bbp %d and rf %d.\n", + state, bbp_state, rf_state); return -EBUSY; } static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, - enum dev_state state) + enum dev_state state) { int retval = 0; switch (state) { - case STATE_RADIO_ON: - retval = rt2400pci_enable_radio(rt2x00dev); + case STATE_RADIO_ON: + retval = rt2400pci_enable_radio(rt2x00dev); break; - case STATE_RADIO_OFF: - rt2400pci_disable_radio(rt2x00dev); + case STATE_RADIO_OFF: + rt2400pci_disable_radio(rt2x00dev); break; - case STATE_RADIO_RX_ON: - case STATE_RADIO_RX_OFF: - rt2400pci_toggle_rx(rt2x00dev, state); + case STATE_RADIO_RX_ON: + case STATE_RADIO_RX_OFF: + rt2400pci_toggle_rx(rt2x00dev, state); break; - case STATE_DEEP_SLEEP: - case STATE_SLEEP: - case STATE_STANDBY: - case STATE_AWAKE: - retval = rt2400pci_set_state(rt2x00dev, state); + case STATE_DEEP_SLEEP: + case STATE_SLEEP: + case STATE_STANDBY: + case STATE_AWAKE: + retval = rt2400pci_set_state(rt2x00dev, state); break; - default: - retval = -ENOTSUPP; + default: + retval = -ENOTSUPP; break; } @@ -1081,9 +1014,11 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, * TX descriptor initialization */ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, - struct data_entry *entry, struct data_desc *txd, - struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr, - unsigned int length, struct ieee80211_tx_control *control) + struct data_desc *txd, + struct txdata_entry_desc *desc, + struct ieee80211_hdr *ieee80211hdr, + unsigned int length, + struct ieee80211_tx_control *control) { u32 word; u32 signal = 0; @@ -1132,22 +1067,25 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); rt2x00_set_field32(&word, TXD_W0_VALID, 1); rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, - test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags)); + test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags)); rt2x00_set_field32(&word, TXD_W0_ACK, - test_bit(ENTRY_TXD_REQ_ACK, &entry->flags)); + !(control->flags & IEEE80211_TXCTL_NO_ACK)); rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, - test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags)); + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags)); rt2x00_set_field32(&word, TXD_W0_RTS, - test_bit(ENTRY_TXD_RTS_FRAME, &entry->flags)); + test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags)); rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs); - rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0); + rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, + !!(control->flags & + IEEE80211_TXCTL_LONG_RETRY_LIMIT)); rt2x00_desc_write(txd, 0, word); } /* * TX data initialization */ -static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue) +static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, + unsigned int queue) { u32 reg; @@ -1173,8 +1111,8 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue) /* * RX control handlers */ -static int rt2400pci_fill_rxdone(struct data_entry *entry, - int *signal, int *rssi, int *ofdm) +static void rt2400pci_fill_rxdone(struct data_entry *entry, + struct rxdata_entry_desc *desc) { struct data_desc *rxd = entry->priv; u32 word0; @@ -1183,23 +1121,20 @@ static int rt2400pci_fill_rxdone(struct data_entry *entry, rt2x00_desc_read(rxd, 0, &word0); rt2x00_desc_read(rxd, 2, &word2); - /* - * TODO: Don't we need to keep statistics - * updated about these errors? - */ - if (rt2x00_get_field32(word0, RXD_W0_CRC) || - rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) - return -EINVAL; + desc->flags = 0; + if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) + desc->flags |= RX_FLAG_FAILED_FCS_CRC; + if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) + desc->flags |= RX_FLAG_FAILED_PLCP_CRC; /* * Obtain the status about this packet. */ - *signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); - *rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - - entry->ring->rt2x00dev->rssi_offset; - *ofdm = 0; - - return rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); + desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); + desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - + entry->ring->rt2x00dev->rssi_offset; + desc->ofdm = 0; + desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); } /* @@ -1207,7 +1142,7 @@ static int rt2400pci_fill_rxdone(struct data_entry *entry, */ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue) { - struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue); + struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue); struct data_entry *entry; struct data_desc *txd; u32 word; @@ -1248,7 +1183,7 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue) entry = ring->entry; if (!rt2x00_ring_full(ring)) ieee80211_wake_queue(rt2x00dev->hw, - entry->tx_status.control.queue); + entry->tx_status.control.queue); } static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) @@ -1279,7 +1214,7 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) * 1 - Beacon timer expired interrupt. */ if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) - rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON); + rt2x00lib_beacondone(rt2x00dev); /* * 2 - Rx ring done interrupt. @@ -1309,45 +1244,39 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) } /* - * Device initialization functions. + * Device probe functions. */ -static int rt2400pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev) +static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) { struct eeprom_93cx6 eeprom; u32 reg; u16 word; u8 *mac; - /* - * Allocate the eeprom memory, check the eeprom width - * and copy the entire eeprom into this allocated memory. - */ - rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL); - if (!rt2x00dev->eeprom) - return -ENOMEM; - rt2x00pci_register_read(rt2x00dev, CSR21, ®); eeprom.data = rt2x00dev; eeprom.register_read = rt2400pci_eepromregister_read; eeprom.register_write = rt2400pci_eepromregister_write; eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? - PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; eeprom.reg_data_in = 0; eeprom.reg_data_out = 0; eeprom.reg_data_clock = 0; eeprom.reg_chip_select = 0; eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, - EEPROM_SIZE / sizeof(u16)); + EEPROM_SIZE / sizeof(u16)); /* * Start validation of the data that has been read. */ mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); if (!is_valid_ether_addr(mac)) { + DECLARE_MAC_BUF(macbuf); + random_ether_addr(mac); - EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac)); + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac)); } rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); @@ -1386,22 +1315,24 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Identify default antenna configuration. */ - rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom, - EEPROM_ANTENNA_TX_DEFAULT); - rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom, - EEPROM_ANTENNA_RX_DEFAULT); + rt2x00dev->hw->conf.antenna_sel_tx = + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); + rt2x00dev->hw->conf.antenna_sel_rx = + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); /* * Store led mode, for correct led behaviour. */ - rt2x00dev->led_mode = rt2x00_get_field16(eeprom, - EEPROM_ANTENNA_LED_MODE); + rt2x00dev->led_mode = + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); /* * Detect if this device has an hardware controlled radio. */ +#ifdef CONFIG_RT2400PCI_RFKILL if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) - __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags); + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); +#endif /* CONFIG_RT2400PCI_RFKILL */ /* * Check if the BBP tuning should be enabled. @@ -1416,13 +1347,24 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) * RF value list for RF2420 & RF2421 * Supports: 2.4 GHz */ -static const u32 rf_vals_bg[] = { - 0x000c1fda, 0x000c1fee, 0x000c2002, 0x000c2016, 0x000c202a, - 0x000c203e, 0x000c2052, 0x000c2066, 0x000c207a, 0x000c208e, - 0x000c20a2, 0x000c20b6, 0x000c20ca, 0x000c20fa +static const struct rf_channel rf_vals_bg[] = { + { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 }, + { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 }, + { 3, 0x00022058, 0x000c2002, 0x00000101, 0 }, + { 4, 0x00022058, 0x000c2016, 0x00000101, 0 }, + { 5, 0x00022058, 0x000c202a, 0x00000101, 0 }, + { 6, 0x00022058, 0x000c203e, 0x00000101, 0 }, + { 7, 0x00022058, 0x000c2052, 0x00000101, 0 }, + { 8, 0x00022058, 0x000c2066, 0x00000101, 0 }, + { 9, 0x00022058, 0x000c207a, 0x00000101, 0 }, + { 10, 0x00022058, 0x000c208e, 0x00000101, 0 }, + { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 }, + { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 }, + { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 }, + { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 }, }; -static void rt2400pci_init_hw_mode(struct rt2x00_dev *rt2x00dev) +static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) { struct hw_mode_spec *spec = &rt2x00dev->spec; u8 *txpower; @@ -1431,30 +1373,16 @@ static void rt2400pci_init_hw_mode(struct rt2x00_dev *rt2x00dev) /* * Initialize all hw fields. */ - rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON | - IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | - IEEE80211_HW_WEP_INCLUDE_IV | - IEEE80211_HW_DATA_NULLFUNC_ACK | - IEEE80211_HW_NO_TKIP_WMM_HWACCEL | - IEEE80211_HW_MONITOR_DURING_OPER | - IEEE80211_HW_NO_PROBE_FILTERING; + rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; rt2x00dev->hw->extra_tx_headroom = 0; + rt2x00dev->hw->max_signal = MAX_SIGNAL; rt2x00dev->hw->max_rssi = MAX_RX_SSI; - rt2x00dev->hw->max_noise = MAX_RX_NOISE; rt2x00dev->hw->queues = 2; SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, - rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0)); - - /* - * Set device specific, but channel independent RF values. - */ - rt2x00dev->rf1 = 0x00022058; - if (rt2x00_rf(&rt2x00dev->chip, RF2420)) - rt2x00dev->rf3 = 0x00000111; - else - rt2x00dev->rf3 = 0x00000101; + rt2x00_eeprom_addr(rt2x00dev, + EEPROM_MAC_ADDR_0)); /* * Convert tx_power array in eeprom. @@ -1468,22 +1396,22 @@ static void rt2400pci_init_hw_mode(struct rt2x00_dev *rt2x00dev) */ spec->num_modes = 1; spec->num_rates = 4; - spec->num_channels = 14; spec->tx_power_a = NULL; spec->tx_power_bg = txpower; spec->tx_power_default = DEFAULT_TXPOWER; - spec->chan_val_a = NULL; - spec->chan_val_bg = rf_vals_bg; + + spec->num_channels = ARRAY_SIZE(rf_vals_bg); + spec->channels = rf_vals_bg; } -static int rt2400pci_init_hw(struct rt2x00_dev *rt2x00dev) +static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) { int retval; /* * Allocate eeprom data. */ - retval = rt2400pci_alloc_eeprom(rt2x00dev); + retval = rt2400pci_validate_eeprom(rt2x00dev); if (retval) return retval; @@ -1494,12 +1422,12 @@ static int rt2400pci_init_hw(struct rt2x00_dev *rt2x00dev) /* * Initialize hw specifications. */ - rt2400pci_init_hw_mode(rt2x00dev); + rt2400pci_probe_hw_mode(rt2x00dev); /* - * This device supports ATIM + * This device requires the beacon ring */ - __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags); + __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags); /* * Set the rssi offset. @@ -1512,28 +1440,70 @@ static int rt2400pci_init_hw(struct rt2x00_dev *rt2x00dev) /* * IEEE80211 stack callback functions. */ -static int rt2400pci_get_stats(struct ieee80211_hw *hw, - struct ieee80211_low_level_stats *stats) +static void rt2400pci_configure_filter(struct ieee80211_hw *hw, + unsigned int changed_flags, + unsigned int *total_flags, + int mc_count, + struct dev_addr_list *mc_list) { struct rt2x00_dev *rt2x00dev = hw->priv; + struct interface *intf = &rt2x00dev->interface; u32 reg; /* - * Update FCS error count from register. - * The dot11ACKFailureCount, dot11RTSFailureCount and - * dot11RTSSuccessCount are updated in interrupt time. + * Mask off any flags we are going to ignore from + * the total_flags field. */ - rt2x00pci_register_read(rt2x00dev, CNT0, ®); - rt2x00dev->low_level_stats.dot11FCSErrorCount += - rt2x00_get_field32(reg, CNT0_FCS_ERROR); + *total_flags &= + FIF_ALLMULTI | + FIF_FCSFAIL | + FIF_PLCPFAIL | + FIF_CONTROL | + FIF_OTHER_BSS | + FIF_PROMISC_IN_BSS; + + /* + * Apply some rules to the filters: + * - Some filters imply different filters to be set. + * - Some things we can't filter out at all. + * - Some filters are set based on interface type. + */ + *total_flags |= FIF_ALLMULTI; + if (*total_flags & FIF_OTHER_BSS || + *total_flags & FIF_PROMISC_IN_BSS) + *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS; + if (is_interface_type(intf, IEEE80211_IF_TYPE_AP)) + *total_flags |= FIF_PROMISC_IN_BSS; - memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats)); + /* + * Check if there is any work left for us. + */ + if (intf->filter == *total_flags) + return; + intf->filter = *total_flags; - return 0; + /* + * Start configuration steps. + * Note that the version error will always be dropped + * since there is no filter for it at this time. + */ + rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); + rt2x00_set_field32(®, RXCSR0_DROP_CRC, + !(*total_flags & FIF_FCSFAIL)); + rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, + !(*total_flags & FIF_PLCPFAIL)); + rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, + !(*total_flags & FIF_CONTROL)); + rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, + !(*total_flags & FIF_PROMISC_IN_BSS)); + rt2x00_set_field32(®, RXCSR0_DROP_TODS, + !(*total_flags & FIF_PROMISC_IN_BSS)); + rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); + rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); } static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw, - u32 short_retry, u32 long_retry) + u32 short_retry, u32 long_retry) { struct rt2x00_dev *rt2x00dev = hw->priv; u32 reg; @@ -1547,7 +1517,8 @@ static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw, } static int rt2400pci_conf_tx(struct ieee80211_hw *hw, - int queue, const struct ieee80211_tx_queue_params *params) + int queue, + const struct ieee80211_tx_queue_params *params) { struct rt2x00_dev *rt2x00dev = hw->priv; @@ -1559,7 +1530,7 @@ static int rt2400pci_conf_tx(struct ieee80211_hw *hw, if (queue != IEEE80211_TX_QUEUE_DATA0) return -EINVAL; - if (rt2x00lib_conf_tx(hw, queue, params)) + if (rt2x00mac_conf_tx(hw, queue, params)) return -EINVAL; /* @@ -1577,7 +1548,7 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw) u32 reg; rt2x00pci_register_read(rt2x00dev, CSR17, ®); - tsf = (u64)rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; + tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; rt2x00pci_register_read(rt2x00dev, CSR16, ®); tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); @@ -1602,17 +1573,19 @@ static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) } static const struct ieee80211_ops rt2400pci_mac80211_ops = { - .tx = rt2x00lib_tx, - .reset = rt2x00lib_reset, - .add_interface = rt2x00lib_add_interface, - .remove_interface = rt2x00lib_remove_interface, - .config = rt2x00lib_config, - .config_interface = rt2x00lib_config_interface, - .set_multicast_list = rt2x00lib_set_multicast_list, - .get_stats = rt2400pci_get_stats, + .tx = rt2x00mac_tx, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, + .remove_interface = rt2x00mac_remove_interface, + .config = rt2x00mac_config, + .config_interface = rt2x00mac_config_interface, + .configure_filter = rt2400pci_configure_filter, + .get_stats = rt2x00mac_get_stats, .set_retry_limit = rt2400pci_set_retry_limit, + .erp_ie_changed = rt2x00mac_erp_ie_changed, .conf_tx = rt2400pci_conf_tx, - .get_tx_stats = rt2x00lib_get_tx_stats, + .get_tx_stats = rt2x00mac_get_tx_stats, .get_tsf = rt2400pci_get_tsf, .reset_tsf = rt2400pci_reset_tsf, .beacon_update = rt2x00pci_beacon_update, @@ -1621,37 +1594,35 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = { static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { .irq_handler = rt2400pci_interrupt, - .init_hw = rt2400pci_init_hw, + .probe_hw = rt2400pci_probe_hw, .initialize = rt2x00pci_initialize, .uninitialize = rt2x00pci_uninitialize, .set_device_state = rt2400pci_set_device_state, -#ifdef CONFIG_RT2400PCI_RFKILL .rfkill_poll = rt2400pci_rfkill_poll, -#endif /* CONFIG_RT2400PCI_RFKILL */ + .link_stats = rt2400pci_link_stats, + .reset_tuner = rt2400pci_reset_tuner, .link_tuner = rt2400pci_link_tuner, .write_tx_desc = rt2400pci_write_tx_desc, .write_tx_data = rt2x00pci_write_tx_data, .kick_tx_queue = rt2400pci_kick_tx_queue, .fill_rxdone = rt2400pci_fill_rxdone, - .config_type = rt2400pci_config_type, - .config_phymode = rt2400pci_config_phymode, - .config_channel = rt2400pci_config_channel, .config_mac_addr = rt2400pci_config_mac_addr, .config_bssid = rt2400pci_config_bssid, - .config_promisc = rt2400pci_config_promisc, - .config_txpower = rt2400pci_config_txpower, - .config_antenna = rt2400pci_config_antenna, - .config_duration = rt2400pci_config_duration, + .config_type = rt2400pci_config_type, + .config_preamble = rt2400pci_config_preamble, + .config = rt2400pci_config, }; static const struct rt2x00_ops rt2400pci_ops = { - .name = DRV_NAME, - .rxd_size = RXD_DESC_SIZE, - .txd_size = TXD_DESC_SIZE, - .lib = &rt2400pci_rt2x00_ops, - .hw = &rt2400pci_mac80211_ops, + .name = DRV_NAME, + .rxd_size = RXD_DESC_SIZE, + .txd_size = TXD_DESC_SIZE, + .eeprom_size = EEPROM_SIZE, + .rf_size = RF_SIZE, + .lib = &rt2400pci_rt2x00_ops, + .hw = &rt2400pci_mac80211_ops, #ifdef CONFIG_RT2X00_LIB_DEBUGFS - .debugfs = &rt2400pci_rt2x00debug, + .debugfs = &rt2400pci_rt2x00debug, #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ }; @@ -1675,10 +1646,8 @@ static struct pci_driver rt2400pci_driver = { .id_table = rt2400pci_device_table, .probe = rt2x00pci_probe, .remove = __devexit_p(rt2x00pci_remove), -#ifdef CONFIG_PM .suspend = rt2x00pci_suspend, .resume = rt2x00pci_resume, -#endif /* CONFIG_PM */ }; static int __init rt2400pci_init(void) |