diff options
Diffstat (limited to 'package/mac80211')
7 files changed, 755 insertions, 604 deletions
diff --git a/package/mac80211/patches/300-ar9300_support.patch b/package/mac80211/patches/300-ar9300_support.patch index 9e494647a9..db8f408068 100644 --- a/package/mac80211/patches/300-ar9300_support.patch +++ b/package/mac80211/patches/300-ar9300_support.patch @@ -978,7 +978,7 @@ +#endif /* INITVALS_AR5008_H */ --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c -@@ -0,0 +1,1345 @@ +@@ -0,0 +1,1347 @@ +/* + * Copyright (c) 2008-2010 Atheros Communications Inc. + * @@ -1073,9 +1073,8 @@ + int reg_writes = 0; + u32 new_bias = 0; + -+ if (!AR_SREV_5416(ah) || synth_freq >= 3000) { ++ if (!AR_SREV_5416(ah) || synth_freq >= 3000) + return; -+ } + + BUG_ON(AR_SREV_9280_10_OR_LATER(ah)); + @@ -1192,7 +1191,8 @@ + * For non single-chip solutions. Converts to baseband spur frequency given the + * input channel frequency and compute register settings below. + */ -+static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) ++static void ar5008_hw_spur_mitigate(struct ath_hw *ah, ++ struct ath9k_channel *chan) +{ + int bb_spur = AR_NO_SPUR; + int bin, cur_bin; @@ -1721,7 +1721,10 @@ + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); + } + -+ /* Set correct baseband to analog shift setting to access analog chips */ ++ /* ++ * Set correct baseband to analog shift setting to ++ * access analog chips. ++ */ + REG_WRITE(ah, AR_PHY(0), 0x00000007); + + /* Write ADDAC shifts */ @@ -2126,8 +2129,7 @@ + break; + } + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ -+ const int cycpwrThr1[] = -+ { 2, 4, 6, 8, 10, 12, 14, 16 }; ++ const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; + u32 level = param; + + if (level >= ARRAY_SIZE(cycpwrThr1)) { @@ -3583,7 +3585,7 @@ + --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c -@@ -0,0 +1,988 @@ +@@ -0,0 +1,995 @@ +/* + * Copyright (c) 2008-2010 Atheros Communications Inc. + * @@ -3658,7 +3660,8 @@ + currCal->calData->calCollect(ah); + ah->cal_samples++; + -+ if (ah->cal_samples >= currCal->calData->calNumSamples) { ++ if (ah->cal_samples >= ++ currCal->calData->calNumSamples) { + int i, numChains = 0; + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + if (rxchainmask & (1 << i)) @@ -3972,8 +3975,9 @@ + + if (ah->initPDADC == 0 || currPDADC == 0) { + /* -+ * Zero value indicates that no frames have been transmitted yet, -+ * can't do temperature compensation until frames are transmitted. ++ * Zero value indicates that no frames have been transmitted ++ * yet, can't do temperature compensation until frames are ++ * transmitted. + */ + return; + } else { @@ -4025,7 +4029,7 @@ +{ + u32 regVal; + unsigned int i; -+ u32 regList [][2] = { ++ u32 regList[][2] = { + { 0x786c, 0 }, + { 0x7854, 0 }, + { 0x7820, 0 }, @@ -4063,16 +4067,16 @@ + /* 7820,b25,1, pdpadrv1=0 */ + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); + /* 7820,b24,0, pdpadrv2=0 */ -+ REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0); ++ REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); + /* 7820,b23,0, pdpaout=0 */ + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); + /* 783c,b14-16,7, padrvgn2tab_0=7 */ -+ REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7); ++ REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); + /* + * 7838,b29-31,0, padrvgn1tab_0=0 + * does not matter since we turn it off + */ -+ REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0); ++ REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); + + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff); + @@ -4090,14 +4094,14 @@ + regVal |= (1 << (20 + i)); + REG_WRITE(ah, 0x7834, regVal); + udelay(1); -+ //regVal = REG_READ(ah, 0x7834); ++ /* regVal = REG_READ(ah, 0x7834); */ + regVal &= (~(0x1 << (20 + i))); + regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9) + << (20 + i)); + REG_WRITE(ah, 0x7834, regVal); + } + -+ regVal = (regVal >>20) & 0x7f; ++ regVal = (regVal >> 20) & 0x7f; + + /* Update PA cal info */ + if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) { @@ -4287,12 +4291,16 @@ + ar9002_hw_pa_cal(ah, false); + ar9002_hw_olc_temp_compensation(ah); + -+ /* Get the value from the previous NF cal and update history buffer */ ++ /* ++ * Get the value from the previous NF cal and update ++ * history buffer. ++ */ + ath9k_hw_getnf(ah, chan); + + /* + * Load the NF from history buffer of the current channel. -+ * NF is slow time-variant, so it is OK to use a historical value. ++ * NF is slow time-variant, so it is OK to use a historical ++ * value. + */ + ath9k_hw_loadnf(ah, ah->curchan); + @@ -4422,7 +4430,8 @@ + AR_PHY_AGC_CONTROL_CAL); + + /* Poll for offset calibration complete */ -+ if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, ++ if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, ++ AR_PHY_AGC_CONTROL_CAL, + 0, AH_WAIT_TIMEOUT)) { + ath_print(common, ATH_DBG_CALIBRATE, + "offset calibration failed to " @@ -4574,7 +4583,7 @@ +} --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c -@@ -0,0 +1,584 @@ +@@ -0,0 +1,588 @@ +/* + * Copyright (c) 2008-2010 Atheros Communications Inc. + * @@ -4714,7 +4723,7 @@ + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, + ar9280PciePhy_clkreq_off_L1_9280, -+ ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); ++ ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); + } else { + INIT_INI_ARRAY(&ah->iniPcieSerdes, + ar9280PciePhy_clkreq_always_on_L1_9280, @@ -4812,10 +4821,12 @@ + if (AR_SREV_9287_11_OR_LATER(ah)) { + INIT_INI_ARRAY(&ah->iniCckfirNormal, + ar9287Common_normal_cck_fir_coeff_92871_1, -+ ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); ++ ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), ++ 2); + INIT_INI_ARRAY(&ah->iniCckfirJapan2484, + ar9287Common_japan_2484_cck_fir_coeff_92871_1, -+ ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); ++ ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), ++ 2); + } +} + @@ -4823,7 +4834,8 @@ +{ + u32 rxgain_type; + -+ if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { ++ if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= ++ AR5416_EEP_MINOR_VER_17) { + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); + + if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) @@ -4849,7 +4861,8 @@ +{ + u32 txgain_type; + -+ if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { ++ if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= ++ AR5416_EEP_MINOR_VER_19) { + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); + + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) @@ -5161,7 +5174,7 @@ +} --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h -@@ -0,0 +1,5229 @@ +@@ -0,0 +1,5230 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -9303,7 +9316,8 @@ + +/* + * For Japanese regulatory requirements, 2484 MHz requires the following three -+ * registers be programmed differently from the channel between 2412 and 2472 MHz. ++ * registers be programmed differently from the channel between 2412 and ++ * 2472 MHz. + */ +static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = { + { 0x0000a1f4, 0x00fffeff }, @@ -10393,7 +10407,7 @@ +#endif /* INITVALS_9002_10_H */ --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c -@@ -0,0 +1,462 @@ +@@ -0,0 +1,480 @@ +/* + * Copyright (c) 2008-2009 Atheros Communications Inc. + * @@ -10412,6 +10426,8 @@ + +#include "hw.h" + ++#define AR_BufLen 0x00000fff ++ +static void ar9002_hw_rx_enable(struct ath_hw *ah) +{ + REG_WRITE(ah, AR_CR, AR_CR_RXE); @@ -10837,6 +10853,22 @@ + ads->ds_ctl0 &= ~AR_VirtMoreFrag; +} + ++void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, ++ u32 size, u32 flags) ++{ ++ struct ar5416_desc *ads = AR5416DESC(ds); ++ struct ath9k_hw_capabilities *pCap = &ah->caps; ++ ++ ads->ds_ctl1 = size & AR_BufLen; ++ if (flags & ATH9K_RXDESC_INTREQ) ++ ads->ds_ctl1 |= AR_RxIntrReq; ++ ++ ads->ds_rxstatus8 &= ~AR_RxDone; ++ if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) ++ memset(&(ads->u), 0, sizeof(ads->u)); ++} ++EXPORT_SYMBOL(ath9k_hw_setuprxdesc); ++ +void ar9002_hw_attach_mac_ops(struct ath_hw *ah) +{ + struct ath_hw_ops *ops = ath9k_hw_ops(ah); @@ -10963,20 +10995,19 @@ + txctl | AR_PHY_CCK_TX_CTRL_JAPAN); + } else { + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, -+ txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); ++ txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); + } + } + } else { + bMode = 0; + fracMode = 0; + -+ switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { ++ switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { + case 0: -+ if ((freq % 20) == 0) { ++ if ((freq % 20) == 0) + aModeRefSel = 3; -+ } else if ((freq % 10) == 0) { ++ else if ((freq % 10) == 0) + aModeRefSel = 2; -+ } + if (aModeRefSel) + break; + case 1: @@ -11024,7 +11055,8 @@ + * For single-chip solutions. Converts to baseband spur frequency given the + * input channel frequency and compute register settings below. + */ -+static void ar9002_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) ++static void ar9002_hw_spur_mitigate(struct ath_hw *ah, ++ struct ath9k_channel *chan) +{ + int bb_spur = AR_NO_SPUR; + int freq; @@ -11432,7 +11464,7 @@ +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 +#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 + -+#define AR_PHY_TEST2 0x9808 ++#define AR_PHY_TEST2 0x9808 + +#define AR_PHY_TIMING2 0x9810 +#define AR_PHY_TIMING3 0x9814 @@ -11943,7 +11975,7 @@ +#define AR_PHY_POWER_TX_RATE8 0xA3D0 +#define AR_PHY_POWER_TX_RATE9 0xA3D4 + -+#define AR_PHY_XPA_CFG 0xA3D8 ++#define AR_PHY_XPA_CFG 0xA3D8 +#define AR_PHY_FORCE_XPA_CFG 0x000000001 +#define AR_PHY_FORCE_XPA_CFG_S 0 + @@ -11970,7 +12002,7 @@ +#endif --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c -@@ -0,0 +1,798 @@ +@@ -0,0 +1,802 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -11997,7 +12029,7 @@ + struct ath_common *common = ath9k_hw_common(ah); + + /* Select calibration to run */ -+ switch(currCal->calData->calType) { ++ switch (currCal->calData->calType) { + case IQ_MISMATCH_CAL: + /* + * Start calibration with @@ -12123,7 +12155,8 @@ + if (longcal) { + /* + * Load the NF from history buffer of the current channel. -+ * NF is slow time-variant, so it is OK to use a historical value. ++ * NF is slow time-variant, so it is OK to use a historical ++ * value. + */ + ath9k_hw_loadnf(ah, ah->curchan); + @@ -12228,7 +12261,7 @@ + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", + i, iCoff, qCoff); + ath_print(common, ATH_DBG_CALIBRATE, -+ "Register offset (0x%04x) " ++ "Register offset (0x%04x) " + "before update = 0x%x\n", + offset_array[i], + REG_READ(ah, offset_array[i])); @@ -12248,7 +12281,8 @@ + ath_print(common, ATH_DBG_CALIBRATE, + "Register offset (0x%04x) QQ COFF " + "(bitfields 0x%08x) after update = 0x%x\n", -+ offset_array[i], AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, ++ offset_array[i], ++ AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, + REG_READ(ah, offset_array[i])); + + ath_print(common, ATH_DBG_CALIBRATE, @@ -12268,9 +12302,9 @@ +} + +static const struct ath9k_percal_data iq_cal_single_sample = { -+ IQ_MISMATCH_CAL, -+ MIN_CAL_SAMPLES, -+ PER_MAX_LOG_COUNT, ++ IQ_MISMATCH_CAL, ++ MIN_CAL_SAMPLES, ++ PER_MAX_LOG_COUNT, + ar9003_hw_iqcal_collect, + ar9003_hw_iqcalibrate +}; @@ -12366,7 +12400,7 @@ + min_abs = abs_i; + } + -+ return (max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4)); ++ return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4); +} + +#define DELPT 32 @@ -12658,7 +12692,9 @@ + AR_PHY_CHAN_INFO_TAB_S2_READ, 1); + + /* 16 bits */ -+ iq_res[idx+1] = 0xffff & REG_READ(ah, chan_info_tab[i] + offset); ++ iq_res[idx+1] = 0xffff & REG_READ(ah, ++ chan_info_tab[i] + ++ offset); + + ath_print(common, ATH_DBG_CALIBRATE, + "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n", @@ -12771,7 +12807,7 @@ +} --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c -@@ -0,0 +1,1841 @@ +@@ -0,0 +1,1856 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -12912,9 +12948,9 @@ + }, + /* ar9300_cal_data_per_freq_op_loop 2g */ + .calPierData2G = { -+ {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}}, -+ {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}}, -+ {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}}, ++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, ++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, ++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, + }, + .calTarget_freqbin_Cck = { + FREQ2FBIN(2412, 1), @@ -12937,24 +12973,24 @@ + }, + .calTargetPowerCck = { + /* 1L-5L,5S,11L,11S */ -+ {{36, 36, 36, 36}}, -+ {{36, 36, 36, 36}}, ++ { {36, 36, 36, 36} }, ++ { {36, 36, 36, 36} }, + }, + .calTargetPower2G = { + /* 6-24,36,48,54 */ -+ {{32, 32, 28, 24}}, -+ {{32, 32, 28, 24}}, -+ {{32, 32, 28, 24}}, ++ { {32, 32, 28, 24} }, ++ { {32, 32, 28, 24} }, ++ { {32, 32, 28, 24} }, + }, + .calTargetPower2GHT20 = { -+ {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}}, -+ {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}}, -+ {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}}, ++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, ++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, ++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, + }, + .calTargetPower2GHT40 = { -+ {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}}, -+ {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}}, -+ {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}}, ++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, ++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, ++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, + }, + .ctlIndex_2G = { + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, @@ -13044,20 +13080,20 @@ + } + }, + .ctlPowerData_2G = { -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, -+ {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, ++ { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, + -+ {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}}, -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, ++ { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, + -+ {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, ++ { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, + -+ {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, -+ {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, ++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, ++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, + }, + .modalHeader5G = { + /* 4 idle,t1,t2,b (4 bits per setting) */ @@ -13177,42 +13213,42 @@ + }, + .calTargetPower5G = { + /* 6-24,36,48,54 */ -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, -+ {{20, 20, 20, 10}}, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, ++ { {20, 20, 20, 10} }, + }, + .calTargetPower5GHT20 = { + /* + * 0_8_16,1-3_9-11_17-19, + * 4,5,6,7,12,13,14,15,20,21,22,23 + */ -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, + }, + .calTargetPower5GHT40 = { + /* + * 0_8_16,1-3_9-11_17-19, + * 4,5,6,7,12,13,14,15,20,21,22,23 + */ -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, -+ {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}}, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, ++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, + }, + .ctlIndex_5G = { + 0x10, 0x16, 0x18, 0x40, 0x46, @@ -13412,9 +13448,9 @@ + return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH; + case EEP_INTERNAL_REGULATOR: + /* Bit 4 is internal regulator flag */ -+ return ((pBase->featureEnable & 0x10) >> 4); ++ return (pBase->featureEnable & 0x10) >> 4; + case EEP_SWREG: -+ return (pBase->swreg); ++ return pBase->swreg; + default: + return 0; + } @@ -13456,7 +13492,7 @@ +#endif + +static bool ar9300_hw_read_eeprom(struct ath_hw *ah, -+ long address, u8 * buffer, int many) ++ long address, u8 *buffer, int many) +{ + int i; + u8 value[2]; @@ -13467,7 +13503,7 @@ + + if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) { + ath_print(common, ATH_DBG_EEPROM, -+ "eeprom address not in range \n"); ++ "eeprom address not in range\n"); + return false; + } + @@ -13488,17 +13524,19 @@ +} + +static bool ar9300_read_eeprom(struct ath_hw *ah, -+ int address, u8 * buffer, int many) ++ int address, u8 *buffer, int many) +{ + int it; + + for (it = 0; it < many; it++) -+ if (!ar9300_hw_read_eeprom(ah, (address - it), (buffer + it), 1)) ++ if (!ar9300_hw_read_eeprom(ah, ++ (address - it), ++ (buffer + it), 1)) + return false; + return true; +} + -+static void ar9300_comp_hdr_unpack(u8 * best, int *code, int *reference, ++static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, + int *length, int *major, int *minor) +{ + unsigned long value[4]; @@ -13514,7 +13552,7 @@ + *minor = (value[3] & 0x00ff); +} + -+static u16 ar9300_comp_cksum(u8 * data, int dsize) ++static u16 ar9300_comp_cksum(u8 *data, int dsize) +{ + int it, checksum = 0; + @@ -13549,13 +13587,15 @@ + + if (length > 0 && spot >= 0 && spot+length < mdataSize) { + ath_print(common, ATH_DBG_EEPROM, -+ "Restore at %d: spot=%d offset=%d length=%d\n", ++ "Restore at %d: spot=%d " ++ "offset=%d length=%d\n", + it, spot, offset, length); -+ memcpy(&mptr[spot],&block[it+2],length); ++ memcpy(&mptr[spot], &block[it+2], length); + spot += length; + } else if (length > 0) { + ath_print(common, ATH_DBG_EEPROM, -+ "Bad restore at %d: spot=%d offset=%d length=%d\n", ++ "Bad restore at %d: spot=%d " ++ "offset=%d length=%d\n", + it, spot, offset, length); + return false; + } @@ -13567,8 +13607,8 @@ + int it, + int code, + int reference, -+ u8 * mptr, -+ u8 * word, int length, int mdata_size) ++ u8 *mptr, ++ u8 *word, int length, int mdata_size) +{ + struct ath_common *common = ath9k_hw_common(ah); + u8 *dptr; @@ -13619,7 +13659,7 @@ + * Returns address of next memory location on success. + */ +static int ar9300_eeprom_restore_internal(struct ath_hw *ah, -+ u8 * mptr, int mdata_size) ++ u8 *mptr, int mdata_size) +{ +#define MDEFAULT 15 +#define MSTATE 100 @@ -13697,7 +13737,7 @@ + u8 *mptr = NULL; + int mdata_size; + -+ mptr = (u8 *) & ah->eeprom.ar9300_eep; ++ mptr = (u8 *) &ah->eeprom.ar9300_eep; + mdata_size = sizeof(struct ar9300_eeprom); + + if (mptr && mdata_size > 0) { @@ -13768,7 +13808,7 @@ + + if (is2ghz) + return eep->modalHeader2G.antCtrlCommon; -+ else ++ else + return eep->modalHeader5G.antCtrlCommon; +} + @@ -13782,18 +13822,20 @@ + return eep->modalHeader5G.antCtrlCommon2; +} + -+static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, bool is2ghz) ++static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, ++ int chain, ++ bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + + if (chain >= 0 && chain < AR9300_MAX_CHAINS) { + if (is2ghz) + return eep->modalHeader2G.antCtrlChain[chain]; -+ else ++ else + return eep->modalHeader5G.antCtrlChain[chain]; + } + -+ return 0; ++ return 0; +} + +static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) @@ -13904,7 +13946,7 @@ + * the returned y value is equal to the py for the highest px. + */ +static int ar9003_hw_power_interpolate(int32_t x, -+ int32_t * px, int32_t * py, u_int16_t np) ++ int32_t *px, int32_t *py, u_int16_t np) +{ + int ip = 0; + int lx = 0, ly = 0, lhave = 0; @@ -13952,7 +13994,7 @@ + y = ly; + } else if (hhave) /* only high is good, use it */ + y = hy; -+ else /* nothing is good,this should never happen unless np=0, ???? */ ++ else /* nothing is good,this should never happen unless np=0, ???? */ + y = -(1 << 30); + return y; +} @@ -13987,9 +14029,9 @@ + } + + /* interpolate to get target power for given frequency */ -+ return ((u8) ar9003_hw_power_interpolate((s32) freq, ++ return (u8) ar9003_hw_power_interpolate((s32) freq, + freqArray, -+ targetPowerArray, numPiers)); ++ targetPowerArray, numPiers); +} + +static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, @@ -14023,9 +14065,9 @@ + } + + /* interpolate to get target power for given frequency */ -+ return ((u8) ar9003_hw_power_interpolate((s32) freq, ++ return (u8) ar9003_hw_power_interpolate((s32) freq, + freqArray, -+ targetPowerArray, numPiers)); ++ targetPowerArray, numPiers); +} + +static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, @@ -14059,9 +14101,9 @@ + } + + /* interpolate to get target power for given frequency */ -+ return ((u8) ar9003_hw_power_interpolate((s32) freq, ++ return (u8) ar9003_hw_power_interpolate((s32) freq, + freqArray, -+ targetPowerArray, numPiers)); ++ targetPowerArray, numPiers); +} + +static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, @@ -14084,9 +14126,9 @@ + } + + /* interpolate to get target power for given frequency */ -+ return ((u8) ar9003_hw_power_interpolate((s32) freq, ++ return (u8) ar9003_hw_power_interpolate((s32) freq, + freqArray, -+ targetPowerArray, numPiers)); ++ targetPowerArray, numPiers); +} + +/* Set tx power registers to array of values passed in */ @@ -14118,7 +14160,7 @@ + REG_WRITE(ah, 0xa3c8, + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) | + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | -+ // POW_SM(txPowerTimes2, 8) | /* this is reserved for AR9003 */ ++ /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)); + + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ @@ -14165,9 +14207,11 @@ + POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0) + ); + -+ /* Write the HT40 power per rate set */ -+ // correct PAR difference between HT40 and HT20/LEGACY -+ /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ ++ /* ++ * Write the HT40 power per rate set ++ * correct PAR difference between HT40 and HT20/LEGACY ++ * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) ++ */ + REG_WRITE(ah, 0xa3d8, + POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) | + POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) | @@ -14328,7 +14372,7 @@ + i++; + + ath_print(common, ATH_DBG_EEPROM, -+ "TPC[%02d] 0x%08x \n", i, targetPowerValT2[i]); ++ "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); + i++; + } + @@ -14360,7 +14404,8 @@ + if (mode) { /* 5GHz */ + if (ipier >= AR9300_NUM_5G_CAL_PIERS) { + ath_print(common, ATH_DBG_EEPROM, -+ "Invalid 5GHz cal pier index, must be less than %d\n", ++ "Invalid 5GHz cal pier index, must " ++ "be less than %d\n", + AR9300_NUM_5G_CAL_PIERS); + return -1; + } @@ -14477,7 +14522,10 @@ + hfrequency[ichain] >= 100000 || + fdiff > + (frequency - hfrequency[ichain])) { -+ /* new best higher frequency measurement */ ++ /* ++ * new best higher ++ * frequency measurement ++ */ + hfrequency[ichain] = pfrequency; + hcorrection[ichain] = + pcorrection; @@ -14490,7 +14538,10 @@ + if (lfrequency[ichain] <= 0 + || fdiff < + (frequency - lfrequency[ichain])) { -+ /* new best lower frequency measurement */ ++ /* ++ * new best lower ++ * frequency measurement ++ */ + lfrequency[ichain] = pfrequency; + lcorrection[ichain] = + pcorrection; @@ -14626,7 +14677,7 @@ +#define AR9300_EEP_MINOR_VER_1 0x1 +#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1 + -+// 16-bit offset location start of calibration struct ++/* 16-bit offset location start of calibration struct */ +#define AR9300_EEP_START_LOC 256 +#define AR9300_NUM_5G_CAL_PIERS 8 +#define AR9300_NUM_2G_CAL_PIERS 3 @@ -14635,7 +14686,7 @@ +#define AR9300_NUM_2G_CCK_TARGET_POWERS 2 +#define AR9300_NUM_2G_20_TARGET_POWERS 3 +#define AR9300_NUM_2G_40_TARGET_POWERS 3 -+//#define AR9300_NUM_CTLS 21 ++/* #define AR9300_NUM_CTLS 21 */ +#define AR9300_NUM_CTLS_5G 9 +#define AR9300_NUM_CTLS_2G 12 +#define AR9300_CTL_MODE_M 0xF @@ -14660,8 +14711,8 @@ +#define AR9300_EEPMISC_WOW 0x02 +#define AR9300_CUSTOMER_DATA_SIZE 20 + -+#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) -+#define FBIN2FREQ(x,y) ((y) ? (2300 + x) : (4800 + 5 * x)) ++#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) ++#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) +#define AR9300_MAX_CHAINS 3 +#define AR9300_ANT_16S 25 +#define AR9300_FUTURE_MODAL_SZ 6 @@ -14693,7 +14744,7 @@ +#define ENABLE_TEMP_COMPENSATION 0x01 +#define ENABLE_VOLT_COMPENSATION 0x02 +/* byte addressable */ -+#define AR9300_EEPROM_SIZE 16*1024 ++#define AR9300_EEPROM_SIZE (16*1024) +#define FIXED_CCA_THRESHOLD 15 + +#define AR9300_BASE_ADDR 0x3ff @@ -14878,8 +14929,8 @@ +} __packed; + +struct cal_ctl_edge_pwr { -+ u8 tPower :6, -+ flag :2; ++ u8 tPower:6, ++ flag:2; +} __packed; + +struct cal_ctl_data_2g { @@ -14959,6 +15010,7 @@ + */ + +#include "hw.h" ++#include "ar9003_mac.h" +#include "ar9003_initvals.h" + +/* General hardware code for the AR9003 hadware family */ @@ -15051,7 +15103,7 @@ + +static void ar9003_tx_gain_table_apply(struct ath_hw *ah) +{ -+ switch(ar9003_hw_get_tx_gain_idx(ah)) { ++ switch (ar9003_hw_get_tx_gain_idx(ah)) { + case 0: + default: + INIT_INI_ARRAY(&ah->iniModesTxGain, @@ -15076,8 +15128,7 @@ + +static void ar9003_rx_gain_table_apply(struct ath_hw *ah) +{ -+ switch(ar9003_hw_get_rx_gain_idx(ah)) -+ { ++ switch (ar9003_hw_get_rx_gain_idx(ah)) { + case 0: + default: + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0, @@ -16945,7 +16996,7 @@ +#endif /* INITVALS_9003_H */ --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c -@@ -0,0 +1,610 @@ +@@ -0,0 +1,611 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -16962,6 +17013,7 @@ + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "hw.h" ++#include "ar9003_mac.h" + +static void ar9003_hw_rx_enable(struct ath_hw *hw) +{ @@ -17558,7 +17610,7 @@ +EXPORT_SYMBOL(ath9k_hw_setup_statusring); --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h -@@ -0,0 +1,124 @@ +@@ -0,0 +1,120 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -17586,6 +17638,8 @@ +#define AR_TxRxDesc_S 15 +#define AR_TxQcuNum 0x00000f00 +#define AR_TxQcuNum_S 8 ++ ++#define AR_BufLen 0x0fff0000 +#define AR_BufLen_S 16 + +#define AR_TxDescId 0xffff0000 @@ -17609,12 +17663,6 @@ + +#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds) + -+enum ath9k_rx_qtype { -+ ATH9K_RX_QUEUE_HP, -+ ATH9K_RX_QUEUE_LP, -+ ATH9K_RX_QUEUE_MAX, -+}; -+ +struct ar9003_rxs { + u32 ds_info; + u32 status1; @@ -17685,7 +17733,7 @@ +#endif --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c -@@ -0,0 +1,1138 @@ +@@ -0,0 +1,1142 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -17765,13 +17813,13 @@ + AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); + + /* Program Synth. setting */ -+ reg32 = (channelSel << 2 ) | (fracMode << 30) | ++ reg32 = (channelSel << 2) | (fracMode << 30) | + (aModeRefSel << 28) | (loadSynthChannel << 31); + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); + + /* Toggle Load Synth channel bit */ + loadSynthChannel = 1; -+ reg32 = (channelSel << 2 ) | (fracMode << 30) | ++ reg32 = (channelSel << 2) | (fracMode << 30) | + (aModeRefSel << 28) | (loadSynthChannel << 31); + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); + @@ -17807,7 +17855,7 @@ + negative = 0; + cur_bb_spur = spur_freq[i] - chan->channel; + -+ if(cur_bb_spur < 0) { ++ if (cur_bb_spur < 0) { + negative = 1; + cur_bb_spur = -cur_bb_spur; + } @@ -17824,11 +17872,14 @@ + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, + AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, -+ AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2); ++ AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, ++ 0x2); + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, -+ AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x1); ++ AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, ++ 0x1); + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, -+ AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, cck_spur_freq); ++ AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, ++ cck_spur_freq); + + return; + } @@ -18188,7 +18239,8 @@ + * MAC addr only will fail. + */ + val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); -+ REG_WRITE(ah, AR_PCU_MISC_MODE2, val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); ++ REG_WRITE(ah, AR_PCU_MISC_MODE2, ++ val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); +} + +static void ar9003_hw_prog_ini(struct ath_hw *ah, @@ -18479,7 +18531,8 @@ + REG_RMW_FIELD(ah, AR_PHY_SFCORR, + AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]); + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, -+ AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]); ++ AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, ++ m2CountThrLow[on]); + + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]); @@ -18544,8 +18597,7 @@ + break; + } + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ -+ const int cycpwrThr1[] = -+ { 2, 4, 6, 8, 10, 12, 14, 16 }; ++ const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; + u32 level = param; + + if (level >= ARRAY_SIZE(cycpwrThr1)) { @@ -18717,7 +18769,7 @@ + * 01x => Chain 1 and 0 enabled + * 1xx => Chain 2,1 and 0 enabled + */ -+ return (chain & 0x7); ++ return chain & 0x7; +} + +static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) @@ -18851,16 +18903,16 @@ + */ +#define AR_CHAN_BASE 0x9800 + -+#define AR_PHY_TIMING1 AR_CHAN_BASE + 0x0 -+#define AR_PHY_TIMING2 AR_CHAN_BASE + 0x4 -+#define AR_PHY_TIMING3 AR_CHAN_BASE + 0x8 -+#define AR_PHY_TIMING4 AR_CHAN_BASE + 0xc -+#define AR_PHY_TIMING5 AR_CHAN_BASE + 0x10 -+#define AR_PHY_TIMING6 AR_CHAN_BASE + 0x14 -+#define AR_PHY_TIMING11 AR_CHAN_BASE + 0x18 -+#define AR_PHY_SPUR_REG AR_CHAN_BASE + 0x1c -+#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_BASE + 0xdc -+#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_BASE + 0xb0 ++#define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0) ++#define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4) ++#define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8) ++#define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc) ++#define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10) ++#define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14) ++#define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18) ++#define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c) ++#define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc) ++#define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0) + +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 @@ -18892,25 +18944,25 @@ +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 + -+#define AR_PHY_FIND_SIG_LOW AR_CHAN_BASE + 0x20 ++#define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20) + -+#define AR_PHY_SFCORR AR_CHAN_BASE + 0x24 -+#define AR_PHY_SFCORR_LOW AR_CHAN_BASE + 0x28 -+#define AR_PHY_SFCORR_EXT AR_CHAN_BASE + 0x2c ++#define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24) ++#define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28) ++#define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c) + -+#define AR_PHY_EXT_CCA AR_CHAN_BASE + 0x30 -+#define AR_PHY_RADAR_0 AR_CHAN_BASE + 0x34 -+#define AR_PHY_RADAR_1 AR_CHAN_BASE + 0x38 -+#define AR_PHY_RADAR_EXT AR_CHAN_BASE + 0x3c -+#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_BASE + 0x80 -+#define AR_PHY_PERCHAIN_CSD AR_CHAN_BASE + 0x84 ++#define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30) ++#define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34) ++#define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38) ++#define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c) ++#define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80) ++#define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84) + -+#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_BASE + 0xd0 -+#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_BASE + 0xd4 -+#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_BASE + 0xc0 -+#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_BASE + 0xc4 -+#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_BASE + 0xc8 -+#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_BASE + 0xcc ++#define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0) ++#define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4) ++#define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0) ++#define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4) ++#define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8) ++#define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc) + +/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */ +#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10) @@ -18920,10 +18972,10 @@ +#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8) +#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8) + -+#define AR_PHY_TX_CRC AR_CHAN_BASE + 0xa0 -+#define AR_PHY_TST_DAC_CONST AR_CHAN_BASE + 0xa4 -+#define AR_PHY_SPUR_REPORT_0 AR_CHAN_BASE + 0xa8 -+#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_BASE + 0x300 ++#define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0) ++#define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4) ++#define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8) ++#define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300) + +/* + * Channel Field Definitions @@ -19040,15 +19092,15 @@ + */ +#define AR_MRC_BASE 0x9c00 + -+#define AR_PHY_TIMING_3A AR_MRC_BASE + 0x0 -+#define AR_PHY_LDPC_CNTL1 AR_MRC_BASE + 0x4 -+#define AR_PHY_LDPC_CNTL2 AR_MRC_BASE + 0x8 -+#define AR_PHY_PILOT_SPUR_MASK AR_MRC_BASE + 0xc -+#define AR_PHY_CHAN_SPUR_MASK AR_MRC_BASE + 0x10 -+#define AR_PHY_SGI_DELTA AR_MRC_BASE + 0x14 -+#define AR_PHY_ML_CNTL_1 AR_MRC_BASE + 0x18 -+#define AR_PHY_ML_CNTL_2 AR_MRC_BASE + 0x1c -+#define AR_PHY_TST_ADC AR_MRC_BASE + 0x20 ++#define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0) ++#define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4) ++#define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8) ++#define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc) ++#define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10) ++#define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14) ++#define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18) ++#define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c) ++#define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20) + +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 @@ -19077,32 +19129,32 @@ + */ +#define AR_AGC_BASE 0x9e00 + -+#define AR_PHY_SETTLING AR_AGC_BASE + 0x0 -+#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_BASE + 0x4 -+#define AR_PHY_GAINS_MINOFF0 AR_AGC_BASE + 0x8 -+#define AR_PHY_DESIRED_SZ AR_AGC_BASE + 0xc -+#define AR_PHY_FIND_SIG AR_AGC_BASE + 0x10 -+#define AR_PHY_AGC AR_AGC_BASE + 0x14 -+#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_BASE + 0x18 -+#define AR_PHY_CCA_0 AR_AGC_BASE + 0x1c -+#define AR_PHY_EXT_CCA0 AR_AGC_BASE + 0x20 -+#define AR_PHY_RESTART AR_AGC_BASE + 0x24 -+#define AR_PHY_MC_GAIN_CTRL AR_AGC_BASE + 0x28 -+#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_BASE + 0x2c -+#define AR_PHY_EXT_CHN_WIN AR_AGC_BASE + 0x30 -+#define AR_PHY_20_40_DET_THR AR_AGC_BASE + 0x34 -+#define AR_PHY_RIFS_SRCH AR_AGC_BASE + 0x38 -+#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_BASE + 0x3c -+#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_BASE + 0x40 -+#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_BASE + 0x44 -+#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_BASE + 0x48 -+#define AR_PHY_RSSI_0 AR_AGC_BASE + 0x180 -+#define AR_PHY_SPUR_CCK_REP0 AR_AGC_BASE + 0x184 -+#define AR_PHY_CCK_DETECT AR_AGC_BASE + 0x1c0 -+#define AR_PHY_DAG_CTRLCCK AR_AGC_BASE + 0x1c4 -+#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_BASE + 0x1c8 -+ -+#define AR_PHY_CCK_SPUR_MIT AR_AGC_BASE + 0x1cc ++#define AR_PHY_SETTLING (AR_AGC_BASE + 0x0) ++#define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4) ++#define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8) ++#define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc) ++#define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10) ++#define AR_PHY_AGC (AR_AGC_BASE + 0x14) ++#define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18) ++#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) ++#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20) ++#define AR_PHY_RESTART (AR_AGC_BASE + 0x24) ++#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28) ++#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) ++#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) ++#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34) ++#define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38) ++#define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c) ++#define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40) ++#define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44) ++#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48) ++#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180) ++#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184) ++#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0) ++#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4) ++#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8) ++ ++#define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc) +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 @@ -19112,7 +19164,7 @@ +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 + -+#define AR_PHY_RX_OCGAIN AR_AGC_BASE + 0x200 ++#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) + +#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110 +#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115 @@ -19211,49 +19263,49 @@ + */ +#define AR_SM_BASE 0xa200 + -+#define AR_PHY_D2_CHIP_ID AR_SM_BASE + 0x0 -+#define AR_PHY_GEN_CTRL AR_SM_BASE + 0x4 -+#define AR_PHY_MODE AR_SM_BASE + 0x8 -+#define AR_PHY_ACTIVE AR_SM_BASE + 0xc -+#define AR_PHY_SPUR_MASK_A AR_SM_BASE + 0x20 -+#define AR_PHY_SPUR_MASK_B AR_SM_BASE + 0x24 -+#define AR_PHY_SPECTRAL_SCAN AR_SM_BASE + 0x28 -+#define AR_PHY_RADAR_BW_FILTER AR_SM_BASE + 0x2c -+#define AR_PHY_SEARCH_START_DELAY AR_SM_BASE + 0x30 -+#define AR_PHY_MAX_RX_LEN AR_SM_BASE + 0x34 -+#define AR_PHY_FRAME_CTL AR_SM_BASE + 0x38 -+#define AR_PHY_RFBUS_REQ AR_SM_BASE + 0x3c -+#define AR_PHY_RFBUS_GRANT AR_SM_BASE + 0x40 -+#define AR_PHY_RIFS AR_SM_BASE + 0x44 -+#define AR_PHY_RX_CLR_DELAY AR_SM_BASE + 0x50 -+#define AR_PHY_RX_DELAY AR_SM_BASE + 0x54 -+ -+#define AR_PHY_XPA_TIMING_CTL AR_SM_BASE + 0x64 -+#define AR_PHY_MISC_PA_CTL AR_SM_BASE + 0x80 -+#define AR_PHY_SWITCH_CHAIN_0 AR_SM_BASE + 0x84 -+#define AR_PHY_SWITCH_COM AR_SM_BASE + 0x88 -+#define AR_PHY_SWITCH_COM_2 AR_SM_BASE + 0x8c -+#define AR_PHY_RX_CHAINMASK AR_SM_BASE + 0xa0 -+#define AR_PHY_CAL_CHAINMASK AR_SM_BASE + 0xc0 -+#define AR_PHY_CALMODE AR_SM_BASE + 0xc8 -+#define AR_PHY_FCAL_1 AR_SM_BASE + 0xcc -+#define AR_PHY_FCAL_2_0 AR_SM_BASE + 0xd0 -+#define AR_PHY_DFT_TONE_CTL_0 AR_SM_BASE + 0xd4 -+#define AR_PHY_CL_CAL_CTL AR_SM_BASE + 0xd8 -+#define AR_PHY_CL_TAB_0 AR_SM_BASE + 0x100 -+#define AR_PHY_SYNTH_CONTROL AR_SM_BASE + 0x140 -+#define AR_PHY_ADDAC_CLK_SEL AR_SM_BASE + 0x144 -+#define AR_PHY_PLL_CTL AR_SM_BASE + 0x148 -+#define AR_PHY_ANALOG_SWAP AR_SM_BASE + 0x14c -+#define AR_PHY_ADDAC_PARA_CTL AR_SM_BASE + 0x150 -+#define AR_PHY_XPA_CFG AR_SM_BASE + 0x158 ++#define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0) ++#define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4) ++#define AR_PHY_MODE (AR_SM_BASE + 0x8) ++#define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) ++#define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20) ++#define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24) ++#define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) ++#define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) ++#define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30) ++#define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34) ++#define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38) ++#define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c) ++#define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40) ++#define AR_PHY_RIFS (AR_SM_BASE + 0x44) ++#define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50) ++#define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54) ++ ++#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64) ++#define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80) ++#define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84) ++#define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88) ++#define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c) ++#define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0) ++#define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0) ++#define AR_PHY_CALMODE (AR_SM_BASE + 0xc8) ++#define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc) ++#define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0) ++#define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4) ++#define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8) ++#define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100) ++#define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140) ++#define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144) ++#define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148) ++#define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c) ++#define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150) ++#define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158) + +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 + -+#define AR_PHY_TEST AR_SM_BASE + 0x160 ++#define AR_PHY_TEST (AR_SM_BASE + 0x160) + +#define AR_PHY_TEST_BBB_OBS_SEL 0x780000 +#define AR_PHY_TEST_BBB_OBS_SEL_S 19 @@ -19264,7 +19316,7 @@ +#define AR_PHY_TEST_CHAIN_SEL 0xC0000000 +#define AR_PHY_TEST_CHAIN_SEL_S 30 + -+#define AR_PHY_TEST_CTL_STATUS AR_SM_BASE + 0x164 ++#define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164) +#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 +#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 +#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C @@ -19277,49 +19329,49 @@ +#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 + + -+#define AR_PHY_TSTDAC AR_SM_BASE + 0x168 ++#define AR_PHY_TSTDAC (AR_SM_BASE + 0x168) + -+#define AR_PHY_CHAN_STATUS AR_SM_BASE + 0x16c -+#define AR_PHY_CHAN_INFO_MEMORY AR_SM_BASE + 0x170 -+#define AR_PHY_CHNINFO_NOISEPWR AR_SM_BASE + 0x174 -+#define AR_PHY_CHNINFO_GAINDIFF AR_SM_BASE + 0x178 -+#define AR_PHY_CHNINFO_FINETIM AR_SM_BASE + 0x17c -+#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_BASE + 0x180 -+#define AR_PHY_SCRAMBLER_SEED AR_SM_BASE + 0x190 -+#define AR_PHY_CCK_TX_CTRL AR_SM_BASE + 0x194 ++#define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c) ++#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170) ++#define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174) ++#define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178) ++#define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c) ++#define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180) ++#define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190) ++#define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194) + -+#define AR_PHY_HEAVYCLIP_CTL AR_SM_BASE + 0x1a4 -+#define AR_PHY_HEAVYCLIP_20 AR_SM_BASE + 0x1a8 -+#define AR_PHY_HEAVYCLIP_40 AR_SM_BASE + 0x1ac -+#define AR_PHY_ILLEGAL_TXRATE AR_SM_BASE + 0x1b0 ++#define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4) ++#define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) ++#define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) ++#define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0) + -+#define AR_PHY_PWRTX_MAX AR_SM_BASE + 0x1f0 -+#define AR_PHY_POWER_TX_SUB AR_SM_BASE + 0x1f4 ++#define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0) ++#define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4) + -+#define AR_PHY_TPC_4_B0 AR_SM_BASE + 0x204 -+#define AR_PHY_TPC_5_B0 AR_SM_BASE + 0x208 -+#define AR_PHY_TPC_6_B0 AR_SM_BASE + 0x20c -+#define AR_PHY_TPC_11_B0 AR_SM_BASE + 0x220 -+#define AR_PHY_TPC_18 AR_SM_BASE + 0x23c -+#define AR_PHY_TPC_19 AR_SM_BASE + 0x240 ++#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204) ++#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208) ++#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c) ++#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220) ++#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c) ++#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240) + -+#define AR_PHY_TX_FORCED_GAIN AR_SM_BASE + 0x258 ++#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258) + -+#define AR_PHY_PDADC_TAB_0 AR_SM_BASE + 0x280 ++#define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280) + -+#define AR_PHY_TX_IQCAL_CONTROL_1 AR_SM_BASE + 0x448 -+#define AR_PHY_TX_IQCAL_START AR_SM_BASE + 0x440 -+#define AR_PHY_TX_IQCAL_STATUS_B0 AR_SM_BASE + 0x48c -+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_BASE + 0x450 ++#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448) ++#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440) ++#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c) ++#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450) + -+#define AR_PHY_PANIC_WD_STATUS AR_SM_BASE + 0x5c0 -+#define AR_PHY_PANIC_WD_CTL_1 AR_SM_BASE + 0x5c4 -+#define AR_PHY_PANIC_WD_CTL_2 AR_SM_BASE + 0x5c8 -+#define AR_PHY_BT_CTL AR_SM_BASE + 0x5cc -+#define AR_PHY_ONLY_WARMRESET AR_SM_BASE + 0x5d0 -+#define AR_PHY_ONLY_CTL AR_SM_BASE + 0x5d4 -+#define AR_PHY_ECO_CTRL AR_SM_BASE + 0x5dc -+#define AR_PHY_BB_THERM_ADC_1 AR_SM_BASE + 0x248 ++#define AR_PHY_PANIC_WD_STATUS (AR_SM_BASE + 0x5c0) ++#define AR_PHY_PANIC_WD_CTL_1 (AR_SM_BASE + 0x5c4) ++#define AR_PHY_PANIC_WD_CTL_2 (AR_SM_BASE + 0x5c8) ++#define AR_PHY_BT_CTL (AR_SM_BASE + 0x5cc) ++#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0) ++#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4) ++#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc) ++#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248) + +#define AR_PHY_65NM_CH0_SYNTH4 0x1608c +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 @@ -19505,13 +19557,13 @@ + */ +#define AR_CHAN1_BASE 0xa800 + -+#define AR_PHY_EXT_CCA_1 AR_CHAN1_BASE + 0x30 -+#define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_BASE + 0xd0 -+#define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_BASE + 0xd4 ++#define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30) ++#define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0) ++#define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4) + -+#define AR_PHY_SPUR_REPORT_1 AR_CHAN1_BASE + 0xa8 -+#define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_BASE + 0x300 -+#define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_BASE + 0xdc ++#define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8) ++#define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300) ++#define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc) + +/* + * Channel 1 Field Definitions @@ -19524,13 +19576,13 @@ + */ +#define AR_AGC1_BASE 0xae00 + -+#define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_BASE + 0x4 -+#define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_BASE + 0x18 -+#define AR_PHY_CCA_1 AR_AGC1_BASE + 0x1c -+#define AR_PHY_CCA_CTRL_1 AR_AGC1_BASE + 0x20 -+#define AR_PHY_RSSI_1 AR_AGC1_BASE + 0x180 -+#define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_BASE + 0x184 -+#define AR_PHY_RX_OCGAIN_2 AR_AGC1_BASE + 0x200 ++#define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4) ++#define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18) ++#define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c) ++#define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20) ++#define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180) ++#define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184) ++#define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200) + +/* + * AGC 1 Field Definitions @@ -19543,31 +19595,31 @@ + */ +#define AR_SM1_BASE 0xb200 + -+#define AR_PHY_SWITCH_CHAIN_1 AR_SM1_BASE + 0x84 -+#define AR_PHY_FCAL_2_1 AR_SM1_BASE + 0xd0 -+#define AR_PHY_DFT_TONE_CTL_1 AR_SM1_BASE + 0xd4 -+#define AR_PHY_CL_TAB_1 AR_SM1_BASE + 0x100 -+#define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_BASE + 0x180 -+#define AR_PHY_TPC_4_B1 AR_SM1_BASE + 0x204 -+#define AR_PHY_TPC_5_B1 AR_SM1_BASE + 0x208 -+#define AR_PHY_TPC_6_B1 AR_SM1_BASE + 0x20c -+#define AR_PHY_TPC_11_B1 AR_SM1_BASE + 0x220 -+#define AR_PHY_PDADC_TAB_1 AR_SM1_BASE + 0x240 -+#define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_BASE + 0x48c -+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_BASE + 0x450 ++#define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84) ++#define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0) ++#define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4) ++#define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100) ++#define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180) ++#define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204) ++#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) ++#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) ++#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) ++#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240) ++#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) ++#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450) + +/* + * Channel 2 Register Map + */ +#define AR_CHAN2_BASE 0xb800 + -+#define AR_PHY_EXT_CCA_2 AR_CHAN2_BASE + 0x30 -+#define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_BASE + 0xd0 -+#define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_BASE + 0xd4 ++#define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30) ++#define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0) ++#define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4) + -+#define AR_PHY_SPUR_REPORT_2 AR_CHAN2_BASE + 0xa8 -+#define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_BASE + 0x300 -+#define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_BASE + 0xdc ++#define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8) ++#define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300) ++#define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc) + +/* + * Channel 2 Field Definitions @@ -19579,11 +19631,11 @@ + */ +#define AR_AGC2_BASE 0xbe00 + -+#define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_BASE + 0x4 -+#define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_BASE + 0x18 -+#define AR_PHY_CCA_2 AR_AGC2_BASE + 0x1c -+#define AR_PHY_CCA_CTRL_2 AR_AGC2_BASE + 0x20 -+#define AR_PHY_RSSI_2 AR_AGC2_BASE + 0x180 ++#define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4) ++#define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18) ++#define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c) ++#define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20) ++#define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180) + +/* + * AGC 2 Field Definitions @@ -19596,18 +19648,18 @@ + */ +#define AR_SM2_BASE 0xc200 + -+#define AR_PHY_SWITCH_CHAIN_2 AR_SM2_BASE + 0x84 -+#define AR_PHY_FCAL_2_2 AR_SM2_BASE + 0xd0 -+#define AR_PHY_DFT_TONE_CTL_2 AR_SM2_BASE + 0xd4 -+#define AR_PHY_CL_TAB_2 AR_SM2_BASE + 0x100 -+#define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_BASE + 0x180 -+#define AR_PHY_TPC_4_B2 AR_SM2_BASE + 0x204 -+#define AR_PHY_TPC_5_B2 AR_SM2_BASE + 0x208 -+#define AR_PHY_TPC_6_B2 AR_SM2_BASE + 0x20c -+#define AR_PHY_TPC_11_B2 AR_SM2_BASE + 0x220 -+#define AR_PHY_PDADC_TAB_2 AR_SM2_BASE + 0x240 -+#define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_BASE + 0x48c -+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_BASE + 0x450 ++#define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84) ++#define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0) ++#define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4) ++#define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100) ++#define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180) ++#define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204) ++#define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208) ++#define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c) ++#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220) ++#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240) ++#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c) ++#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450) + +#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 + @@ -19616,7 +19668,7 @@ + */ +#define AR_AGC3_BASE 0xce00 + -+#define AR_PHY_RSSI_3 AR_AGC3_BASE + 0x180 ++#define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180) + +/* + * Misc helper defines @@ -21245,7 +21297,7 @@ return pBase->regDmn[0]; --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h -@@ -0,0 +1,279 @@ +@@ -0,0 +1,280 @@ +/* + * Copyright (c) 2010 Atheros Communications Inc. + * @@ -21444,7 +21496,8 @@ + return ath9k_hw_private_ops(ah)->olc_init(ah); +} + -+static inline void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) ++static inline void ath9k_hw_set_rfmode(struct ath_hw *ah, ++ struct ath9k_channel *chan) +{ + return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan); +} @@ -21489,7 +21542,7 @@ +} + +static inline bool ath9k_hw_ani_control(struct ath_hw *ah, -+ enum ath9k_ani_cmd cmd, int param) ++ enum ath9k_ani_cmd cmd, int param) +{ + return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param); +} @@ -21534,13 +21587,14 @@ * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above -@@ -19,15 +19,14 @@ +@@ -19,15 +19,15 @@ #include <asm/unaligned.h> #include "hw.h" +#include "hw-ops.h" #include "rc.h" -#include "initvals.h" ++#include "ar9003_mac.h" #define ATH9K_CLOCK_RATE_CCK 22 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 @@ -21551,7 +21605,7 @@ MODULE_AUTHOR("Atheros Communications"); MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); -@@ -46,6 +45,37 @@ static void __exit ath9k_exit(void) +@@ -46,6 +46,39 @@ static void __exit ath9k_exit(void) } module_exit(ath9k_exit); @@ -21569,7 +21623,9 @@ + +static bool ath9k_hw_macversion_supported(struct ath_hw *ah) +{ -+ return ath9k_hw_private_ops(ah)->macversion_supported(ah->hw_version.macVersion); ++ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); ++ ++ return priv_ops->macversion_supported(ah->hw_version.macVersion); +} + +static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, @@ -21589,7 +21645,7 @@ /********************/ /* Helper Functions */ /********************/ -@@ -233,21 +263,6 @@ static void ath9k_hw_read_revisions(stru +@@ -233,21 +266,6 @@ static void ath9k_hw_read_revisions(stru } } @@ -21611,7 +21667,7 @@ /************************************/ /* HW Attach, Detach, Init Routines */ /************************************/ -@@ -270,18 +285,25 @@ static void ath9k_hw_disablepcie(struct +@@ -270,18 +288,25 @@ static void ath9k_hw_disablepcie(struct REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); } @@ -21628,19 +21684,34 @@ 0x99999999 }; - int i, j; + int i, j, loop_max; -+ + +- for (i = 0; i < 2; i++) { + if (!AR_SREV_9300_20_OR_LATER(ah)) { + loop_max = 2; + regAddr[1] = AR_PHY_BASE + (8 << 2); + } else + loop_max = 1; - -- for (i = 0; i < 2; i++) { ++ + for (i = 0; i < loop_max; i++) { u32 addr = regAddr[i]; u32 wrData, rdData; -@@ -369,7 +391,6 @@ static void ath9k_hw_init_config(struct +@@ -336,7 +361,13 @@ static void ath9k_hw_init_config(struct + ah->config.ofdm_trig_high = 500; + ah->config.cck_trig_high = 200; + ah->config.cck_trig_low = 100; +- ah->config.enable_ani = 1; ++ ++ /* ++ * For now ANI is disabled for AR9003, it is still ++ * being tested. ++ */ ++ if (!AR_SREV_9300_20_OR_LATER(ah)) ++ ah->config.enable_ani = 1; + + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { + ah->config.spurchans[i][0] = AR_NO_SPUR; +@@ -369,7 +400,6 @@ static void ath9k_hw_init_config(struct if (num_possible_cpus() > 1) ah->config.serialize_regmode = SER_REG_MODE_AUTO; } @@ -21648,7 +21719,7 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah) { -@@ -383,8 +404,6 @@ static void ath9k_hw_init_defaults(struc +@@ -383,8 +413,6 @@ static void ath9k_hw_init_defaults(struc ah->hw_version.subvendorid = 0; ah->ah_flags = 0; @@ -21657,7 +21728,7 @@ if (!AR_SREV_9100(ah)) ah->ah_flags = AH_USE_EEPROM; -@@ -397,44 +416,17 @@ static void ath9k_hw_init_defaults(struc +@@ -397,44 +425,17 @@ static void ath9k_hw_init_defaults(struc ah->power_mode = ATH9K_PM_UNDEFINED; } @@ -21704,7 +21775,7 @@ sum += eeval; common->macaddr[2 * i] = eeval >> 8; common->macaddr[2 * i + 1] = eeval & 0xff; -@@ -445,54 +437,6 @@ static int ath9k_hw_init_macaddr(struct +@@ -445,54 +446,6 @@ static int ath9k_hw_init_macaddr(struct return 0; } @@ -21759,7 +21830,7 @@ static int ath9k_hw_post_init(struct ath_hw *ah) { int ecode; -@@ -502,9 +446,11 @@ static int ath9k_hw_post_init(struct ath +@@ -502,9 +455,11 @@ static int ath9k_hw_post_init(struct ath return -ENODEV; } @@ -21774,7 +21845,7 @@ ecode = ath9k_hw_eeprom_init(ah); if (ecode != 0) -@@ -515,14 +461,12 @@ static int ath9k_hw_post_init(struct ath +@@ -515,14 +470,12 @@ static int ath9k_hw_post_init(struct ath ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); @@ -21795,7 +21866,7 @@ } if (!AR_SREV_9100(ah)) { -@@ -533,344 +477,22 @@ static int ath9k_hw_post_init(struct ath +@@ -533,344 +486,22 @@ static int ath9k_hw_post_init(struct ath return 0; } @@ -22149,7 +22220,7 @@ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { ath_print(common, ATH_DBG_FATAL, -@@ -878,6 +500,11 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -878,6 +509,11 @@ int ath9k_hw_init(struct ath_hw *ah) return -EIO; } @@ -22161,7 +22232,7 @@ if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); return -EIO; -@@ -902,7 +529,7 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -902,7 +538,7 @@ int ath9k_hw_init(struct ath_hw *ah) else ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; @@ -22170,7 +22241,7 @@ ath_print(common, ATH_DBG_FATAL, "Mac Chip Rev 0x%02x.%x is not supported by " "this driver\n", ah->hw_version.macVersion, -@@ -910,28 +537,19 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -910,28 +546,15 @@ int ath9k_hw_init(struct ath_hw *ah) return -EOPNOTSUPP; } @@ -22190,7 +22261,7 @@ ah->ani_function = ATH9K_ANI_ALL; - if (AR_SREV_9280_10_OR_LATER(ah)) { -+ if (AR_SREV_9280_10_OR_LATER(ah)) ++ if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; - ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel; - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate; @@ -22198,14 +22269,10 @@ - ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel; - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate; - } -+ -+ /* this is still being tested */ -+ if (AR_SREV_9300_20_OR_LATER(ah)) -+ ah->ani_function = 0; ath9k_hw_init_mode_regs(ah); -@@ -940,15 +558,8 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -940,15 +563,8 @@ int ath9k_hw_init(struct ath_hw *ah) else ath9k_hw_disablepcie(ah); @@ -22223,7 +22290,7 @@ r = ath9k_hw_post_init(ah); if (r) -@@ -959,8 +570,6 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -959,8 +575,6 @@ int ath9k_hw_init(struct ath_hw *ah) if (r) return r; @@ -22232,7 +22299,7 @@ r = ath9k_hw_init_macaddr(ah); if (r) { ath_print(common, ATH_DBG_FATAL, -@@ -973,6 +582,9 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -973,6 +587,9 @@ int ath9k_hw_init(struct ath_hw *ah) else ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); @@ -22242,7 +22309,7 @@ ath9k_init_nfcal_hist_buffer(ah); common->state = ATH_HW_INITIALIZED; -@@ -980,21 +592,45 @@ int ath9k_hw_init(struct ath_hw *ah) +@@ -980,21 +597,45 @@ int ath9k_hw_init(struct ath_hw *ah) return 0; } @@ -22298,13 +22365,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah) { -@@ -1016,64 +652,8 @@ static void ath9k_hw_init_qos(struct ath +@@ -1016,64 +657,8 @@ static void ath9k_hw_init_qos(struct ath static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan) { - u32 pll; -+ u32 pll = ath9k_hw_compute_pll_control(ah, chan); - +- - if (AR_SREV_9100(ah)) { - if (chan && IS_CHAN_5GHZ(chan)) - pll = 0x1450; @@ -22333,7 +22399,8 @@ - } else { - pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); - } -- ++ u32 pll = ath9k_hw_compute_pll_control(ah, chan); + - } else if (AR_SREV_9160_10_OR_LATER(ah)) { - - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); @@ -22364,7 +22431,7 @@ REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); /* Switch the core clock for ar9271 to 117Mhz */ -@@ -1087,43 +667,6 @@ static void ath9k_hw_init_pll(struct ath +@@ -1087,43 +672,6 @@ static void ath9k_hw_init_pll(struct ath REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); } @@ -22408,7 +22475,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, enum nl80211_iftype opmode) { -@@ -1133,12 +676,24 @@ static void ath9k_hw_init_interrupt_mask +@@ -1133,12 +681,24 @@ static void ath9k_hw_init_interrupt_mask AR_IMR_RXORN | AR_IMR_BCNMISC; @@ -22438,7 +22505,7 @@ if (opmode == NL80211_IFTYPE_AP) imr_reg |= AR_IMR_MIB; -@@ -1152,6 +707,13 @@ static void ath9k_hw_init_interrupt_mask +@@ -1152,6 +712,13 @@ static void ath9k_hw_init_interrupt_mask REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); } @@ -22452,10 +22519,15 @@ } static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) -@@ -1220,305 +782,67 @@ void ath9k_hw_init_global_settings(struc - * timeout issues in other cases as well. - */ - if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) +@@ -1215,310 +782,72 @@ void ath9k_hw_init_global_settings(struc + /* + * Workaround for early ACK timeouts, add an offset to match the + * initval's 64us ack timeout value. +- * This was initially only meant to work around an issue with delayed +- * BA frames in some implementations, but it has been found to fix ACK +- * timeout issues in other cases as well. +- */ +- if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) - acktimeout += 64 - sifstime - ah->slottime; - - ath9k_hw_setslottime(ah, slottime); @@ -22667,26 +22739,15 @@ - u32 val = INI_RA(&ah->iniCommon, i, 1); - - REG_WRITE(ah, reg, val); -+ acktimeout += 64 - sifstime - ah->slottime; - +- - if (reg >= 0x7800 && reg < 0x78a0 - && ah->config.analog_shiftreg) { - udelay(100); - } -+ ath9k_hw_setslottime(ah, slottime); -+ ath9k_hw_set_ack_timeout(ah, acktimeout); -+ ath9k_hw_set_cts_timeout(ah, acktimeout); -+ if (ah->globaltxtimeout != (u32) -1) -+ ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); -+} -+EXPORT_SYMBOL(ath9k_hw_init_global_settings); - +- - DO_DELAY(regWrites); - } -+void ath9k_hw_deinit(struct ath_hw *ah) -+{ -+ struct ath_common *common = ath9k_hw_common(ah); - +- - if (AR_SREV_9271(ah)) { - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1) - REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271, @@ -22695,32 +22756,38 @@ - REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, - modesIndex, regWrites); - } -+ if (common->state < ATH_HW_INITIALIZED) -+ goto free_hw; - +- - ath9k_hw_write_regs(ah, freqIndex, regWrites); -+ if (!AR_SREV_9100(ah)) -+ ath9k_hw_ani_disable(ah); ++ * This was initially only meant to work around an issue with delayed ++ * BA frames in some implementations, but it has been found to fix ACK ++ * timeout issues in other cases as well. ++ */ ++ if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) ++ acktimeout += 64 - sifstime - ah->slottime; - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { - REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, - regWrites); - } -+ ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); ++ ath9k_hw_setslottime(ah, slottime); ++ ath9k_hw_set_ack_timeout(ah, acktimeout); ++ ath9k_hw_set_cts_timeout(ah, acktimeout); ++ if (ah->globaltxtimeout != (u32) -1) ++ ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); ++} ++EXPORT_SYMBOL(ath9k_hw_init_global_settings); - ath9k_hw_override_ini(ah, chan); - ath9k_hw_set_regs(ah, chan); - ath9k_hw_init_chain_masks(ah); -+free_hw: -+ ath9k_hw_rf_free_ext_banks(ah); -+} -+EXPORT_SYMBOL(ath9k_hw_deinit); ++void ath9k_hw_deinit(struct ath_hw *ah) ++{ ++ struct ath_common *common = ath9k_hw_common(ah); - if (OLC_FOR_AR9280_20_LATER) - ath9k_olc_init(ah); -+/*******/ -+/* INI */ -+/*******/ ++ if (common->state < ATH_HW_INITIALIZED) ++ goto free_hw; - /* Set TX power */ - ah->eep_ops->set_txpower(ah, chan, @@ -22729,9 +22796,8 @@ - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) regulatory->power_limit)); -+u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) -+{ -+ u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); ++ if (!AR_SREV_9100(ah)) ++ ath9k_hw_ani_disable(ah); - /* Write analog registers */ - if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { @@ -22739,23 +22805,24 @@ - "ar5416SetRfRegs failed\n"); - return -EIO; - } -+ if (IS_CHAN_B(chan)) -+ ctl |= CTL_11B; -+ else if (IS_CHAN_G(chan)) -+ ctl |= CTL_11G; -+ else -+ ctl |= CTL_11A; ++ ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); - return 0; -+ return ctl; ++free_hw: ++ ath9k_hw_rf_free_ext_banks(ah); } ++EXPORT_SYMBOL(ath9k_hw_deinit); - /****************************************/ - /* Reset and Channel Switching Routines */ - /****************************************/ +-/****************************************/ +-/* Reset and Channel Switching Routines */ +-/****************************************/ ++/*******/ ++/* INI */ ++/*******/ -static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) --{ ++u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) + { - u32 rfMode = 0; - - if (chan == NULL) @@ -22767,18 +22834,29 @@ - if (!AR_SREV_9280_10_OR_LATER(ah)) - rfMode |= (IS_CHAN_5GHZ(chan)) ? - AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; -- ++ u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); + - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) - rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); -- ++ if (IS_CHAN_B(chan)) ++ ctl |= CTL_11B; ++ else if (IS_CHAN_G(chan)) ++ ctl |= CTL_11G; ++ else ++ ctl |= CTL_11A; + - REG_WRITE(ah, AR_PHY_MODE, rfMode); --} -- ++ return ctl; + } + -static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) -{ - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); -} -- ++/****************************************/ ++/* Reset and Channel Switching Routines */ ++/****************************************/ + static inline void ath9k_hw_set_dma(struct ath_hw *ah) { + struct ath_common *common = ath9k_hw_common(ah); @@ -22796,7 +22874,7 @@ /* * let mac dma reads be in 128 byte chunks -@@ -1531,7 +855,8 @@ static inline void ath9k_hw_set_dma(stru +@@ -1531,7 +860,8 @@ static inline void ath9k_hw_set_dma(stru * The initial value depends on whether aggregation is enabled, and is * adjusted whenever underruns are detected. */ @@ -22806,7 +22884,7 @@ /* * let mac dma writes be in 128 byte chunks -@@ -1544,6 +869,14 @@ static inline void ath9k_hw_set_dma(stru +@@ -1544,6 +874,14 @@ static inline void ath9k_hw_set_dma(stru */ REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); @@ -22821,7 +22899,7 @@ /* * reduce the number of usable entries in PCU TXBUF to avoid * wrap around issues. -@@ -1559,6 +892,9 @@ static inline void ath9k_hw_set_dma(stru +@@ -1559,6 +897,9 @@ static inline void ath9k_hw_set_dma(stru REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); } @@ -22831,7 +22909,7 @@ } static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) -@@ -1586,10 +922,8 @@ static void ath9k_hw_set_operating_mode( +@@ -1586,10 +927,8 @@ static void ath9k_hw_set_operating_mode( } } @@ -22844,7 +22922,7 @@ { u32 coef_exp, coef_man; -@@ -1605,40 +939,6 @@ static inline void ath9k_hw_get_delta_sl +@@ -1605,40 +944,6 @@ static inline void ath9k_hw_get_delta_sl *coef_exponent = coef_exp - 16; } @@ -22885,7 +22963,7 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) { u32 rst_flags; -@@ -1663,11 +963,16 @@ static bool ath9k_hw_set_reset(struct at +@@ -1663,11 +968,16 @@ static bool ath9k_hw_set_reset(struct at if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { @@ -22905,7 +22983,7 @@ rst_flags = AR_RTC_RC_MAC_WARM; if (type == ATH9K_RESET_COLD) -@@ -1698,13 +1003,15 @@ static bool ath9k_hw_set_reset_power_on( +@@ -1698,13 +1008,15 @@ static bool ath9k_hw_set_reset_power_on( REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); @@ -22924,7 +23002,7 @@ REG_WRITE(ah, AR_RC, 0); REG_WRITE(ah, AR_RTC_RESET, 1); -@@ -1740,34 +1047,6 @@ static bool ath9k_hw_set_reset_reg(struc +@@ -1740,34 +1052,6 @@ static bool ath9k_hw_set_reset_reg(struc } } @@ -22959,7 +23037,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan) { -@@ -1793,7 +1072,7 @@ static bool ath9k_hw_channel_change(stru +@@ -1793,7 +1077,7 @@ static bool ath9k_hw_channel_change(stru struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); struct ath_common *common = ath9k_hw_common(ah); struct ieee80211_channel *channel = chan->chan; @@ -22968,7 +23046,7 @@ int r; for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { -@@ -1805,17 +1084,15 @@ static bool ath9k_hw_channel_change(stru +@@ -1805,17 +1089,15 @@ static bool ath9k_hw_channel_change(stru } } @@ -22989,7 +23067,7 @@ if (r) { ath_print(common, ATH_DBG_FATAL, "Failed to set channel\n"); -@@ -1829,20 +1106,12 @@ static bool ath9k_hw_channel_change(stru +@@ -1829,20 +1111,12 @@ static bool ath9k_hw_channel_change(stru min((u32) MAX_RATE_POWER, (u32) regulatory->power_limit)); @@ -23012,7 +23090,7 @@ if (!chan->oneTimeCalsDone) chan->oneTimeCalsDone = true; -@@ -1850,18 +1119,6 @@ static bool ath9k_hw_channel_change(stru +@@ -1850,18 +1124,6 @@ static bool ath9k_hw_channel_change(stru return true; } @@ -23031,7 +23109,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, bool bChannelChange) { -@@ -1871,11 +1128,18 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -1871,11 +1133,18 @@ int ath9k_hw_reset(struct ath_hw *ah, st u32 saveDefAntenna; u32 macStaId1; u64 tsf = 0; @@ -23051,7 +23129,7 @@ if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return -EIO; -@@ -1943,16 +1207,6 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -1943,16 +1212,6 @@ int ath9k_hw_reset(struct ath_hw *ah, st if (AR_SREV_9280_10_OR_LATER(ah)) REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); @@ -23068,7 +23146,7 @@ r = ath9k_hw_process_ini(ah, chan); if (r) return r; -@@ -1977,7 +1231,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -1977,7 +1236,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) ath9k_hw_set_delta_slope(ah, chan); @@ -23077,7 +23155,7 @@ ah->eep_ops->set_board_values(ah, chan); REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); -@@ -1999,7 +1253,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -1999,7 +1258,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); @@ -23086,7 +23164,7 @@ if (r) return r; -@@ -2018,25 +1272,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -2018,25 +1277,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st ath9k_hw_init_global_settings(ah); @@ -23115,7 +23193,7 @@ } REG_WRITE(ah, AR_STA_ID1, -@@ -2051,17 +1289,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -2051,17 +1294,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); } @@ -23139,7 +23217,7 @@ REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); /* -@@ -2093,6 +1331,11 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -2093,6 +1336,11 @@ int ath9k_hw_reset(struct ath_hw *ah, st if (ah->btcoex_hw.enabled) ath9k_hw_btcoex_enable(ah); @@ -23151,7 +23229,7 @@ return 0; } EXPORT_SYMBOL(ath9k_hw_reset); -@@ -2379,21 +1622,32 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid); +@@ -2379,21 +1627,35 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid); /* Power Management (Chipset) */ /******************************/ @@ -23163,7 +23241,10 @@ { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { -+ /* Clear the RTC force wake bit to allow the mac to go to sleep */ ++ /* ++ * Clear the RTC force wake bit to allow the ++ * mac to go to sleep. ++ */ REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); - if (!AR_SREV_9100(ah)) @@ -23185,7 +23266,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); -@@ -2401,9 +1655,14 @@ static void ath9k_set_power_network_slee +@@ -2401,9 +1663,14 @@ static void ath9k_set_power_network_slee struct ath9k_hw_capabilities *pCap = &ah->caps; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { @@ -23200,7 +23281,7 @@ REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); } -@@ -2422,7 +1681,8 @@ static bool ath9k_hw_set_power_awake(str +@@ -2422,7 +1689,8 @@ static bool ath9k_hw_set_power_awake(str ATH9K_RESET_POWER_ON) != true) { return false; } @@ -23210,7 +23291,7 @@ } if (AR_SREV_9100(ah)) REG_SET_BIT(ah, AR_RTC_RESET, -@@ -2492,420 +1752,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah +@@ -2492,420 +1760,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah } EXPORT_SYMBOL(ath9k_hw_setpower); @@ -23631,7 +23712,7 @@ /*******************/ /* Beacon Handling */ /*******************/ -@@ -3241,6 +2087,20 @@ int ath9k_hw_fill_cap_info(struct ath_hw +@@ -3241,6 +2095,20 @@ int ath9k_hw_fill_cap_info(struct ath_hw btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; } @@ -23652,7 +23733,7 @@ return 0; } -@@ -3273,10 +2133,6 @@ bool ath9k_hw_getcapability(struct ath_h +@@ -3273,10 +2141,6 @@ bool ath9k_hw_getcapability(struct ath_h case ATH9K_CAP_TKIP_SPLIT: return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? false : true; @@ -23663,7 +23744,7 @@ case ATH9K_CAP_MCAST_KEYSRCH: switch (capability) { case 0: -@@ -3319,8 +2175,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability); +@@ -3319,8 +2183,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability); bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 setting, int *status) { @@ -23672,7 +23753,7 @@ switch (type) { case ATH9K_CAP_TKIP_MIC: if (setting) -@@ -3330,14 +2184,6 @@ bool ath9k_hw_setcapability(struct ath_h +@@ -3330,14 +2192,6 @@ bool ath9k_hw_setcapability(struct ath_h ah->sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; return true; @@ -23687,7 +23768,7 @@ case ATH9K_CAP_MCAST_KEYSRCH: if (setting) ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; -@@ -3405,7 +2251,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, +@@ -3405,7 +2259,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, if (gpio >= ah->caps.num_gpio_pins) return 0xffffffff; @@ -23698,7 +23779,7 @@ return MS_REG_READ(AR9271, gpio) != 0; else if (AR_SREV_9287_10_OR_LATER(ah)) return MS_REG_READ(AR9287, gpio) != 0; -@@ -3847,6 +2695,7 @@ static struct { +@@ -3847,6 +2703,7 @@ static struct { { AR_SREV_VERSION_9285, "9285" }, { AR_SREV_VERSION_9287, "9287" }, { AR_SREV_VERSION_9271, "9271" }, @@ -23715,15 +23796,7 @@ * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above -@@ -28,6 +28,7 @@ - #include "reg.h" - #include "phy.h" - #include "btcoex.h" -+#include "ar9003_mac.h" - - #include "../regd.h" - #include "../debug.h" -@@ -41,6 +42,9 @@ +@@ -41,6 +41,9 @@ #define AR9280_DEVID_PCIE 0x002a #define AR9285_DEVID_PCIE 0x002b #define AR2427_DEVID_PCIE 0x002c @@ -23733,7 +23806,7 @@ #define AR5416_AR9100_DEVID 0x000b -@@ -48,9 +52,6 @@ +@@ -48,9 +51,6 @@ #define AR_SUBVENDOR_ID_NEW_A 0x7065 #define AR5416_MAGIC 0x19641014 @@ -23743,7 +23816,7 @@ #define AR9280_COEX2WIRE_SUBSYSID 0x309b #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab -@@ -75,6 +76,8 @@ +@@ -75,6 +75,8 @@ #define REG_RMW_FIELD(_a, _r, _f, _v) \ REG_WRITE(_a, _r, \ (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) @@ -23752,7 +23825,7 @@ #define REG_SET_BIT(_a, _r, _f) \ REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) #define REG_CLR_BIT(_a, _r, _f) \ -@@ -135,6 +138,16 @@ +@@ -135,6 +137,16 @@ #define TU_TO_USEC(_tu) ((_tu) << 10) @@ -23769,7 +23842,7 @@ enum wireless_mode { ATH9K_MODE_11A = 0, ATH9K_MODE_11G, -@@ -165,13 +178,15 @@ enum ath9k_hw_caps { +@@ -165,13 +177,15 @@ enum ath9k_hw_caps { ATH9K_HW_CAP_ENHANCEDPM = BIT(14), ATH9K_HW_CAP_AUTOSLEEP = BIT(15), ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), @@ -23786,7 +23859,7 @@ ATH9K_CAP_TXPOW, ATH9K_CAP_MCAST_KEYSRCH, ATH9K_CAP_DS -@@ -192,6 +207,11 @@ struct ath9k_hw_capabilities { +@@ -192,6 +206,11 @@ struct ath9k_hw_capabilities { u8 num_gpio_pins; u8 num_antcfg_2ghz; u8 num_antcfg_5ghz; @@ -23798,7 +23871,7 @@ }; struct ath9k_ops_config { -@@ -212,6 +232,7 @@ struct ath9k_ops_config { +@@ -212,6 +231,7 @@ struct ath9k_ops_config { u32 enable_ani; int serialize_regmode; bool rx_intr_mitigation; @@ -23806,7 +23879,7 @@ #define SPUR_DISABLE 0 #define SPUR_ENABLE_IOCTL 1 #define SPUR_ENABLE_EEPROM 2 -@@ -231,6 +252,8 @@ struct ath9k_ops_config { +@@ -231,6 +251,8 @@ struct ath9k_ops_config { enum ath9k_int { ATH9K_INT_RX = 0x00000001, ATH9K_INT_RXDESC = 0x00000002, @@ -23815,7 +23888,20 @@ ATH9K_INT_RXNOFRM = 0x00000008, ATH9K_INT_RXEOL = 0x00000010, ATH9K_INT_RXORN = 0x00000020, -@@ -440,6 +463,124 @@ struct ath_gen_timer_table { +@@ -363,6 +385,12 @@ enum ser_reg_mode { + SER_REG_MODE_AUTO = 2, + }; + ++enum ath9k_rx_qtype { ++ ATH9K_RX_QUEUE_HP, ++ ATH9K_RX_QUEUE_LP, ++ ATH9K_RX_QUEUE_MAX, ++}; ++ + struct ath9k_beacon_state { + u32 bs_nexttbtt; + u32 bs_nextdtim; +@@ -440,6 +468,124 @@ struct ath_gen_timer_table { } timer_mask; }; @@ -23940,7 +24026,7 @@ struct ath_hw { struct ieee80211_hw *hw; struct ath_common common; -@@ -453,14 +594,18 @@ struct ath_hw { +@@ -453,14 +599,18 @@ struct ath_hw { struct ar5416_eeprom_def def; struct ar5416_eeprom_4k map4k; struct ar9287_eeprom map9287; @@ -23960,7 +24046,7 @@ u16 rfsilent; u32 rfkill_gpio; u32 rfkill_polarity; -@@ -493,6 +638,7 @@ struct ath_hw { +@@ -493,6 +643,7 @@ struct ath_hw { struct ath9k_cal_list adcgain_caldata; struct ath9k_cal_list adcdc_calinitdata; struct ath9k_cal_list adcdc_caldata; @@ -23968,7 +24054,7 @@ struct ath9k_cal_list *cal_list; struct ath9k_cal_list *cal_list_last; struct ath9k_cal_list *cal_list_curr; -@@ -533,12 +679,10 @@ struct ath_hw { +@@ -533,12 +684,10 @@ struct ath_hw { DONT_USE_32KHZ, } enable_32kHz_clock; @@ -23985,7 +24071,7 @@ /* Used to program the radio on non single-chip devices */ u32 *analogBank0Data; -@@ -592,6 +736,7 @@ struct ath_hw { +@@ -592,6 +741,7 @@ struct ath_hw { struct ar5416IniArray iniBank7; struct ar5416IniArray iniAddac; struct ar5416IniArray iniPcieSerdes; @@ -23993,7 +24079,7 @@ struct ar5416IniArray iniModesAdditional; struct ar5416IniArray iniModesRxGain; struct ar5416IniArray iniModesTxGain; -@@ -604,9 +749,21 @@ struct ath_hw { +@@ -604,9 +754,21 @@ struct ath_hw { struct ar5416IniArray iniModes_high_power_tx_gain_9271; struct ar5416IniArray iniModes_normal_power_tx_gain_9271; @@ -24015,7 +24101,7 @@ }; static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) -@@ -619,6 +776,16 @@ static inline struct ath_regulatory *ath +@@ -619,6 +781,16 @@ static inline struct ath_regulatory *ath return &(ath9k_hw_common(ah)->regulatory); } @@ -24032,7 +24118,7 @@ /* Initialization, Detach, Reset */ const char *ath9k_hw_probe(u16 vendorid, u16 devid); void ath9k_hw_deinit(struct ath_hw *ah); -@@ -630,6 +797,7 @@ bool ath9k_hw_getcapability(struct ath_h +@@ -630,6 +802,7 @@ bool ath9k_hw_getcapability(struct ath_h u32 capability, u32 *result); bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 setting, int *status); @@ -24040,7 +24126,7 @@ /* Key Cache Management */ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); -@@ -681,13 +849,6 @@ void ath9k_hw_set_sta_beacon_timers(stru +@@ -681,13 +854,6 @@ void ath9k_hw_set_sta_beacon_timers(stru bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); @@ -24054,7 +24140,7 @@ /* Generic hw timer primitives */ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, void (*trigger)(void *), -@@ -709,6 +870,36 @@ void ath9k_hw_name(struct ath_hw *ah, ch +@@ -709,6 +875,36 @@ void ath9k_hw_name(struct ath_hw *ah, ch /* HTC */ void ath9k_hw_htc_resetinit(struct ath_hw *ah); @@ -31737,7 +31823,30 @@ if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) ah->txok_interrupt_mask |= 1 << q; else -@@ -999,12 +745,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah +@@ -940,22 +686,6 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a + } + EXPORT_SYMBOL(ath9k_hw_rxprocdesc); + +-void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, +- u32 size, u32 flags) +-{ +- struct ar5416_desc *ads = AR5416DESC(ds); +- struct ath9k_hw_capabilities *pCap = &ah->caps; +- +- ads->ds_ctl1 = size & AR_BufLen; +- if (flags & ATH9K_RXDESC_INTREQ) +- ads->ds_ctl1 |= AR_RxIntrReq; +- +- ads->ds_rxstatus8 &= ~AR_RxDone; +- if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) +- memset(&(ads->u), 0, sizeof(ads->u)); +-} +-EXPORT_SYMBOL(ath9k_hw_setuprxdesc); +- + /* + * This can stop or re-enables RX. + * +@@ -999,12 +729,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah } EXPORT_SYMBOL(ath9k_hw_putrxbuf); @@ -31750,7 +31859,7 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah) { ath9k_enable_mib_counters(ah); -@@ -1023,6 +763,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw +@@ -1023,6 +747,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw } EXPORT_SYMBOL(ath9k_hw_stoppcurecv); @@ -31765,7 +31874,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah) { #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ -@@ -1068,3 +816,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw +@@ -1068,3 +800,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); } EXPORT_SYMBOL(ath9k_hw_beaconq_setup); @@ -31947,17 +32056,15 @@ #define ATH9K_RXDESC_INTREQ 0x0020 -@@ -353,7 +358,8 @@ struct ar5416_desc { +@@ -353,7 +358,6 @@ struct ar5416_desc { #define AR_DestIdxValid 0x40000000 #define AR_CTSEnable 0x80000000 -#define AR_BufLen 0x00000fff -+#define AR_BufLen AR_SREV_9300_20_OR_LATER(ah) ? 0x0fff0000 : \ -+ 0x00000fff #define AR_TxMore 0x00001000 #define AR_DestIdx 0x000fe000 #define AR_DestIdx_S 13 -@@ -410,6 +416,7 @@ struct ar5416_desc { +@@ -410,6 +414,7 @@ struct ar5416_desc { #define AR_EncrType 0x0c000000 #define AR_EncrType_S 26 #define AR_TxCtlRsvd61 0xf0000000 @@ -31965,7 +32072,7 @@ #define AR_2040_0 0x00000001 #define AR_GI0 0x00000002 -@@ -493,7 +500,6 @@ struct ar5416_desc { +@@ -493,7 +498,6 @@ struct ar5416_desc { #define AR_RxCTLRsvd00 0xffffffff @@ -31973,7 +32080,7 @@ #define AR_RxCtlRsvd00 0x00001000 #define AR_RxIntrReq 0x00002000 #define AR_RxCtlRsvd01 0xffffc000 -@@ -686,34 +692,10 @@ struct ath9k_channel; +@@ -686,34 +690,10 @@ struct ath9k_channel; u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); void ath9k_hw_txstart(struct ath_hw *ah, u32 q); @@ -32009,7 +32116,7 @@ void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo); -@@ -729,10 +711,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw +@@ -729,10 +709,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw u32 size, u32 flags); bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); @@ -32124,6 +32231,16 @@ if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) ah->imask |= ATH9K_INT_GTT; +@@ -1436,7 +1468,8 @@ static int ath9k_add_interface(struct ie + if ((vif->type == NL80211_IFTYPE_STATION) || + (vif->type == NL80211_IFTYPE_ADHOC) || + (vif->type == NL80211_IFTYPE_MESH_POINT)) { +- ah->imask |= ATH9K_INT_MIB; ++ if (ah->config.enable_ani) ++ ah->imask |= ATH9K_INT_MIB; + ah->imask |= ATH9K_INT_TSFOOR; + } + --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i @@ -33753,16 +33870,17 @@ * probes don't enable rts */ --- a/drivers/net/wireless/ath/ath9k/recv.c +++ b/drivers/net/wireless/ath/ath9k/recv.c -@@ -16,6 +16,8 @@ +@@ -15,6 +15,9 @@ + */ #include "ath9k.h" - -+#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) ++#include "ar9003_mac.h" + ++#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) + static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, struct ieee80211_hdr *hdr) - { -@@ -115,56 +117,246 @@ static void ath_opmode_init(struct ath_s +@@ -115,56 +118,246 @@ static void ath_opmode_init(struct ath_s ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); } @@ -34036,7 +34154,7 @@ err: if (error) -@@ -180,17 +372,23 @@ void ath_rx_cleanup(struct ath_softc *sc +@@ -180,17 +373,23 @@ void ath_rx_cleanup(struct ath_softc *sc struct sk_buff *skb; struct ath_buf *bf; @@ -34069,7 +34187,7 @@ } /* -@@ -273,6 +471,11 @@ int ath_startrecv(struct ath_softc *sc) +@@ -273,6 +472,11 @@ int ath_startrecv(struct ath_softc *sc) struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf, *tbf; @@ -34081,17 +34199,16 @@ spin_lock_bh(&sc->rx.rxbuflock); if (list_empty(&sc->rx.rxbuf)) goto start_recv; -@@ -306,7 +509,12 @@ bool ath_stoprecv(struct ath_softc *sc) +@@ -306,7 +510,11 @@ bool ath_stoprecv(struct ath_softc *sc) ath9k_hw_stoppcurecv(ah); ath9k_hw_setrxfilter(ah, 0); stopped = ath9k_hw_stopdmarecv(ah); - sc->rx.rxlink = NULL; + -+ if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { ++ if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) + ath_edma_stop_recv(sc); -+ } else { ++ else + sc->rx.rxlink = NULL; -+ } return stopped; } @@ -34495,17 +34612,18 @@ #define AR_Q_TXE 0x0840 #define AR_Q_TXE_M 0x000003FF -@@ -461,6 +478,9 @@ +@@ -461,6 +478,10 @@ #define AR_Q_RDYTIMESHDN 0x0a40 #define AR_Q_RDYTIMESHDN_M 0x000003FF +/* MAC Descriptor CRC check */ +#define AR_Q_DESC_CRCCHK 0xa44 -+#define AR_Q_DESC_CRCCHK_EN 1 /* Enable CRC check on the descriptor fetched from host */ ++/* Enable CRC check on the descriptor fetched from host */ ++#define AR_Q_DESC_CRCCHK_EN 1 #define AR_NUM_DCU 10 #define AR_DCU_0 0x0001 -@@ -759,6 +779,8 @@ +@@ -759,6 +780,8 @@ #define AR_SREV_VERSION_9271 0x140 #define AR_SREV_REVISION_9271_10 0 #define AR_SREV_REVISION_9271_11 1 @@ -34514,7 +34632,7 @@ #define AR_SREV_5416(_ah) \ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ -@@ -844,6 +866,15 @@ +@@ -844,6 +867,15 @@ #define AR_SREV_9271_11(_ah) \ (AR_SREV_9271(_ah) && \ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) @@ -34530,7 +34648,7 @@ #define AR_SREV_9285E_20(_ah) \ (AR_SREV_9285_12_OR_LATER(_ah) && \ -@@ -945,6 +976,7 @@ enum { +@@ -945,6 +977,7 @@ enum { #define AR9285_NUM_GPIO 12 #define AR9287_NUM_GPIO 11 #define AR9271_NUM_GPIO 16 @@ -34538,7 +34656,7 @@ #define AR_GPIO_IN_OUT 0x4048 #define AR_GPIO_IN_VAL 0x0FFFC000 -@@ -957,19 +989,21 @@ enum { +@@ -957,19 +990,21 @@ enum { #define AR9287_GPIO_IN_VAL_S 11 #define AR9271_GPIO_IN_VAL 0xFFFF0000 #define AR9271_GPIO_IN_VAL_S 16 @@ -34564,7 +34682,7 @@ #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 -@@ -987,13 +1021,13 @@ enum { +@@ -987,13 +1022,13 @@ enum { #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 #define AR_GPIO_JTAG_DISABLE 0x00020000 @@ -34580,7 +34698,7 @@ #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f #define AR_GPIO_INPUT_MUX2_CLK25_S 0 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 -@@ -1001,13 +1035,13 @@ enum { +@@ -1001,13 +1036,13 @@ enum { #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 @@ -34599,7 +34717,7 @@ #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff #define AR_EEPROM_STATUS_DATA_VAL_S 0 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 -@@ -1015,13 +1049,24 @@ enum { +@@ -1015,13 +1050,24 @@ enum { #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 @@ -34627,7 +34745,7 @@ #define AR_RTC_9160_PLL_DIV 0x000003ff #define AR_RTC_9160_PLL_DIV_S 0 -@@ -1039,6 +1084,16 @@ enum { +@@ -1039,6 +1085,16 @@ enum { #define AR_RTC_RC_COLD_RESET 0x00000004 #define AR_RTC_RC_WARM_RESET 0x00000008 @@ -34644,7 +34762,7 @@ #define AR_RTC_PLL_CONTROL \ ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) -@@ -1069,6 +1124,7 @@ enum { +@@ -1069,6 +1125,7 @@ enum { #define AR_RTC_SLEEP_CLK \ ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) #define AR_RTC_FORCE_DERIVED_CLK 0x2 @@ -34652,7 +34770,7 @@ #define AR_RTC_FORCE_WAKE \ ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) -@@ -1533,7 +1589,7 @@ enum { +@@ -1533,7 +1590,7 @@ enum { #define AR_TSFOOR_THRESHOLD 0x813c #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF @@ -34661,7 +34779,7 @@ #define AR_PHY_ERR_3 0x8168 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF -@@ -1599,24 +1655,26 @@ enum { +@@ -1599,24 +1656,26 @@ enum { #define AR_FIRST_NDP_TIMER 7 #define AR_NDP2_PERIOD 0x81a0 #define AR_NDP2_TIMER_MODE 0x81c0 @@ -34706,7 +34824,7 @@ #define AR_TIMER_MODE 0x8240 #define AR_TBTT_TIMER_EN 0x00000001 -@@ -1730,4 +1788,32 @@ enum { +@@ -1730,4 +1789,32 @@ enum { #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ @@ -34741,7 +34859,15 @@ #endif --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c -@@ -91,7 +91,6 @@ static int ath_max_4ms_framelen[3][16] = +@@ -15,6 +15,7 @@ + */ + + #include "ath9k.h" ++#include "ar9003_mac.h" + + #define BITS_PER_BYTE 8 + #define OFDM_PLCP_BITS 22 +@@ -91,7 +92,6 @@ static int ath_max_4ms_framelen[3][16] = } }; @@ -34749,7 +34875,7 @@ /*********************/ /* Aggregation logic */ /*********************/ -@@ -279,7 +278,7 @@ static struct ath_buf* ath_clone_txbuf(s +@@ -279,7 +279,7 @@ static struct ath_buf* ath_clone_txbuf(s tbf->aphy = bf->aphy; tbf->bf_mpdu = bf->bf_mpdu; tbf->bf_buf_addr = bf->bf_buf_addr; @@ -34758,17 +34884,16 @@ tbf->bf_state = bf->bf_state; tbf->bf_dmacontext = bf->bf_dmacontext; -@@ -358,8 +357,7 @@ static void ath_tx_complete_aggr(struct - /* transmit completion */ +@@ -359,7 +359,7 @@ static void ath_tx_complete_aggr(struct acked_cnt++; } else { -- if (!(tid->state & AGGR_CLEANUP) && + if (!(tid->state & AGGR_CLEANUP) && - ts->ts_flags != ATH9K_TX_SW_ABORTED) { -+ if (!(tid->state & AGGR_CLEANUP) && !bf_last->bf_tx_aborted) { ++ !bf_last->bf_tx_aborted) { if (bf->bf_retries < ATH_MAX_SW_RETRIES) { ath_tx_set_retry(sc, txq, bf); txpending = 1; -@@ -378,7 +376,8 @@ static void ath_tx_complete_aggr(struct +@@ -378,7 +378,8 @@ static void ath_tx_complete_aggr(struct } } @@ -34778,7 +34903,7 @@ /* * Make sure the last desc is reclaimed if it * not a holding desc. -@@ -412,36 +411,38 @@ static void ath_tx_complete_aggr(struct +@@ -412,36 +413,43 @@ static void ath_tx_complete_aggr(struct !txfail, sendbar); } else { /* retry the un-acked ones */ @@ -34795,14 +34920,22 @@ - ath_tx_update_baw(sc, tid, - bf->bf_seqno); - spin_unlock_bh(&txq->axq_lock); +- +- bf->bf_state.bf_type |= BUF_XRETRY; +- ath_tx_rc_status(bf, ts, nbad, +- 0, false); +- ath_tx_complete_buf(sc, bf, txq, +- &bf_head, ts, 0, 0); +- break; + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { + if (bf->bf_next == NULL && bf_last->bf_stale) { + struct ath_buf *tbf; + + tbf = ath_clone_txbuf(sc, bf_last); + /* -+ * Update tx baw and complete the frame with -+ * failed status if we run out of tx buf ++ * Update tx baw and complete the ++ * frame with failed status if we ++ * run out of tx buf. + */ + if (!tbf) { + spin_lock_bh(&txq->axq_lock); @@ -34810,28 +34943,26 @@ + bf->bf_seqno); + spin_unlock_bh(&txq->axq_lock); + -+ bf->bf_state.bf_type |= BUF_XRETRY; ++ bf->bf_state.bf_type |= ++ BUF_XRETRY; + ath_tx_rc_status(bf, ts, nbad, + 0, false); + ath_tx_complete_buf(sc, bf, txq, -+ &bf_head, ts, 0, 0); ++ &bf_head, ++ ts, 0, 0); + break; + } - -- bf->bf_state.bf_type |= BUF_XRETRY; -- ath_tx_rc_status(bf, ts, nbad, -- 0, false); -- ath_tx_complete_buf(sc, bf, txq, -- &bf_head, ts, 0, 0); -- break; -+ ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); ++ ++ ath9k_hw_cleartxdesc(sc->sc_ah, ++ tbf->bf_desc); + list_add_tail(&tbf->list, &bf_head); + } else { + /* + * Clear descriptor status words for + * software retry + */ -+ ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); ++ ath9k_hw_cleartxdesc(sc->sc_ah, ++ bf->bf_desc); } - - ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); @@ -34845,7 +34976,7 @@ } /* -@@ -665,7 +666,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_ +@@ -665,7 +673,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_ bpad = PADBYTES(al_delta) + (ndelim << 2); bf->bf_next = NULL; @@ -34854,7 +34985,7 @@ /* link buffers of this frame to the aggregate */ ath_tx_addto_baw(sc, tid, bf); -@@ -673,7 +674,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_ +@@ -673,7 +681,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_ list_move_tail(&bf->list, bf_q); if (bf_prev) { bf_prev->bf_next = bf; @@ -34864,7 +34995,7 @@ } bf_prev = bf; -@@ -853,7 +855,7 @@ struct ath_txq *ath_txq_setup(struct ath +@@ -853,7 +862,7 @@ struct ath_txq *ath_txq_setup(struct ath struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); struct ath9k_tx_queue_info qi; @@ -34873,7 +35004,7 @@ memset(&qi, 0, sizeof(qi)); qi.tqi_subtype = subtype; -@@ -877,11 +879,16 @@ struct ath_txq *ath_txq_setup(struct ath +@@ -877,11 +886,16 @@ struct ath_txq *ath_txq_setup(struct ath * The UAPSD queue is an exception, since we take a desc- * based intr on the EOSP frames. */ @@ -34895,7 +35026,7 @@ qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); if (qnum == -1) { /* -@@ -908,6 +915,11 @@ struct ath_txq *ath_txq_setup(struct ath +@@ -908,6 +922,11 @@ struct ath_txq *ath_txq_setup(struct ath txq->axq_depth = 0; txq->axq_tx_inprogress = false; sc->tx.txqsetup |= 1<<qnum; @@ -34907,7 +35038,7 @@ } return &sc->tx.txq[qnum]; } -@@ -1035,36 +1047,64 @@ void ath_draintxq(struct ath_softc *sc, +@@ -1035,36 +1054,54 @@ void ath_draintxq(struct ath_softc *sc, struct ath_tx_status ts; memset(&ts, 0, sizeof(ts)); @@ -34924,28 +35055,16 @@ - spin_unlock_bh(&txq->axq_lock); - break; - } +- +- bf = list_first_entry(&txq->axq_q, struct ath_buf, list); + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { -+ if (list_empty(&txq->txq_fifo_pending)) { -+ txq->txq_headidx = txq->txq_tailidx = 0; -+ spin_unlock_bh(&txq->axq_lock); -+ break; -+ } - -- bf = list_first_entry(&txq->axq_q, struct ath_buf, list); -+ bf = list_first_entry(&txq->txq_fifo_pending, -+ struct ath_buf, list); - -- if (bf->bf_stale) { -- list_del(&bf->list); -- spin_unlock_bh(&txq->axq_lock); -+ list_cut_position( -+ &txq->txq_fifo[txq->txq_tailidx], -+ &txq->txq_fifo_pending, -+ &bf->bf_lastbf->list); ++ txq->txq_headidx = txq->txq_tailidx = 0; ++ spin_unlock_bh(&txq->axq_lock); ++ break; + } else { + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], -+ struct ath_buf, list); ++ struct ath_buf, list); + } + } else { + if (list_empty(&txq->axq_q)) { @@ -34956,14 +35075,17 @@ + bf = list_first_entry(&txq->axq_q, struct ath_buf, + list); +- if (bf->bf_stale) { +- list_del(&bf->list); +- spin_unlock_bh(&txq->axq_lock); ++ if (bf->bf_stale) { ++ list_del(&bf->list); ++ spin_unlock_bh(&txq->axq_lock); + - spin_lock_bh(&sc->tx.txbuflock); - list_add_tail(&bf->list, &sc->tx.txbuf); - spin_unlock_bh(&sc->tx.txbuflock); - continue; -+ if (bf->bf_stale) { -+ list_del(&bf->list); -+ spin_unlock_bh(&txq->axq_lock); -+ + spin_lock_bh(&sc->tx.txbuflock); + list_add_tail(&bf->list, &sc->tx.txbuf); + spin_unlock_bh(&sc->tx.txbuflock); @@ -34990,7 +35112,35 @@ txq->axq_depth--; spin_unlock_bh(&txq->axq_lock); -@@ -1224,25 +1264,46 @@ static void ath_tx_txqaddbuf(struct ath_ +@@ -1087,6 +1124,27 @@ void ath_draintxq(struct ath_softc *sc, + spin_unlock_bh(&txq->axq_lock); + } + } ++ ++ if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { ++ spin_lock_bh(&txq->axq_lock); ++ while (!list_empty(&txq->txq_fifo_pending)) { ++ bf = list_first_entry(&txq->txq_fifo_pending, ++ struct ath_buf, list); ++ list_cut_position(&bf_head, ++ &txq->txq_fifo_pending, ++ &bf->bf_lastbf->list); ++ spin_unlock_bh(&txq->axq_lock); ++ ++ if (bf_isampdu(bf)) ++ ath_tx_complete_aggr(sc, txq, bf, &bf_head, ++ &ts, 0); ++ else ++ ath_tx_complete_buf(sc, bf, txq, &bf_head, ++ &ts, 0, 0); ++ spin_lock_bh(&txq->axq_lock); ++ } ++ spin_unlock_bh(&txq->axq_lock); ++ } + } + + void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) +@@ -1224,25 +1282,47 @@ static void ath_tx_txqaddbuf(struct ath_ bf = list_first_entry(head, struct ath_buf, list); @@ -35008,7 +35158,8 @@ + } + if (!list_empty(&txq->txq_fifo[txq->txq_headidx])) + ath_print(common, ATH_DBG_XMIT, -+ "Initializing tx fifo %d which is non-empty\n", ++ "Initializing tx fifo %d which " ++ "is non-empty\n", + txq->txq_headidx); + INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]); + list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]); @@ -35047,7 +35198,7 @@ } static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) -@@ -1408,8 +1469,7 @@ static void assign_aggr_tid_seqno(struct +@@ -1408,8 +1488,7 @@ static void assign_aggr_tid_seqno(struct INCR(tid->seq_next, IEEE80211_SEQ_MAX); } @@ -35057,7 +35208,7 @@ { struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); int flags = 0; -@@ -1420,6 +1480,9 @@ static int setup_tx_flags(struct ath_sof +@@ -1420,6 +1499,9 @@ static int setup_tx_flags(struct ath_sof if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) flags |= ATH9K_TXDESC_NOACK; @@ -35067,7 +35218,7 @@ return flags; } -@@ -1571,6 +1634,7 @@ static int ath_tx_setup_buffer(struct ie +@@ -1571,6 +1653,7 @@ static int ath_tx_setup_buffer(struct ie int hdrlen; __le16 fc; int padpos, padsize; @@ -35075,7 +35226,7 @@ tx_info->pad[0] = 0; switch (txctl->frame_type) { -@@ -1597,10 +1661,13 @@ static int ath_tx_setup_buffer(struct ie +@@ -1597,10 +1680,13 @@ static int ath_tx_setup_buffer(struct ie bf->bf_frmlen -= padsize; } @@ -35091,7 +35242,7 @@ bf->bf_keytype = get_hw_crypto_keytype(skb); if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { -@@ -1659,8 +1726,7 @@ static void ath_tx_start_dma(struct ath_ +@@ -1659,8 +1745,7 @@ static void ath_tx_start_dma(struct ath_ list_add_tail(&bf->list, &bf_head); ds = bf->bf_desc; @@ -35101,7 +35252,7 @@ ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, bf->bf_keyix, bf->bf_keytype, bf->bf_flags); -@@ -1669,7 +1735,9 @@ static void ath_tx_start_dma(struct ath_ +@@ -1669,7 +1754,9 @@ static void ath_tx_start_dma(struct ath_ skb->len, /* segment length */ true, /* first segment */ true, /* last segment */ @@ -35112,7 +35263,7 @@ spin_lock_bh(&txctl->txq->axq_lock); -@@ -1896,7 +1964,7 @@ static int ath_tx_num_badfrms(struct ath +@@ -1896,7 +1983,7 @@ static int ath_tx_num_badfrms(struct ath int nbad = 0; int isaggr = 0; @@ -35121,7 +35272,7 @@ return 0; isaggr = bf_isaggr(bf); -@@ -2138,10 +2206,119 @@ void ath_tx_tasklet(struct ath_softc *sc +@@ -2138,10 +2225,119 @@ void ath_tx_tasklet(struct ath_softc *sc } } @@ -35241,7 +35392,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs) { struct ath_common *common = ath9k_hw_common(sc->sc_ah); -@@ -2150,7 +2327,7 @@ int ath_tx_init(struct ath_softc *sc, in +@@ -2150,7 +2346,7 @@ int ath_tx_init(struct ath_softc *sc, in spin_lock_init(&sc->tx.txbuflock); error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, @@ -35250,7 +35401,7 @@ if (error != 0) { ath_print(common, ATH_DBG_FATAL, "Failed to allocate tx descriptors: %d\n", error); -@@ -2158,7 +2335,7 @@ int ath_tx_init(struct ath_softc *sc, in +@@ -2158,7 +2354,7 @@ int ath_tx_init(struct ath_softc *sc, in } error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, @@ -35259,7 +35410,7 @@ if (error != 0) { ath_print(common, ATH_DBG_FATAL, "Failed to allocate beacon descriptors: %d\n", error); -@@ -2167,6 +2344,12 @@ int ath_tx_init(struct ath_softc *sc, in +@@ -2167,6 +2363,12 @@ int ath_tx_init(struct ath_softc *sc, in INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); @@ -35272,7 +35423,7 @@ err: if (error != 0) ath_tx_cleanup(sc); -@@ -2181,6 +2364,9 @@ void ath_tx_cleanup(struct ath_softc *sc +@@ -2181,6 +2383,9 @@ void ath_tx_cleanup(struct ath_softc *sc if (sc->tx.txdma.dd_desc_len != 0) ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); diff --git a/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch b/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch index 8098b22e23..f5d7d554f5 100644 --- a/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch +++ b/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch @@ -8,7 +8,7 @@ #include <asm/unaligned.h> #include "hw.h" -@@ -431,8 +432,16 @@ static int ath9k_hw_init_macaddr(struct +@@ -440,8 +441,16 @@ static int ath9k_hw_init_macaddr(struct common->macaddr[2 * i] = eeval >> 8; common->macaddr[2 * i + 1] = eeval & 0xff; } diff --git a/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch b/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch index 19a29d916f..55d5569fbf 100644 --- a/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch +++ b/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch @@ -31,7 +31,7 @@ common->bus_ops = bus_ops; --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c -@@ -404,10 +404,6 @@ static void ath9k_hw_init_defaults(struc +@@ -413,10 +413,6 @@ static void ath9k_hw_init_defaults(struc ah->hw_version.magic = AR5416_MAGIC; ah->hw_version.subvendorid = 0; diff --git a/package/mac80211/patches/407-ath9k-override-mac-address-from-platform-data.patch b/package/mac80211/patches/407-ath9k-override-mac-address-from-platform-data.patch index 999ced42d6..7b62a46ac3 100644 --- a/package/mac80211/patches/407-ath9k-override-mac-address-from-platform-data.patch +++ b/package/mac80211/patches/407-ath9k-override-mac-address-from-platform-data.patch @@ -11,7 +11,7 @@ #include "hw.h" #include "hw-ops.h" #include "rc.h" -@@ -416,18 +418,23 @@ static void ath9k_hw_init_defaults(struc +@@ -425,18 +427,23 @@ static void ath9k_hw_init_defaults(struc static int ath9k_hw_init_macaddr(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); diff --git a/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch b/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch index 2d3f9246ec..33a036969f 100644 --- a/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch +++ b/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c -@@ -1298,7 +1298,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st +@@ -1303,7 +1303,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st if (ah->config.rx_intr_mitigation) { REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); diff --git a/package/mac80211/patches/550-ath9k_bb_fix.patch b/package/mac80211/patches/550-ath9k_bb_fix.patch index 0cfb6cf655..c129f538e5 100644 --- a/package/mac80211/patches/550-ath9k_bb_fix.patch +++ b/package/mac80211/patches/550-ath9k_bb_fix.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c -@@ -1131,6 +1131,34 @@ static bool ath9k_hw_channel_change(stru +@@ -1136,6 +1136,34 @@ static bool ath9k_hw_channel_change(stru return true; } @@ -37,7 +37,7 @@ { --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h -@@ -846,6 +846,7 @@ void ath9k_hw_set11nmac2040(struct ath_h +@@ -851,6 +851,7 @@ void ath9k_hw_set11nmac2040(struct ath_h void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs); diff --git a/package/mac80211/patches/560-ath9k_tx_buf_return_cleanup.patch b/package/mac80211/patches/560-ath9k_tx_buf_return_cleanup.patch index 2d5fb0aa85..a2ccf23e7c 100644 --- a/package/mac80211/patches/560-ath9k_tx_buf_return_cleanup.patch +++ b/package/mac80211/patches/560-ath9k_tx_buf_return_cleanup.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c -@@ -260,19 +260,40 @@ static void ath_tx_set_retry(struct ath_ +@@ -261,19 +261,40 @@ static void ath_tx_set_retry(struct ath_ hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); } @@ -46,7 +46,7 @@ ATH_TXBUF_RESET(tbf); tbf->aphy = bf->aphy; -@@ -1084,9 +1105,7 @@ void ath_draintxq(struct ath_softc *sc, +@@ -1081,9 +1102,7 @@ void ath_draintxq(struct ath_softc *sc, list_del(&bf->list); spin_unlock_bh(&txq->axq_lock); @@ -57,7 +57,7 @@ continue; } } -@@ -1306,25 +1325,6 @@ static void ath_tx_txqaddbuf(struct ath_ +@@ -1325,25 +1344,6 @@ static void ath_tx_txqaddbuf(struct ath_ txq->axq_depth++; } @@ -83,7 +83,7 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, struct list_head *bf_head, struct ath_tx_control *txctl) -@@ -1806,9 +1806,7 @@ int ath_tx_start(struct ieee80211_hw *hw +@@ -1825,9 +1825,7 @@ int ath_tx_start(struct ieee80211_hw *hw } spin_unlock_bh(&txq->axq_lock); @@ -94,7 +94,7 @@ return r; } -@@ -2122,13 +2120,12 @@ static void ath_tx_processq(struct ath_s +@@ -2141,13 +2139,12 @@ static void ath_tx_processq(struct ath_s txq->axq_depth--; txok = !(ts.ts_status & ATH9K_TXERR_MASK); txq->axq_tx_inprogress = false; |