diff options
Diffstat (limited to 'package/kernel/mac80211/patches/334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch')
| -rw-r--r-- | package/kernel/mac80211/patches/334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch b/package/kernel/mac80211/patches/334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch new file mode 100644 index 0000000000..f26e059cf0 --- /dev/null +++ b/package/kernel/mac80211/patches/334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch @@ -0,0 +1,67 @@ +From: Oleksij Rempel <linux@rempel-privat.de> +Date: Sun, 22 Mar 2015 19:30:03 +0100 +Subject: [PATCH] ath9k: use REG_RMW and rmw buffer in + ath9k_hw_def_set_gain + +Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> +Signed-off-by: Kalle Valo <kvalo@codeaurora.org> +--- + +--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c ++++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c +@@ -466,6 +466,7 @@ static void ath9k_hw_def_set_gain(struct + struct ar5416_eeprom_def *eep, + u8 txRxAttenLocal, int regChainOffset, int i) + { ++ ENABLE_REG_RMW_BUFFER(ah); + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { + txRxAttenLocal = pModal->txRxAttenCh[i]; + +@@ -483,16 +484,12 @@ static void ath9k_hw_def_set_gain(struct + AR_PHY_GAIN_2GHZ_XATTEN2_DB, + pModal->xatten2Db[i]); + } else { +- REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, +- (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & +- ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) +- | SM(pModal-> bswMargin[i], +- AR_PHY_GAIN_2GHZ_BSW_MARGIN)); +- REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, +- (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & +- ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) +- | SM(pModal->bswAtten[i], +- AR_PHY_GAIN_2GHZ_BSW_ATTEN)); ++ REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, ++ SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN), ++ AR_PHY_GAIN_2GHZ_BSW_MARGIN); ++ REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, ++ SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN), ++ AR_PHY_GAIN_2GHZ_BSW_ATTEN); + } + } + +@@ -504,17 +501,14 @@ static void ath9k_hw_def_set_gain(struct + AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); + } else { +- REG_WRITE(ah, +- AR_PHY_RXGAIN + regChainOffset, +- (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & +- ~AR_PHY_RXGAIN_TXRX_ATTEN) +- | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN)); +- REG_WRITE(ah, +- AR_PHY_GAIN_2GHZ + regChainOffset, +- (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & +- ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | +- SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); ++ REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset, ++ SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN), ++ AR_PHY_RXGAIN_TXRX_ATTEN); ++ REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, ++ SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN), ++ AR_PHY_GAIN_2GHZ_RXTX_MARGIN); + } ++ REG_RMW_BUFFER_FLUSH(ah); + } + + static void ath9k_hw_def_set_board_values(struct ath_hw *ah, |