diff options
Diffstat (limited to 'package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch')
| -rw-r--r-- | package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch new file mode 100644 index 0000000000..f14c383638 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch @@ -0,0 +1,49 @@ +From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Wed, 19 Jul 2023 17:16:33 +0800 +Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek + MT7988 SoC + +This patch adds reset bits for MediaTek MT7988 + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + create mode 100644 include/dt-bindings/reset/mt7988-reset.h + +--- /dev/null ++++ b/include/dt-bindings/reset/mt7988-reset.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 MediaTek Inc. ++ */ ++ ++#ifndef _DT_BINDINGS_MTK_RESET_H_ ++#define _DT_BINDINGS_MTK_RESET_H_ ++ ++/* ETHDMA Subsystem resets */ ++#define ETHDMA_FE_RST 6 ++#define ETHDMA_PMTR_RST 8 ++#define ETHDMA_GMAC_RST 23 ++#define ETHDMA_WDMA0_RST 24 ++#define ETHDMA_WDMA1_RST 25 ++#define ETHDMA_WDMA2_RST 26 ++#define ETHDMA_PPE0_RST 29 ++#define ETHDMA_PPE1_RST 30 ++#define ETHDMA_PPE2_RST 31 ++ ++/* ETHWARP Subsystem resets */ ++#define ETHWARP_GSW_RST 9 ++#define ETHWARP_EIP197_RST 10 ++#define ETHWARP_WOCPU0_RST 32 ++#define ETHWARP_WOCPU1_RST 33 ++#define ETHWARP_WOCPU2_RST 34 ++#define ETHWARP_WOX_NET_MUX_RST 35 ++#define ETHWARP_WED0_RST 36 ++#define ETHWARP_WED1_RST 37 ++#define ETHWARP_WED2_RST 38 ++ ++#endif /* _DT_BINDINGS_MTK_RESET_H_ */ |