diff options
Diffstat (limited to 'package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch')
| -rw-r--r-- | package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch index f84fdec2b4..6475dde388 100644 --- a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch +++ b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch @@ -1,16 +1,16 @@ -From e9c0c2ebd346aa578007c2aa88fc0974af6afb40 Mon Sep 17 00:00:00 2001 +From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> -Date: Fri, 29 Jul 2022 11:14:33 +0800 -Subject: [PATCH 24/31] clk: mediatek: add infrasys clock mux support +Date: Wed, 31 Aug 2022 19:05:09 +0800 +Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support This patch adds infrasys clock mux support for mediatek clock drivers. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- - drivers/clk/mediatek/clk-mtk.c | 72 ++++++++++++++++++++++++++++++++++ + drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 4 +- - 2 files changed, 75 insertions(+), 1 deletion(-) + 2 files changed, 74 insertions(+), 1 deletion(-) --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -332,6 +350,34 @@ static ulong mtk_topckgen_get_mux_rate(s +@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s return priv->tree->xtal_rate; } @@ -48,15 +48,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + u32 index; -+ u32 flag; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + -+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) -+ flag = 1; -+ if (mux->parent[index] > 0 || flag == 1) { ++ if (mux->parent[index] > 0 || ++ (mux->parent[index] == CLK_XTAL && ++ priv->tree->flags & CLK_BYPASS_XTAL)) { + switch (mux->flags & CLK_PARENT_MASK) { + case CLK_PARENT_TOPCKGEN: + return mtk_clk_find_parent_rate(clk, mux->parent[index], @@ -74,7 +73,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -346,6 +392,25 @@ static ulong mtk_topckgen_get_rate(struc +@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc priv->tree->muxes_offs); } @@ -100,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static int mtk_clk_mux_enable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -494,6 +559,13 @@ const struct clk_ops mtk_clk_topckgen_op +@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op .set_parent = mtk_common_clk_set_parent, }; |