1 files changed, 0 insertions, 63 deletions
diff --git a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch b/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch
deleted file mode 100644
index b9f0954401..0000000000
--- a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 907d65c5020fefc9944ec57a9e0bd66dc648823e Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 31 Aug 2022 19:04:59 +0800
-Subject: [PATCH 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
- bypassing searching clock parent of xtal clock
-
-The mtk clock framework in u-boot uses array index for searching clock
-parent (kernel uses strings for search), so we need to specify a special
-clock with ID=0 for CLK_XTAL in u-boot.
-
-In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
-mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
-expected.
-
-However for newer chips, they may have some clocks with ID=0 not
-representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
-called. Current logic will make entire clock driver not working.
-
-This patch adds a flag to indicate that whether a clock driver needs clocks
-with ID=0 to call mtk_topckgen_get_mux_rate.
-
-Reviewed-by: Simon Glass <sjg@chromium.org>
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/clk/mediatek/clk-mtk.c | 4 +++-
- drivers/clk/mediatek/clk-mtk.h | 6 ++++++
- 2 files changed, 9 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(s
- 	index &= mux->mux_mask << mux->mux_shift;
- 	index = index >> mux->mux_shift;
- 
--	if (mux->parent[index])
-+	if (mux->parent[index] > 0 ||
-+	    (mux->parent[index] == CLK_XTAL &&
-+	     priv->tree->flags & CLK_BYPASS_XTAL))
- 		return mtk_clk_find_parent_rate(clk, mux->parent[index],
- 						NULL);
- 
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -11,6 +11,11 @@
- #define CLK_XTAL			0
- #define MHZ				(1000 * 1000)
- 
-+/* flags in struct mtk_clk_tree */
-+
-+/* clk id == 0 doesn't mean it's xtal clk */
-+#define CLK_BYPASS_XTAL			BIT(0)
-+
- #define HAVE_RST_BAR			BIT(0)
- #define CLK_DOMAIN_SCPSYS		BIT(0)
- #define CLK_MUX_SETCLR_UPD		BIT(1)
-@@ -197,6 +202,7 @@ struct mtk_clk_tree {
- 	const struct mtk_fixed_clk *fclks;
- 	const struct mtk_fixed_factor *fdivs;
- 	const struct mtk_composite *muxes;
-+	u32 flags;
- };
- 
- struct mtk_clk_priv {