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Diffstat (limited to 'package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch')
-rw-r--r--package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch462
1 files changed, 0 insertions, 462 deletions
diff --git a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch
deleted file mode 100644
index 425f0de1b4..0000000000
--- a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch
+++ /dev/null
@@ -1,462 +0,0 @@
-From 5512a2e8257b0a733cf90ec247f34094ff31f750 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 31 Aug 2022 19:00:20 +0800
-Subject: [PATCH 02/32] arm: mediatek: add support for MediaTek MT7981 SoC
-
-This patch adds basic support for MediaTek MT7981 SoC.
-This include the file that will initialize the SoC after boot and its
-device tree.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- arch/arm/dts/mt7981.dtsi | 293 ++++++++++++++++++
- arch/arm/mach-mediatek/Kconfig | 13 +-
- arch/arm/mach-mediatek/Makefile | 1 +
- arch/arm/mach-mediatek/mt7981/Makefile | 4 +
- arch/arm/mach-mediatek/mt7981/init.c | 45 +++
- arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 ++
- 6 files changed, 387 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/dts/mt7981.dtsi
- create mode 100644 arch/arm/mach-mediatek/mt7981/Makefile
- create mode 100644 arch/arm/mach-mediatek/mt7981/init.c
- create mode 100644 arch/arm/mach-mediatek/mt7981/lowlevel_init.S
-
---- /dev/null
-+++ b/arch/arm/dts/mt7981.dtsi
-@@ -0,0 +1,293 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/clock/mt7981-clk.h>
-+#include <dt-bindings/reset/mt7629-reset.h>
-+#include <dt-bindings/pinctrl/mt65xx.h>
-+
-+/ {
-+ compatible = "mediatek,mt7981";
-+ interrupt-parent = <&gic>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ cpu0: cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a53";
-+ reg = <0x0>;
-+ };
-+ cpu1: cpu@1 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a53";
-+ reg = <0x1>;
-+ };
-+ };
-+
-+ gpt_clk: gpt_dummy20m {
-+ compatible = "fixed-clock";
-+ clock-frequency = <13000000>;
-+ #clock-cells = <0>;
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ hwver: hwver {
-+ compatible = "mediatek,hwver";
-+ reg = <0x8000000 0x1000>;
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupt-parent = <&gic>;
-+ clock-frequency = <13000000>;
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+ arm,cpu-registers-not-fw-configured;
-+ };
-+
-+ timer0: timer@10008000 {
-+ compatible = "mediatek,mt7986-timer";
-+ reg = <0x10008000 0x1000>;
-+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gpt_clk>;
-+ clock-names = "gpt-clk";
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ watchdog: watchdog@1001c000 {
-+ compatible = "mediatek,mt7986-wdt";
-+ reg = <0x1001c000 0x1000>;
-+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+ #reset-cells = <1>;
-+ status = "disabled";
-+ };
-+
-+ gic: interrupt-controller@c000000 {
-+ compatible = "arm,gic-v3";
-+ #interrupt-cells = <3>;
-+ interrupt-parent = <&gic>;
-+ interrupt-controller;
-+ reg = <0x0c000000 0x40000>, /* GICD */
-+ <0x0c080000 0x200000>; /* GICR */
-+
-+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ fixed_plls: apmixedsys@1001e000 {
-+ compatible = "mediatek,mt7981-fixed-plls";
-+ reg = <0x1001e000 0x1000>;
-+ #clock-cells = <1>;
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ topckgen: topckgen@1001b000 {
-+ compatible = "mediatek,mt7981-topckgen";
-+ reg = <0x1001b000 0x1000>;
-+ clock-parent = <&fixed_plls>;
-+ #clock-cells = <1>;
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ infracfg_ao: infracfg_ao@10001000 {
-+ compatible = "mediatek,mt7981-infracfg_ao";
-+ reg = <0x10001000 0x80>;
-+ clock-parent = <&infracfg>;
-+ #clock-cells = <1>;
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ infracfg: infracfg@10001000 {
-+ compatible = "mediatek,mt7981-infracfg";
-+ reg = <0x10001000 0x30>;
-+ clock-parent = <&topckgen>;
-+ #clock-cells = <1>;
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ pinctrl: pinctrl@11d00000 {
-+ compatible = "mediatek,mt7981-pinctrl";
-+ reg = <0x11d00000 0x1000>,
-+ <0x11c00000 0x1000>,
-+ <0x11c10000 0x1000>,
-+ <0x11d20000 0x1000>,
-+ <0x11e00000 0x1000>,
-+ <0x11e20000 0x1000>,
-+ <0x11f00000 0x1000>,
-+ <0x11f10000 0x1000>,
-+ <0x1000b000 0x1000>;
-+ reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
-+ "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
-+ "iocfg_tm_base", "iocfg_tl_base", "eint";
-+ gpio: gpio-controller {
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
-+ };
-+
-+ pwm: pwm@10048000 {
-+ compatible = "mediatek,mt7981-pwm";
-+ reg = <0x10048000 0x1000>;
-+ #clock-cells = <1>;
-+ #pwm-cells = <2>;
-+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg CK_INFRA_PWM>,
-+ <&infracfg_ao CK_INFRA_PWM_BSEL>,
-+ <&infracfg_ao CK_INFRA_PWM1_CK>,
-+ <&infracfg_ao CK_INFRA_PWM2_CK>,
-+ /* FIXME */
-+ <&infracfg_ao CK_INFRA_PWM2_CK>;
-+ assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
-+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
-+ status = "disabled";
-+ };
-+
-+ uart0: serial@11002000 {
-+ compatible = "mediatek,hsuart";
-+ reg = <0x11002000 0x400>;
-+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
-+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+ <&infracfg_ao CK_INFRA_UART0_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+ <&infracfg CK_INFRA_UART>;
-+ mediatek,force-highspeed;
-+ status = "disabled";
-+ u-boot,dm-pre-reloc;
-+ };
-+
-+ uart1: serial@11003000 {
-+ compatible = "mediatek,hsuart";
-+ reg = <0x11003000 0x400>;
-+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
-+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+ <&infracfg_ao CK_INFRA_UART1_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+ <&infracfg CK_INFRA_UART>;
-+ mediatek,force-highspeed;
-+ status = "disabled";
-+ };
-+
-+ uart2: serial@11004000 {
-+ compatible = "mediatek,hsuart";
-+ reg = <0x11004000 0x400>;
-+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
-+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-+ <&infracfg_ao CK_INFRA_UART2_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
-+ <&infracfg CK_INFRA_UART>;
-+ mediatek,force-highspeed;
-+ status = "disabled";
-+ };
-+
-+ snand: snand@11005000 {
-+ compatible = "mediatek,mt7986-snand";
-+ reg = <0x11005000 0x1000>,
-+ <0x11006000 0x1000>;
-+ reg-names = "nfi", "ecc";
-+ clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
-+ <&infracfg_ao CK_INFRA_NFI1_CK>,
-+ <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
-+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
-+ <&topckgen CK_TOP_NFI1X_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
-+ <&topckgen CK_TOP_CB_M_D8>;
-+ status = "disabled";
-+ };
-+
-+ ethsys: syscon@15000000 {
-+ compatible = "mediatek,mt7981-ethsys", "syscon";
-+ reg = <0x15000000 0x1000>;
-+ clock-parent = <&topckgen>;
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
-+
-+ eth: ethernet@15100000 {
-+ compatible = "mediatek,mt7981-eth", "syscon";
-+ reg = <0x15100000 0x20000>;
-+ resets = <&ethsys ETHSYS_FE_RST>;
-+ reset-names = "fe";
-+ mediatek,ethsys = <&ethsys>;
-+ mediatek,sgmiisys = <&sgmiisys0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ sgmiisys0: syscon@10060000 {
-+ compatible = "mediatek,mt7986-sgmiisys", "syscon";
-+ reg = <0x10060000 0x1000>;
-+ pn_swap;
-+ #clock-cells = <1>;
-+ };
-+
-+ sgmiisys1: syscon@10070000 {
-+ compatible = "mediatek,mt7986-sgmiisys", "syscon";
-+ reg = <0x10070000 0x1000>;
-+ #clock-cells = <1>;
-+ };
-+
-+ spi0: spi@1100a000 {
-+ compatible = "mediatek,ipm-spi";
-+ reg = <0x1100a000 0x100>;
-+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
-+ <&topckgen CK_TOP_SPI_SEL>;
-+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
-+ <&infracfg CK_INFRA_SPI0_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
-+ <&topckgen CK_INFRA_ISPI0>;
-+ clock-names = "sel-clk", "spi-clk";
-+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ spi1: spi@1100b000 {
-+ compatible = "mediatek,ipm-spi";
-+ reg = <0x1100b000 0x100>;
-+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ spi2: spi@11009000 {
-+ compatible = "mediatek,ipm-spi";
-+ reg = <0x11009000 0x100>;
-+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
-+ <&topckgen CK_TOP_SPI_SEL>;
-+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
-+ <&infracfg CK_INFRA_SPI0_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
-+ <&topckgen CK_INFRA_ISPI0>;
-+ clock-names = "sel-clk", "spi-clk";
-+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ mmc0: mmc@11230000 {
-+ compatible = "mediatek,mt7981-mmc";
-+ reg = <0x11230000 0x1000>,
-+ <0x11C20000 0x1000>;
-+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&topckgen CK_TOP_EMMC_400M>,
-+ <&topckgen CK_TOP_EMMC_208M>,
-+ <&infracfg_ao CK_INFRA_MSDC_CK>;
-+ assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
-+ <&topckgen CK_TOP_EMMC_208M_SEL>;
-+ assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
-+ <&topckgen CK_TOP_CB_M_D2>;
-+ clock-names = "source", "hclk", "source_cg";
-+ status = "disabled";
-+ };
-+
-+};
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -40,6 +40,15 @@ config TARGET_MT7629
- including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
- switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
-
-+config TARGET_MT7981
-+ bool "MediaTek MT7981 SoC"
-+ select ARM64
-+ select CPU
-+ help
-+ The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53.
-+ including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C,
-+ built-in Wi-Fi, and PCIe.
-+
- config TARGET_MT7986
- bool "MediaTek MT7986 SoC"
- select ARM64
-@@ -93,6 +102,7 @@ config SYS_BOARD
- default "mt7622" if TARGET_MT7622
- default "mt7623" if TARGET_MT7623
- default "mt7629" if TARGET_MT7629
-+ default "mt7981" if TARGET_MT7981
- default "mt7986" if TARGET_MT7986
- default "mt8183" if TARGET_MT8183
- default "mt8512" if TARGET_MT8512
-@@ -109,6 +119,7 @@ config SYS_CONFIG_NAME
- default "mt7622" if TARGET_MT7622
- default "mt7623" if TARGET_MT7623
- default "mt7629" if TARGET_MT7629
-+ default "mt7981" if TARGET_MT7981
- default "mt7986" if TARGET_MT7986
- default "mt8183" if TARGET_MT8183
- default "mt8512" if TARGET_MT8512
-@@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO
- string
- default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
-- default "media=snand;nandinfo=2k+64" if TARGET_MT7986
-+ default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
- default "lk=1" if TARGET_MT7623
-
- endif
---- a/arch/arm/mach-mediatek/Makefile
-+++ b/arch/arm/mach-mediatek/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
- obj-$(CONFIG_TARGET_MT7622) += mt7622/
- obj-$(CONFIG_TARGET_MT7623) += mt7623/
- obj-$(CONFIG_TARGET_MT7629) += mt7629/
-+obj-$(CONFIG_TARGET_MT7981) += mt7981/
- obj-$(CONFIG_TARGET_MT7986) += mt7986/
- obj-$(CONFIG_TARGET_MT8183) += mt8183/
- obj-$(CONFIG_TARGET_MT8516) += mt8516/
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7981/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+obj-y += init.o
-+obj-y += lowlevel_init.o
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7981/init.c
-@@ -0,0 +1,45 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include <init.h>
-+#include <asm/armv8/mmu.h>
-+#include <asm/system.h>
-+#include <asm/global_data.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int dram_init(void)
-+{
-+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
-+
-+ return 0;
-+}
-+
-+void reset_cpu(ulong addr)
-+{
-+ psci_system_reset();
-+}
-+
-+static struct mm_region mt7981_mem_map[] = {
-+ {
-+ /* DDR */
-+ .virt = 0x40000000UL,
-+ .phys = 0x40000000UL,
-+ .size = 0x80000000UL,
-+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
-+ }, {
-+ .virt = 0x00000000UL,
-+ .phys = 0x00000000UL,
-+ .size = 0x40000000UL,
-+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+ PTE_BLOCK_NON_SHARE |
-+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+ }, {
-+ 0,
-+ }
-+};
-+
-+struct mm_region *mem_map = mt7981_mem_map;
---- /dev/null
-+++ b/arch/arm/mach-mediatek/mt7981/lowlevel_init.S
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2022 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+/*
-+ * Switch from AArch64 EL2 to AArch32 EL2
-+ * @param inputs:
-+ * x0: argument, zero
-+ * x1: machine nr
-+ * x2: fdt address
-+ * x3: input argument
-+ * x4: kernel entry point
-+ * @param outputs for secure firmware:
-+ * x0: function id
-+ * x1: kernel entry point
-+ * x2: machine nr
-+ * x3: fdt address
-+ *
-+ * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c
-+*/
-+
-+.global armv8_el2_to_aarch32
-+armv8_el2_to_aarch32:
-+ mov x3, x2
-+ mov x2, x1
-+ mov x1, x4
-+ mov x4, #0
-+ ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */
-+ SMC #0
-+ ret
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 19:35:58 +0000