diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch b/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch deleted file mode 100644 index 33ea668526..0000000000 --- a/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001 -From: Sumit Garg <sumit.garg@nxp.com> -Date: Wed, 11 May 2016 12:44:35 -0400 -Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency - -Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. -The SMPEN bit should be set before enabling the data cache. If not -enabled, the cache is not coherent with other cores and data -corruption could occur. It also enables core level cache snooping. - -Signed-off-by: Sumit Garg <sumit.garg@nxp.com> ---- - arch/arm/cpu/armv8/start.S | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S -index 235213f..9703f6b 100644 ---- a/arch/arm/cpu/armv8/start.S -+++ b/arch/arm/cpu/armv8/start.S -@@ -70,6 +70,9 @@ reset: - mov x0, #3 << 20 - msr cpacr_el1, x0 /* Enable FP/SIMD */ - 0: -+ /* Enalbe SMPEN bit */ -+ mov x0, #0x40 -+ msr s3_1_c15_c2_1, x0 - - /* Apply ARM core specific erratas */ - bl apply_core_errata --- -1.7.9.5 - |